CN106057931B - Large open-circuit voltage nano heterojunction solar cell and preparation method thereof - Google Patents

Large open-circuit voltage nano heterojunction solar cell and preparation method thereof Download PDF

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CN106057931B
CN106057931B CN201610543913.7A CN201610543913A CN106057931B CN 106057931 B CN106057931 B CN 106057931B CN 201610543913 A CN201610543913 A CN 201610543913A CN 106057931 B CN106057931 B CN 106057931B
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substrate layer
circuit voltage
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CN106057931A (en
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张希威
孟丹
汤振杰
胡丹
于凤军
贾拴稳
牛晓平
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Anyang Normal University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042—PV modules or arrays of single PV cells
    • H01L31/0445—PV modules or arrays of single PV cells including thin film solar cells, e.g. single thin film a-Si, CIS or CdTe solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1828—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIBVI compounds, e.g. CdS, ZnS, CdTe
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/543—Solar cells from Group II-VI materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

The invention discloses a large open-circuit voltage nano heterojunction solar cell and a preparation method thereof. The semiconductor device comprises a substrate layer, a p-type semiconductor nanowire, a gold electrode, a passivation layer, an n-type semiconductor film and a titanium electrode. Firstly, transferring the p-type semiconductor nanowire onto a substrate layer; then depositing a gold electrode on one end of the p-type semiconductor nanowire by using a photoetching technology and a magnetron sputtering method; then adopting a photoetching technology and an atomic layer deposition method to deposit a passivation layer on the other end of the p-type semiconductor nanowire; depositing an n-type semiconductor film on the passivation layer by utilizing an atomic layer deposition method; and finally, depositing a titanium electrode on the n-type semiconductor film by using a magnetron sputtering method. The invention adopts a nano heterojunction structure, and realizes the large open-circuit voltage solar cell with the open-circuit voltage of more than 1V through the selection of materials, the optimization of the structure and the process.

Description

Large open-circuit voltage nano heterojunction solar cell and preparation method thereof
Technical field:
the invention relates to the field of nano solar cells, in particular to a large open-circuit voltage nano heterojunction solar cell and a preparation method thereof.
The background technology is as follows:
the world's general energy supply shortage crisis is becoming serious, the massive development and utilization of fossil energy has become one of the main reasons causing natural environment pollution and human living environment deterioration, and the search for emerging energy has become a world's hot spot problem. Among various new energy sources, solar photovoltaic power generation has the advantages of no pollution, sustainability, large total amount, wide distribution, various application forms and the like, and is highly valued in countries around the world.
Open circuit voltage is an important parameter characterizing solar cells. The large open-circuit voltage is the basis for obtaining high conversion efficiency, and can promote the absorption of high-energy photons so as to improve the utilization rate of sunlight. In addition, the large open circuit voltage is the basis of the large output voltage, which makes the large open circuit voltage solar cell have many special applications, such as a solar cell phone charger, etc. For the solar cell module, the large open-circuit voltage can reduce the number of serial devices, so that the cell volume is reduced, and the manufacture of the portable solar cell is easier to realize.
But the open circuit voltage of various solar cells is obviously lower at present. The open circuit voltage of monocrystalline silicon and polycrystalline silicon cells in the first generation solar cells is only about 0.7V, and the highest reported amorphous silicon cells are only 0.85V. The gallium arsenide cell and the cadmium telluride cell in the second generation thin film solar cell can improve the open circuit voltage to 1V and 0.85V due to the larger forbidden bandwidth, and the copper indium selenide and copper indium gallium selenide cells are only about 0.7V. Dye sensitized solar cells in the third generation are only about 0.73V. Thus, the long-term research and development investment does not improve the defects of low open circuit voltage of the various batteries.
The invention comprises the following steps:
aiming at the defects of the prior art, the invention provides a large open-circuit voltage nano heterojunction solar cell and a preparation method thereof, and aims to obtain the nano heterojunction solar cell with large open-circuit voltage.
In order to achieve the above object, the present invention provides a large open-circuit voltage nano heterojunction solar cell, which is characterized in that: the semiconductor nanowire comprises a substrate layer (1), wherein a p-type semiconductor nanowire (2) is arranged on the substrate layer (1), a gold electrode (3) is arranged on one end of the p-type semiconductor nanowire (2), a passivation layer (4) is arranged on the other end of the p-type semiconductor nanowire (2), an n-type semiconductor film (5) is arranged on the passivation layer (4), and a titanium electrode (6) is arranged on the n-type semiconductor film (5).
Preferably, the substrate layer (1) is quartz glass, a silicon wafer with an oxide layer, a sapphire substrate or a PET (Polyethylene terephthalate ) flexible substrate.
Preferably, the p-type semiconductor nanowire (2) is p-type selenizationZinc (ZnSe) nanowires; the diameter of the p-type semiconductor nanowire (2) is 150-250 nanometers, the length is 15-25 micrometers, and the hole concentration is 10 18 -10 19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The p-type semiconductor nanowires (2) are horizontally arranged on the substrate layer (1) in an array mode, and the parallel interval of the p-type semiconductor nanowires is 1-5 microns.
Preferably, the thickness of the gold electrode (3) is 50-100 nanometers.
Preferably, the passivation layer (4) is silicon nitride (Si 3 N 4 ) Or alumina (Al) 2 O 3 ) A layer; the thickness of the passivation layer (4) is 4-8 nanometers; and one end of the p-type semiconductor nanowire (2) is uniformly wrapped by the passivation layer (4).
Preferably, the n-type semiconductor thin film (5) is a n-type cadmium sulfide (CdS) thin film; the thickness of the n-type semiconductor film (5) is 40-100 nanometers.
Preferably, the thickness of the titanium electrode (6) is 20-40 nanometers.
In order to achieve the above object, the preparation method of the present invention comprises the steps of:
1) Transferring the p-type semiconductor nanowires onto a substrate layer to enable the p-type semiconductor nanowires to be distributed in a horizontal array;
2) Coating photoresist on the surface of a substrate layer, then placing the substrate layer in a photoetching machine, exposing and developing one end of a p-type semiconductor nanowire, placing the substrate layer in a magnetron sputtering instrument, depositing a gold electrode on the exposed end of the p-type semiconductor nanowire, and finally placing the substrate layer in an acetone solvent to dissolve the photoresist, thereby obtaining the p-type semiconductor nanowire with the gold electrode deposited on one end;
3) Coating photoresist on the surface of the substrate layer again, then placing the substrate layer in a photoetching machine, exposing and developing to expose the other end of the p-type semiconductor nanowire, placing the substrate layer in an atomic layer deposition device, and depositing a passivation layer on the exposed end of the p-type semiconductor nanowire;
4) Depositing an n-type semiconductor film over the passivation layer using atomic layer deposition:
4a) Placing the substrate layer of step 3) on atomic layer depositionThe reaction cavity is sealed and the pressure in the cavity is pumped to be less than 10 -4 Pa, and heating to maintain the temperature in the cavity at 130 ℃;
4b) With thioacetamide (H) 3 CCSNH 2 ) Powder and liquid dimethyl cadmium Cd (CH) 3 ) 2 As a precursor, nitrogen is used as carrier gas and purified gas, and thioacetamide is heated to 110 ℃ by using a heating sleeve;
4c) Introducing thioacetamide precursor to form a first monolayer of S on the surface of the passivation layer; then pumping out residual precursor and nitrogen by a mechanical pump after nitrogen is introduced and flushed;
4d) Introducing dimethyl cadmium to form a second monolayer of Cd on the first monolayer, wherein the first monolayer and the second monolayer form an S-Cd bond; pumping out residual precursor and nitrogen by a mechanical pump after nitrogen is introduced and flushed;
4e) Sequentially repeating the steps 4 c) and 4 d) for 600-1500 times to finish the deposition of the n-type semiconductor film;
5) Placing the substrate layer in the step 4) in a magnetron sputtering instrument, and depositing a titanium electrode on the n-type semiconductor film;
6) Placing the substrate layer in the step 5) in an acetone solvent to dissolve the photoresist;
7) Placing the substrate layer in the step 6) in a rapid annealing furnace, sealing the furnace chamber and pumping the pressure in the chamber to be less than 10 - 3 And (3) rapidly heating to 300-400 ℃ to finish rapid annealing, wherein the rapid heating time is 60-120 seconds, the annealing temperature is 300-400 ℃, and the annealing time is 3-6 minutes.
Compared with the prior art, the invention has the following beneficial results:
in the invention, a p-type zinc selenide nanowire and an n-type cadmium sulfide film with excellent photoelectric properties and a wide-bandgap structure are selected, and a nano heterojunction with a large built-in potential difference is constructed by the p-type zinc selenide nanowire and the n-type cadmium sulfide film; according to the invention, a passivation layer is arranged between the p-type semiconductor nanowire and the n-type semiconductor film, and the nano heterojunction is subjected to rapid annealing treatment, so that the defect state quantity of the nano heterojunction interface can be effectively reduced, and the leakage current of the nano heterojunction area is further reduced to improve the open-circuit voltage of the device; the open-circuit voltage of the nano heterojunction solar cell can reach more than 1V and can reach 1.5V at most.
Description of the drawings:
fig. 1 is a schematic view of the transverse cross-sectional structure of the present invention.
Fig. 2 is a schematic view of the longitudinal sectional structure of the present invention.
Fig. 3 is a flow chart of the fabrication process of the present invention.
The specific embodiment is as follows:
referring to fig. 1 and 2, the semiconductor nanowire comprises a substrate layer (1), a p-type semiconductor nanowire (2), a gold electrode (3), a passivation layer (4), an n-type semiconductor film (5) and a titanium electrode (6), wherein the p-type semiconductor nanowire (2) is arranged on the substrate layer (1), the gold electrode (3) is arranged on one end of the p-type semiconductor nanowire (2), the passivation layer (4) is arranged on the other end of the p-type semiconductor nanowire (2), the n-type semiconductor film (5) is arranged on the passivation layer (4), and the titanium electrode (6) is arranged on the n-type semiconductor film (5). The substrate layer (1) is quartz glass, a silicon wafer with an oxide layer, a sapphire substrate or a PET flexible substrate; the p-type semiconductor nanowire (2) is a p-type zinc selenide (ZnSe) nanowire, the diameter of the p-type semiconductor nanowire is 150-250 nanometers, the length of the p-type semiconductor nanowire is 15-25 micrometers, and the hole concentration of the p-type semiconductor nanowire is 10 18 -10 19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The p-type semiconductor nanowires (2) are horizontally arranged on the substrate layer (1) in an array manner, and the parallel interval of the p-type semiconductor nanowires is 1-5 micrometers; the thickness of the gold electrode (3) is 50-100 nanometers; the passivation layer (4) is silicon nitride (Si) 3 N 4 ) Or alumina (Al) 2 O 3 ) A layer having a thickness of 4-8 nm; the n-type semiconductor film (5) is a n-type cadmium sulfide (CdS) film, and the thickness of the n-type semiconductor film is 40-100 nanometers; the thickness of the titanium electrode (6) is 20-40 nanometers.
Three examples of fabricating a large open circuit voltage nano heterojunction solar cell are given below:
in example 1, a large open-circuit voltage nano heterojunction solar cell was fabricated in which the substrate layer was quartz glass, the gold electrode had a thickness of 50 nm, the passivation layer was silicon nitride and had a thickness of 4 nm, the n-type cadmium sulfide thin film had a thickness of 45 nm, and the titanium electrode had a thickness of 20 nm.
Referring to fig. 3, the manufacturing steps of the present embodiment are as follows:
1) The diameter is 150-250 nm, the length is 15-25 μm, and the hole concentration is 10 18 -10 19 cm -3 The p-type zinc selenide nanowires are transferred to the substrate layer, the p-type zinc selenide nanowires are horizontally arranged on the substrate layer in an array manner, and the parallel intervals of the nanowires are 1-5 microns;
2) Coating photoresist on the surface of a substrate layer, then placing the substrate layer in a photoetching machine, exposing and developing one end of a p-type semiconductor nanowire, placing the substrate layer in a magnetron sputtering instrument, depositing a gold electrode with the thickness of 50 nanometers on the exposed end of the p-type zinc selenide nanowire, and finally placing the substrate layer in an acetone solvent to dissolve the photoresist, thereby obtaining the p-type zinc selenide nanowire with the gold electrode deposited on one end;
3) Coating photoresist on the surface of the substrate layer again, then placing the substrate layer in a photoetching machine, exposing and developing to expose the other end of the p-type zinc selenide nanowire, placing the substrate layer in an atomic layer deposition device, and depositing a silicon nitride passivation layer with the thickness of 4 nanometers on the exposed end of the p-type zinc selenide nanowire;
4) Depositing an n-type cadmium sulfide film over the passivation layer using atomic layer deposition:
4a0 placing the substrate layer in step 3) in an atomic layer deposition reaction chamber, sealing the reaction chamber and pumping the pressure in the chamber to less than 10 -4 Pa, and heating to maintain the temperature in the cavity at 130 ℃;
4b) With thioacetamide (H) 3 CCSNH 2 ) Powder and liquid dimethyl cadmium Cd (CH) 3 ) 2 As a precursor, nitrogen is used as carrier gas and purified gas, and thioacetamide is heated to 110 ℃ by using a heating sleeve;
4c) Introducing thioacetamide precursor to form a first monolayer of S on the surface of the silicon nitride passivation layer; then pumping out residual precursor and nitrogen by a mechanical pump after nitrogen is introduced and flushed;
4d) Introducing dimethyl cadmium to form a second monolayer of Cd on the first monolayer, wherein the first monolayer and the second monolayer form an S-Cd bond; after nitrogen is introduced and flushed, residual precursor and nitrogen are pumped away by a mechanical pump;
4e) Sequentially repeating the steps 4 c) and 4 d), wherein the repetition time is 680 times, and finishing the deposition of the n-type cadmium sulfide film with the thickness of 45 nanometers;
5) Placing the substrate layer in the step 4) in a magnetron sputtering instrument, and depositing a titanium electrode with the thickness of 20 nanometers on the n-type cadmium sulfide film;
6) Placing the substrate layer in the step 5) in an acetone solvent to dissolve the photoresist;
7) Placing the substrate layer in the step 6) in a rapid annealing furnace, sealing the furnace chamber and pumping the pressure in the chamber to be less than 10 - 3 And (3) quickly heating to 350 ℃ to finish the quick annealing, wherein the quick heating time is 90 seconds, the annealing temperature is 350 ℃, and the annealing time is 5 minutes.
After the preparation of the large open-circuit voltage nano heterojunction solar cell is completed, the open-circuit voltage of the large open-circuit voltage nano heterojunction solar cell is tested under a standard analog light source to obtain the large open-circuit voltage nano heterojunction solar cell with the open-circuit voltage of 1.3V and the conversion efficiency of 5.27%.
In example 2, a silicon wafer with an oxide layer was fabricated as the substrate layer, the gold electrode had a thickness of 70 nm, the passivation layer had an alumina thickness of 6 nm, the n-type cadmium sulfide thin film had a thickness of 60 nm, and the titanium electrode had a thickness of 30 nm.
Referring to fig. 3, the manufacturing steps of the present embodiment are as follows:
1) The diameter is 150-250 nm, the length is 15-25 μm, and the hole concentration is 10 18 -10 19 Transferring p-type zinc selenide nanowires of cm-3 to a substrate layer, wherein the p-type zinc selenide nanowires are horizontally arranged on the substrate layer in an array manner, and the parallel intervals of the nanowires are 1-5 micrometers;
2) Coating photoresist on the surface of a substrate layer, then placing the substrate layer in a photoetching machine, exposing and developing one end of a p-type semiconductor nanowire, placing the substrate layer in a magnetron sputtering instrument, depositing a gold electrode with the thickness of 70 nanometers on the exposed end of the p-type zinc selenide nanowire, and finally placing the substrate layer in an acetone solvent to dissolve the photoresist, thereby obtaining the p-type zinc selenide nanowire with the gold electrode deposited on one end;
3) Coating photoresist on the surface of the substrate layer again, then placing the substrate layer in a photoetching machine, exposing and developing to expose the other end of the p-type zinc selenide nanowire, placing the substrate layer in an atomic layer deposition device, and depositing an aluminum oxide passivation layer with the thickness of 6 nanometers on the exposed end of the p-type zinc selenide nanowire;
4) Depositing an n-type cadmium sulfide film over the passivation layer using atomic layer deposition:
4a) Placing the substrate layer in the step 3) into an atomic layer deposition reaction cavity, sealing the reaction cavity and pumping the pressure in the cavity to be less than 10 -4 Pa, and heating to maintain the temperature in the cavity at 130 ℃;
4b) With thioacetamide (H) 3 CCSNH 2 ) Powder and liquid dimethyl cadmium Cd (CH) 3 ) 2 As a precursor, nitrogen is used as carrier gas and purified gas, and thioacetamide is heated to 110 ℃ by using a heating sleeve;
4c) Introducing thioacetamide precursor to form a first monolayer of S on the surface of the alumina passivation layer; then pumping out residual precursor and nitrogen by a mechanical pump after nitrogen is introduced and flushed;
4d) Introducing dimethyl cadmium to form a second monolayer of Cd on the first monolayer, wherein the first monolayer and the second monolayer form an S-Cd bond; after nitrogen is introduced and flushed, residual precursor and nitrogen are pumped away by a mechanical pump;
4e) Sequentially repeating the steps 4 c) and 4 d), wherein the repetition time is 900 times, and the deposition of the n-type cadmium sulfide film with the thickness of 60 nanometers is completed;
5) Placing the substrate layer in the step 4) in a magnetron sputtering instrument, and depositing a titanium electrode with the thickness of 30 nanometers on the n-type cadmium sulfide film;
6) Placing the substrate layer in the step 5) in an acetone solvent, dissolving the photoresist;
7) Placing the substrate layer in the step 6) in a rapid annealing furnace, sealing the furnace chamber and pumping the pressure in the chamber to be less than 10 - 3 Pa, quickly heating to 400 ℃, and completing quick annealing, wherein the quick heating time is that120 seconds, the annealing temperature was 400℃and the annealing time was 6 minutes.
After the preparation of the large open-circuit voltage nano heterojunction solar cell is completed, the open-circuit voltage of the large open-circuit voltage nano heterojunction solar cell is tested under a standard analog light source to obtain the large open-circuit voltage nano heterojunction solar cell with the open-circuit voltage of 1.5V and the conversion efficiency of 4.70%.
In example 3, a large open circuit voltage nano heterojunction solar cell was fabricated in which the substrate layer was a PET flexible substrate, the gold electrode had a thickness of 90 nm, the passivation layer was silicon nitride and had a thickness of 8 nm, the n-type cadmium sulfide thin film had a thickness of 80 nm, and the titanium electrode had a thickness of 35 nm.
Referring to fig. 3, the manufacturing steps of the present embodiment are as follows:
1) The diameter is 150-250 nm, the length is 15-25 μm, and the hole concentration is 10 18 -10 19 cm -3 The p-type zinc selenide nanowires are transferred to the substrate layer, the p-type zinc selenide nanowires are horizontally arranged on the substrate layer in an array manner, and the parallel intervals of the nanowires are 1-5 microns;
2) Coating photoresist on the surface of a substrate layer, then placing the substrate layer in a photoetching machine, exposing and developing one end of a p-type semiconductor nanowire, placing the substrate layer in a magnetron sputtering instrument, depositing a gold electrode with the thickness of 90 nanometers on the exposed end of the p-type zinc selenide nanowire, and finally placing the substrate layer in an acetone solvent to dissolve the photoresist, thereby obtaining the p-type zinc selenide nanowire with the gold electrode deposited on one end;
3) Coating photoresist on the surface of the substrate layer again, then placing the substrate layer in a photoetching machine, exposing and developing to expose the other end of the p-type zinc selenide nanowire, placing the substrate layer in an atomic layer deposition device, and depositing a silicon nitride passivation layer with the thickness of 8 nanometers on the exposed end of the p-type zinc selenide nanowire;
4) Depositing an n-type cadmium sulfide film over the passivation layer using atomic layer deposition:
4a) Placing the substrate layer in the step 3) into an atomic layer deposition reaction cavity, sealing the reaction cavity and pumping the pressure in the cavity to be less than 10 -4 Pa, and heating to maintain the temperature in the cavity at 130 ℃;
4b) Thioacetamide is used as raw materialH 3 CCSNH 2 ) Powder and liquid dimethyl cadmium Cd (CH) 3 ) 2 As a precursor, nitrogen is used as carrier gas and purified gas, and thioacetamide is heated to 110 ℃ by using a heating sleeve;
4c) Introducing thioacetamide precursor to form a first monolayer of S on the surface of the silicon nitride passivation layer; then pumping out residual precursor and nitrogen by a mechanical pump after nitrogen is introduced and flushed;
4d) Introducing dimethyl cadmium to form a second monolayer of Cd on the first monolayer, wherein the first monolayer and the second monolayer form an S-Cd bond; after nitrogen is introduced and flushed, residual precursor and nitrogen are pumped away by a mechanical pump;
4e) Sequentially repeating the steps 4 c) and 4 d), wherein the repetition time is 1200 times, and finishing the deposition of the n-type cadmium sulfide film with the thickness of 80 nanometers;
5) Placing the substrate layer in the step 4) in a magnetron sputtering instrument, and depositing a titanium electrode with the thickness of 35 nanometers on the n-type cadmium sulfide film;
6) Placing the substrate layer in the step 5) in an acetone solvent to dissolve the photoresist;
7) Placing the substrate layer in the step 6) in a rapid annealing furnace, sealing the furnace chamber and pumping the pressure in the chamber to be less than 10 - 3 And (3) rapidly heating to 300 ℃ to finish rapid annealing, wherein the rapid heating time is 60 seconds, the annealing temperature is 300 ℃, and the annealing time is 4 minutes.
After the preparation of the large open-circuit voltage nano heterojunction solar cell is completed, the open-circuit voltage of the large open-circuit voltage nano heterojunction solar cell is tested under a standard analog light source to obtain the large open-circuit voltage nano heterojunction solar cell with the open-circuit voltage of 1.05V and the conversion efficiency of 3.40%.

Claims (9)

1. The utility model provides a big open circuit voltage nanometer heterojunction solar cell which characterized in that: the semiconductor nanowire comprises a substrate layer (1), wherein a p-type semiconductor nanowire (2) is arranged on the substrate layer (1), a gold electrode (3) is arranged on one end of the p-type semiconductor nanowire (2), a passivation layer (4) is arranged on the other end of the p-type semiconductor nanowire (2), an n-type semiconductor film (5) is arranged on the passivation layer (4), and a titanium electrode (6) is arranged on the n-type semiconductor film (5);
the preparation method of the large open-circuit voltage nano heterojunction solar cell comprises the following steps:
1) Transferring the p-type semiconductor nanowires onto a substrate layer to enable the p-type semiconductor nanowires to be distributed in a horizontal array;
2) Coating photoresist on the surface of a substrate layer, then placing the substrate layer in a photoetching machine, exposing and developing one end of a p-type semiconductor nanowire, placing the substrate layer in a magnetron sputtering instrument, depositing a gold electrode on the exposed end of the p-type semiconductor nanowire, and finally placing the substrate layer in an acetone solvent to dissolve the photoresist, thereby obtaining the p-type semiconductor nanowire with the gold electrode deposited on one end;
3) Coating photoresist on the surface of the substrate layer again, then placing the substrate layer in a photoetching machine, exposing and developing to expose the other end of the p-type semiconductor nanowire, placing the substrate layer in an atomic layer deposition device, and depositing a passivation layer on the exposed end of the p-type semiconductor nanowire;
4) Depositing an n-type semiconductor film over the passivation layer using atomic layer deposition:
4a) Placing the substrate layer in the step 3) into an atomic layer deposition reaction cavity, sealing the reaction cavity and pumping the pressure in the cavity to be less than 10 -4 Pa, and heating to maintain the temperature in the cavity at 130 ℃;
4b) By thioacetamide H 3 CCSNH 2 Powder and liquid dimethyl cadmium Cd (CH) 3 ) 2 As a precursor, nitrogen is used as carrier gas and purified gas, and thioacetamide is heated to 110 ℃ by using a heating sleeve;
4c) Introducing thioacetamide precursor to form a first monolayer of S on the surface of the passivation layer; then pumping out residual precursor and nitrogen by a mechanical pump after nitrogen is introduced and flushed;
4d) Introducing dimethyl cadmium to form a second monolayer of Cd on the first monolayer, wherein the first monolayer and the second monolayer form an S-Cd bond; pumping out residual precursor and nitrogen by a mechanical pump after nitrogen is introduced and flushed;
4e) Sequentially repeating the steps 4 c) and 4 d) to finish the deposition of the n-type semiconductor film;
5) Placing the substrate layer in the step 4) in a magnetron sputtering instrument, and depositing a titanium electrode on the n-type semiconductor film;
6) Placing the substrate layer in the step 5) in an acetone solvent to dissolve the photoresist;
7) Placing the substrate layer in the step 6) in a rapid annealing furnace, sealing the furnace chamber and pumping the pressure in the chamber to be less than 10 -3 And (5) Pa, quickly heating to 300-400 ℃ to finish the quick annealing.
2. The large open-circuit voltage nano-heterojunction solar cell of claim 1, wherein: the substrate layer (1) is quartz glass, a silicon wafer with an oxide layer, a sapphire substrate or a PET flexible substrate.
3. The large open-circuit voltage nano-heterojunction solar cell of claim 1, wherein: the p-type semiconductor nanowire (2) is a p-type zinc selenide ZnSe nanowire; the diameter of the p-type semiconductor nanowire (2) is 150-250 nanometers, the length is 15-25 micrometers, and the hole concentration is 10 18 -10 19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The p-type semiconductor nanowires (2) are horizontally arranged on the substrate layer (1) in an array mode, and the parallel interval of the p-type semiconductor nanowires is 1-5 microns.
4. The large open-circuit voltage nano-heterojunction solar cell of claim 1, wherein: the thickness of the gold electrode (3) is 50-100 nanometers.
5. The large open-circuit voltage nano-heterojunction solar cell of claim 1, wherein: the passivation layer (4) is silicon nitride Si 3 N 4 Or aluminum oxide Al 2 O 3 A layer; the thickness of the passivation layer (4) is 4-8 nanometers; and one end of the p-type semiconductor nanowire (2) is uniformly wrapped by the passivation layer (4).
6. The large open-circuit voltage nano-heterojunction solar cell of claim 1, wherein: the n-type semiconductor film (5) is a n-type cadmium sulfide (CdS) film; the thickness of the n-type semiconductor film (5) is 40-100 nanometers.
7. The large open-circuit voltage nano-heterojunction solar cell of claim 1, wherein: the thickness of the titanium electrode (6) is 20-40 nanometers.
8. A large open-circuit voltage nano-heterojunction solar cell according to claim 1, wherein the number of times of sequentially repeating steps 4 c) and 4 d) in step 4 e) is 600-1500.
9. The large open-circuit voltage nano heterojunction solar cell of claim 1, wherein the rapid heating time in the step 7) is 60-120 seconds, the annealing temperature is 300-400 ℃, and the annealing time is 3-6 minutes.
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