CN106057931A - Large open-circuit voltage nano heterojunction solar energy cell and manufacturing method - Google Patents

Large open-circuit voltage nano heterojunction solar energy cell and manufacturing method Download PDF

Info

Publication number
CN106057931A
CN106057931A CN201610543913.7A CN201610543913A CN106057931A CN 106057931 A CN106057931 A CN 106057931A CN 201610543913 A CN201610543913 A CN 201610543913A CN 106057931 A CN106057931 A CN 106057931A
Authority
CN
China
Prior art keywords
type semiconductor
substrate layer
circuit voltage
type
semiconductor nanowires
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201610543913.7A
Other languages
Chinese (zh)
Other versions
CN106057931B (en
Inventor
张希威
孟丹
汤振杰
胡丹
于凤军
贾拴稳
牛晓平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anyang Normal University
Original Assignee
Anyang Normal University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anyang Normal University filed Critical Anyang Normal University
Priority to CN201610543913.7A priority Critical patent/CN106057931B/en
Publication of CN106057931A publication Critical patent/CN106057931A/en
Application granted granted Critical
Publication of CN106057931B publication Critical patent/CN106057931B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042PV modules or arrays of single PV cells
    • H01L31/0445PV modules or arrays of single PV cells including thin film solar cells, e.g. single thin film a-Si, CIS or CdTe solar cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1828Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIBVI compounds, e.g. CdS, ZnS, CdTe
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/543Solar cells from Group II-VI materials
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Abstract

The invention discloses a large open-circuit voltage nano heterojunction solar energy cell and a manufacturing method thereof. The solar energy cell comprises a substrate layer, a p-type semiconductor nano wire, a gold electrode, a passivation layer, an n-type semiconductor film and a titanium electrode. According to the method, firstly, the p-type semiconductor nano wire is transferred onto the substrate layer; secondly, the gold electrode is deposited on one end of the p-type semiconductor nano wire through utilizing the lithography technology and a magnetron sputtering method; thirdly, the passivation layer is deposited on the other end of the p-type semiconductor nano wire through utilizing the lithography technology and an atomic layer sedimentation method; fourthly, the n-type semiconductor film is deposited on the passivation layer through utilizing the atomic layer sedimentation method; and fifthly, the titanium electrode is deposited on the n-type semiconductor film through utilizing the magnetron sputtering method. According to the method, the nano heterojunction structure is utilized, through material selection and structure and process optimization, the large open-circuit voltage nano heterojunction solar energy cell having an open-circuit voltage greater than 1V is realized.

Description

A kind of big nano heterogeneous joint solar cell of open-circuit voltage and preparation method
Technical field:
The present invention relates to nano solar field of batteries, more particularly to the one big open-circuit voltage nano heterojunction sun Can battery and preparation method.
Background technology:
World's conventional energy resource short supply crisis is day by day serious, and a large amount of exploitation of fossil energy have become and cause nature The one of the main reasons that environmental pollution and environment for human survival deteriorate, finding emerging energy has become world's hot issue.Respectively Planting in new forms of energy, solar energy power generating has the advantages such as pollution-free, sustainable, total amount big, distribution wide, application form is various, Paid much attention to by countries in the world.
Open-circuit voltage is the important parameter characterizing solaode.Big open-circuit voltage is the basis obtaining high conversion efficiency, Big open-circuit voltage can promote absorbing thus the raising utilization rate to sunlight of high-energy photon.It addition, big open-circuit voltage is big The basis of output voltage, this makes big open-circuit voltage solaode have many special applications, such as solar mobile phone charging device etc.. For solar module, big open-circuit voltage can reduce Tandem devices quantity, thus reduces battery volume, it is easier to Realize the manufacture of lightweight solaode.
But the open-circuit voltage of current various solaode is the most on the low side.Monocrystal silicon in first generation solaode Being only about 0.7V with the open-circuit voltage of polycrystal silicon cell, the highest of the amorphous silicon battery reported at present is 0.85V.The second filial generation Gallium arsenide cells and cadmium telluride cells in thin-film solar cells can make more greatly open-circuit voltage improve extremely due to energy gap 1V and 0.85V, Cu-In selenide and Copper indium gallium selenide battery then only have about 0.7V.Dye sensitization of solar in the third generation Battery only has about 0.73V.As can be seen here, long-term Innovation Input does not make the shortcoming that above-mentioned all kinds of battery open circuit voltage is low obtain To improve.
Summary of the invention:
The present invention is directed to the deficiencies in the prior art, it is proposed that a kind of big nano heterogeneous joint solar cell of open-circuit voltage and system Preparation Method, it is intended to obtain the nano heterogeneous joint solar cell with big open-circuit voltage.
For achieving the above object, the present invention proposes a kind of big nano heterogeneous joint solar cell of open-circuit voltage, its feature Being: include substrate layer (1), being provided with p-type semiconductor nanowires (2) on described substrate layer (1), described p-type quasiconductor is received It is provided with gold electrode (3) on one end of rice noodle (2), on the other end of described p-type semiconductor nanowires (2), is provided with passivation layer (4), on described passivation layer (4), it is provided with n-type semiconductive thin film (5), on described n-type semiconductive thin film (5), is provided with titanium electricity Pole (6).
As preferably, described substrate layer (1) is quartz glass, silicon chip, Sapphire Substrate or PET with oxide layer (Polyethylene terephthalate, polyethylene terephthalate) flexible substrate.
As preferably, described p-type semiconductor nanowires (2) is p-type zinc selenide (ZnSe) nano wire;Described p-type A diameter of 150-250 nanometer of semiconductor nanowires (2), a length of 15-25 micron, hole concentration is 1018-1019cm-3;Described P-type semiconductor nanowires (2) on substrate layer (1) in horizontal array arrange, p-type semiconductor nanowires parallel interval is 1-5 micron.
As preferably, described gold electrode (3) thickness is 50-100 nanometer.
As preferably, described passivation layer (4) is silicon nitride (Si3N4) or aluminium oxide (Al2O3) layer;Described passivation layer (4) is thick Degree is 4-8 nanometer;One end of p-type semiconductor nanowires (2) is uniformly wrapped up by described passivation layer (4).
As preferably, described n-type semiconductive thin film (5) is n-type cadmium sulfide (CdS) thin film;Described n-type semiconductor film The thickness of film (5) is 40-100 nanometer.
As preferably, the thickness of described Ti electrode (6) is 20-40 nanometer.
For achieving the above object, the preparation method of the present invention comprises the steps:
1) p-type semiconductor nanowires is transferred on substrate layer, is allowed to arrange in horizontal array;
2) it is positioned in litho machine after substrate layer surface smear photoresist, makes p-type quasiconductor receive by exposed and developed Rice noodle one end is exposed, then is positioned in magnetic control sputtering device by this substrate layer, on one end that p-type semiconductor nanowires is exposed Deposition gold electrode, is finally positioned over described substrate layer in acetone solvent, makes photoresist dissolve, and obtaining one end deposition has gold electricity The p-type semiconductor nanowires of pole;
3) again it is positioned in litho machine after substrate layer surface smear photoresist, makes p-type partly lead by exposed and developed The other end of body nano wire is exposed, is then positioned in atomic layer deposition apparatus by this substrate layer, at p-type semiconductor nanowires Deposit passivation layer on exposed one end;
4) atomic layer deposition method depositing n-type semiconductive thin film on passivation layer is used:
4a) step 3) in substrate layer be positioned in the reaction chamber of ald, confined reaction chamber by intracavity pressure Power is evacuated to less than 10-4Pa, and heat make cavity inner temperature remain 130 DEG C;
4b) with thioacetamide (H3CCSNH2) powder and liquid dimethyl base cadmium Cd (CH3)2For presoma, with nitrogen for carrying Gas and purification gas, and use heating mantle that thioacetamide is heated to 110 DEG C;
4c) it is passed through thioacetamide presoma, forms first monolayer of S in passivation layer surface;Then pass to nitrogen rinse After walked remaining presoma and nitrogen by mechanical pump extraction;
4d) it is passed through dimethyl cadmium, the first monolayer mentioned above is formed second monolayer of Cd, the first monolayer and second Monolayer forms S-Cd key;It is passed through after nitrogen rinses and is walked remaining presoma and nitrogen by mechanical pump extraction;
4e) it is repeated in step 4c) and 4d), number of repetition is 600-1500 time, completes the heavy of n-type semiconductive thin film Long-pending;
5) by step 4) in substrate layer be positioned in magnetic control sputtering device, on n-type semiconductive thin film titanium deposition electricity Pole;
6) by step 5) in substrate layer be positioned in acetone solvent, make photoresist dissolve;
7) by step 6) in substrate layer be positioned in quick anneal oven, cavity pressure is also evacuated to less than 10 by airtight furnace chamber- 3Pa, is rapidly heated to 300-400 DEG C, completes short annealing, and wherein, fast ramp up time is the 60-120 second, and annealing temperature is 300-400 DEG C, annealing time is 3-6 minute.
Compared with prior art, the present invention has a following beneficial outcomes:
In the present invention, choose and there is excellent photoelectric property and there is p-type ZnSe nano wire and the n-type of broad-band gap structure Cadmium sulphide membrane, both construct the nano heterojunction with big build-up potential;In the present invention, take at p-type quasiconductor Insert passivation layer between nano wire and n-type semiconductive thin film, and nano heterojunction is carried out short annealing process, above-mentioned arrange Execute and can effectively reduce nano heterojunction boundary defect state quantity, and then reduce nano heterojunction leakage current in junction region to improve device Open-circuit voltage;The open-circuit voltage of above-mentioned nano heterogeneous joint solar cell, up to more than 1V, reaches as high as 1.5V.
Accompanying drawing illustrates:
Fig. 1 is horizontal section structural representation of the present invention.
Fig. 2 is longitudinal profile structural representation of the present invention.
Fig. 3 is the fabrication processing figure of the present invention.
Detailed description of the invention:
Seeing figures.1.and.2, the present invention includes substrate layer (1), p-type semiconductor nanowires (2), gold electrode (3), passivation layer (4), n-type semiconductive thin film (5), Ti electrode (6), be wherein provided with p-type semiconductor nanowires (2) on substrate layer (1), described Be provided with gold electrode (3) on one end of p-type semiconductor nanowires (2), the other end of described p-type semiconductor nanowires (2) it It is provided with passivation layer (4), on described passivation layer (4), is provided with n-type semiconductive thin film (5), described n-type semiconductive thin film (5) On be provided with Ti electrode (6).Described substrate layer (1) is quartz glass, silicon chip, Sapphire Substrate or PET with oxide layer Flexible substrate;Described p-type semiconductor nanowires (2) is p-type zinc selenide (ZnSe) nano wire, its a diameter of 150-250 nanometer, A length of 15-25 micron, hole concentration is 1018-1019cm-3;Described p-type semiconductor nanowires (2) is on substrate layer (1) Arranging in horizontal array, p-type semiconductor nanowires parallel interval is 1-5 micron;Described gold electrode (3) thickness is that 50-100 receives Rice;Described passivation layer (4) is silicon nitride (Si3N4) or aluminium oxide (Al2O3) layer, thickness is 4-8 nanometer;Described n-type quasiconductor Thin film (5) is n-type cadmium sulfide (CdS) thin film, and its thickness is 40-100 nanometer;The thickness of described Ti electrode (6) is that 20-40 receives Rice.
Three embodiments of the making given below nano heterogeneous joint solar cell of a kind of big open-circuit voltage:
Embodiment 1, making substrate layer is quartz glass, and gold electrode thickness is 50 nanometers, and passivation layer is silicon nitride and thickness Being 4 nanometers, n-type cadmium sulphide membrane thickness is 45 nanometers, Ti electrode thickness be the big open-circuit voltage nano heterojunction of 20 nanometers too Sun can battery.
With reference to Fig. 3, the making step of the present embodiment is as follows:
1) by a diameter of 150-250 nanometer, a length of 15-25 micron, hole concentration is 1018-1019cm-3P-type selenizing Zinc nano wire is transferred on substrate layer, and p-type ZnSe nano wire is arranged in horizontal array on substrate layer, parallel of nano wire It is divided into 1-5 micron;
2) it is positioned in litho machine after substrate layer surface smear photoresist, makes p-type quasiconductor receive by exposed and developed Rice noodle one end is exposed, then is positioned in magnetic control sputtering device by this substrate layer, on one end that p-type ZnSe nano wire is exposed Deposit thickness is the gold electrode of 50 nanometers, is finally positioned in acetone solvent by described substrate layer, makes photoresist dissolve, obtains One end deposition has the p-type ZnSe nano wire of gold electrode;
3) again it is positioned in litho machine after substrate layer surface smear photoresist, makes p-type selenizing by exposed and developed The other end of zinc nano wire is exposed, is then positioned in atomic layer deposition apparatus by this substrate layer, at p-type ZnSe nano wire On exposed one end, deposit thickness is the silicon nitride passivation of 4 nanometers;
4) atomic layer deposition method depositing n-type cadmium sulphide membrane on passivation layer is used:
4a0 is step 3) in substrate layer be positioned in the reaction chamber of ald, confined reaction chamber by intracavity pressure Power is evacuated to less than 10-4Pa, and heat make cavity inner temperature remain 130 DEG C;
4b) with thioacetamide (H3CCSNH2) powder and liquid dimethyl base cadmium Cd (CH3)2For presoma, with nitrogen for carrying Gas and purification gas, and use heating mantle that thioacetamide is heated to 110 DEG C;
4c) it is passed through thioacetamide presoma, forms first monolayer of S on silicon nitride passivation surface;Then pass to nitrogen Remaining presoma and nitrogen is walked by mechanical pump extraction after gas flushing;
4d) it is passed through dimethyl cadmium, the first monolayer mentioned above is formed second monolayer of Cd, the first monolayer and second Monolayer forms S-Cd key;It is passed through after nitrogen rinses and is taken away remaining presoma and nitrogen by mechanical pump;
4e) it is repeated in step 4c) and 4d), number of repetition is 680 times, completes the n-type cadmium sulfide that thickness is 45 nanometers The deposition of thin film;
5) by step 4) in substrate layer be positioned in magnetic control sputtering device, on n-type cadmium sulphide membrane, deposit thickness is The Ti electrode of 20 nanometers;
6) by step 5) in substrate layer be positioned in acetone solvent, make photoresist dissolve;
7) by step 6) in substrate layer be positioned in quick anneal oven, cavity pressure is also evacuated to less than 10 by airtight furnace chamber- 3Pa, is rapidly heated to 350 DEG C, completes short annealing, and wherein, fast ramp up time is 90 seconds, and annealing temperature is 350 DEG C, annealing Time is 5 minutes.
After completing the preparation of the above-mentioned nano heterogeneous joint solar cell of big open-circuit voltage, it is surveyed under standard analog light source Examination can obtain its open-circuit voltage be 1.3V, conversion efficiency be 5.27%.
Embodiment 2, making substrate layer is the silicon chip with oxide layer, and gold electrode thickness is 70 nanometers, and passivation layer is oxidation Aluminum and thickness are 6 nanometers, and n-type cadmium sulphide membrane thickness is 60 nanometers, and Ti electrode thickness is the big open-circuit voltage nanometer of 30 nanometers Heterojunction solar battery.
With reference to Fig. 3, the making step of the present embodiment is as follows:
1) by a diameter of 150-250 nanometer, a length of 15-25 micron, hole concentration is 1018-1019The p-type selenium of cm-3 Changing zinc nano wire to be transferred on substrate layer, p-type ZnSe nano wire is arranged in horizontal array on substrate layer, and nano wire is parallel It is spaced apart 1-5 micron;
2) it is positioned in litho machine after substrate layer surface smear photoresist, makes p-type quasiconductor receive by exposed and developed Rice noodle one end is exposed, then is positioned in magnetic control sputtering device by this substrate layer, on one end that p-type ZnSe nano wire is exposed Deposit thickness is the gold electrode of 70 nanometers, is finally positioned in acetone solvent by described substrate layer, makes photoresist dissolve, obtains One end deposition has the p-type ZnSe nano wire of gold electrode;
3) again it is positioned in litho machine after substrate layer surface smear photoresist, makes p-type selenizing by exposed and developed The other end of zinc nano wire is exposed, is then positioned in atomic layer deposition apparatus by this substrate layer, at p-type ZnSe nano wire On exposed one end, deposit thickness is the alumina passivation layer of 6 nanometers;
4) atomic layer deposition method depositing n-type cadmium sulphide membrane on passivation layer is used:
4a) step 3) in substrate layer be positioned in the reaction chamber of ald, confined reaction chamber by intracavity pressure Power is evacuated to less than 10-4Pa, and heat make cavity inner temperature remain 130 DEG C;
4b) with thioacetamide (H3CCSNH2) powder and liquid dimethyl base cadmium Cd (CH3)2For presoma, with nitrogen for carrying Gas and purification gas, and use heating mantle that thioacetamide is heated to 110 DEG C;
4c) it is passed through thioacetamide presoma, forms first monolayer of S on alumina passivation layer surface;Then pass to nitrogen Remaining presoma and nitrogen is walked by mechanical pump extraction after gas flushing;
4d) it is passed through dimethyl cadmium, the first monolayer mentioned above is formed second monolayer of Cd, the first monolayer and second Monolayer forms S-Cd key;It is passed through after nitrogen rinses and is taken away remaining presoma and nitrogen by mechanical pump;
4e) it is repeated in step 4c) and 4d), number of repetition is 900 times, completes the n-type cadmium sulfide that thickness is 60 nanometers The deposition of thin film;
5) by step 4) in substrate layer be positioned in magnetic control sputtering device, on n-type cadmium sulphide membrane, deposit thickness is The Ti electrode of 30 nanometers;
6) by step 5) in substrate layer be positioned in acetone solvent, make photoresist dissolve;
7) by step 6) in substrate layer be positioned in quick anneal oven, cavity pressure is also evacuated to less than 10 by airtight furnace chamber- 3Pa, is rapidly heated to 400 DEG C, completes short annealing, and wherein, fast ramp up time is 120 seconds, and annealing temperature is 400 DEG C, moves back The fire time is 6 minutes.
After completing the preparation of the above-mentioned nano heterogeneous joint solar cell of big open-circuit voltage, it is surveyed under standard analog light source Examination can obtain its open-circuit voltage be 1.5V, conversion efficiency be 4.70%.
Embodiment 3, making substrate layer is PET flexible substrate, and gold electrode thickness is 90 nanometers, and passivation layer is silicon nitride and thickness Degree is 8 nanometers, and n-type cadmium sulphide membrane thickness is 80 nanometers, and Ti electrode thickness is the big open-circuit voltage nano heterojunction of 35 nanometers Solaode.
With reference to Fig. 3, the making step of the present embodiment is as follows:
1) by a diameter of 150-250 nanometer, a length of 15-25 micron, hole concentration is 1018-1019cm-3P-type selenizing Zinc nano wire is transferred on substrate layer, and p-type ZnSe nano wire is arranged in horizontal array on substrate layer, parallel of nano wire It is divided into 1-5 micron;
2) it is positioned in litho machine after substrate layer surface smear photoresist, makes p-type quasiconductor receive by exposed and developed Rice noodle one end is exposed, then is positioned in magnetic control sputtering device by this substrate layer, on one end that p-type ZnSe nano wire is exposed Deposit thickness is the gold electrode of 90 nanometers, is finally positioned in acetone solvent by described substrate layer, makes photoresist dissolve, obtains One end deposition has the p-type ZnSe nano wire of gold electrode;
3) again it is positioned in litho machine after substrate layer surface smear photoresist, makes p-type selenizing by exposed and developed The other end of zinc nano wire is exposed, is then positioned in atomic layer deposition apparatus by this substrate layer, at p-type ZnSe nano wire On exposed one end, deposit thickness is the silicon nitride passivation of 8 nanometers;
4) atomic layer deposition method depositing n-type cadmium sulphide membrane on passivation layer is used:
4a) step 3) in substrate layer be positioned in the reaction chamber of ald, confined reaction chamber by intracavity pressure Power is evacuated to less than 10-4Pa, and heat make cavity inner temperature remain 130 DEG C;
4b) with thioacetamide (H3CCSNH2) powder and liquid dimethyl base cadmium Cd (CH3)2For presoma, with nitrogen for carrying Gas and purification gas, and use heating mantle that thioacetamide is heated to 110 DEG C;
4c) it is passed through thioacetamide presoma, forms first monolayer of S on silicon nitride passivation surface;Then pass to nitrogen Remaining presoma and nitrogen is walked by mechanical pump extraction after gas flushing;
4d) it is passed through dimethyl cadmium, the first monolayer mentioned above is formed second monolayer of Cd, the first monolayer and second Monolayer forms S-Cd key;It is passed through after nitrogen rinses and is taken away remaining presoma and nitrogen by mechanical pump;
4e) it is repeated in step 4c) and 4d), number of repetition is 1200 times, completes the n-type cadmium sulfide that thickness is 80 nanometers The deposition of thin film;
5) by step 4) in substrate layer be positioned in magnetic control sputtering device, on n-type cadmium sulphide membrane, deposit thickness is The Ti electrode of 35 nanometers;
6) by step 5) in substrate layer be positioned in acetone solvent, make photoresist dissolve;
7) by step 6) in substrate layer be positioned in quick anneal oven, cavity pressure is also evacuated to less than 10 by airtight furnace chamber- 3Pa, is rapidly heated to 300 DEG C, completes short annealing, and wherein, fast ramp up time is 60 seconds, and annealing temperature is 300 DEG C, annealing Time is 4 minutes.
After completing the preparation of the above-mentioned nano heterogeneous joint solar cell of big open-circuit voltage, it is surveyed under standard analog light source Examination can obtain its open-circuit voltage be 1.05V, conversion efficiency be 3.40%.

Claims (10)

1. the nano heterogeneous joint solar cell of big open-circuit voltage, it is characterised in that: include substrate layer (1), described substrate layer (1) it is provided with p-type semiconductor nanowires (2) on, on one end of described p-type semiconductor nanowires (2), is provided with gold electrode (3), being provided with passivation layer (4) on the other end of described p-type semiconductor nanowires (2), described passivation layer is provided with n-on (4) Type semiconductive thin film (5), is provided with Ti electrode (6) on described n-type semiconductive thin film (5).
2. according to a kind of big nano heterogeneous joint solar cell of open-circuit voltage described in claims 1, it is characterised in that: described Substrate layer (1) is quartz glass, silicon chip, Sapphire Substrate or PET (Polyethylene with oxide layer Terephthalate, polyethylene terephthalate) flexible substrate.
3. according to a kind of big nano heterogeneous joint solar cell of open-circuit voltage described in claims 1, it is characterised in that: described P-type semiconductor nanowires (2) be p-type zinc selenide (ZnSe) nano wire;The diameter of described p-type semiconductor nanowires (2) For 150-250 nanometer, a length of 15-25 micron, hole concentration is 1018-1019cm-3;Described p-type semiconductor nanowires (2) Arranging in horizontal array on substrate layer (1), p-type semiconductor nanowires parallel interval is 1-5 micron.
4. according to a kind of big nano heterogeneous joint solar cell of open-circuit voltage described in claims 1, it is characterised in that: described Gold electrode (3) thickness is 50-100 nanometer.
5. according to a kind of big nano heterogeneous joint solar cell of open-circuit voltage described in claims 1, it is characterised in that: described Passivation layer (4) is silicon nitride (Si3N4) or aluminium oxide (Al2O3) layer;Described passivation layer (4) thickness is 4-8 nanometer;Described passivation One end of p-type semiconductor nanowires (2) is uniformly wrapped up by layer (4).
6. according to a kind of big nano heterogeneous joint solar cell of open-circuit voltage described in claims 1, it is characterised in that: described N-type semiconductive thin film (5) is n-type cadmium sulfide (CdS) thin film;The thickness of described n-type semiconductive thin film (5) is that 40-100 receives Rice.
7. according to a kind of big nano heterogeneous joint solar cell of open-circuit voltage described in claims 1, it is characterised in that: described The thickness of Ti electrode (6) is 20-40 nanometer.
8. a preparation method for the nano heterogeneous joint solar cell of big open-circuit voltage, comprises the steps:
1) p-type semiconductor nanowires is transferred on substrate layer, is allowed to arrange in horizontal array;
2) it is positioned in litho machine after substrate layer surface smear photoresist, makes p-type semiconductor nanowires by exposed and developed One end is exposed, then is positioned in magnetic control sputtering device by this substrate layer, deposits on one end that p-type semiconductor nanowires is exposed Gold electrode, is finally positioned over described substrate layer in acetone solvent, makes photoresist dissolve, and obtaining one end deposition has gold electrode P-type semiconductor nanowires;
3) again it is positioned in litho machine after substrate layer surface smear photoresist, makes p-type quasiconductor receive by exposed and developed The other end of rice noodle is exposed, is then positioned in atomic layer deposition apparatus by this substrate layer, exposed at p-type semiconductor nanowires One end on deposit passivation layer;
4) atomic layer deposition method depositing n-type semiconductive thin film on passivation layer is used:
4a) step 3) in substrate layer be positioned in the reaction chamber of ald, cavity pressure is also taken out by confined reaction chamber To less than 10-4Pa, and heat make cavity inner temperature remain 130 DEG C;
4b) with thioacetamide (H3CCSNH2) powder and liquid dimethyl base cadmium Cd (CH3)2For presoma, nitrogen buffer gas and Purify gas, and use heating mantle that thioacetamide is heated to 110 DEG C;
4c) it is passed through thioacetamide presoma, forms first monolayer of S in passivation layer surface;Then pass to nitrogen rinse after by Remaining presoma and nitrogen are walked in mechanical pump extraction;
4d) it is passed through dimethyl cadmium, the first monolayer mentioned above is formed second monolayer of Cd, the first monolayer and the second monolayer Form S-Cd key;It is passed through after nitrogen rinses and is walked remaining presoma and nitrogen by mechanical pump extraction;
4e) it is repeated in step 4c) and 4d), complete the deposition of n-type semiconductive thin film;
5) by step 4) in substrate layer be positioned in magnetic control sputtering device, titanium deposition electrode on n-type semiconductive thin film;
6) by step 5) in substrate layer be positioned in acetone solvent, make photoresist dissolve;
7) by step 6) in substrate layer be positioned in quick anneal oven, cavity pressure is also evacuated to less than 10 by airtight furnace chamber-3Pa, soon Speed is warming up to 300-400 DEG C, completes short annealing.
The preparation method of a kind of nano heterogeneous joint solar cell of big open-circuit voltage the most as claimed in claim 8, its feature exists In step 4e) described in be repeated in step 4c) and number of times 4d) be 600-1500 time.
The preparation method of a kind of nano heterogeneous joint solar cell of big open-circuit voltage the most as claimed in claim 8, its feature exists In step 7) described in fast ramp up time be the 60-120 second, annealing temperature is 300-400 DEG C, and annealing time is 3-6 minute.
CN201610543913.7A 2016-07-05 2016-07-05 Large open-circuit voltage nano heterojunction solar cell and preparation method thereof Active CN106057931B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610543913.7A CN106057931B (en) 2016-07-05 2016-07-05 Large open-circuit voltage nano heterojunction solar cell and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610543913.7A CN106057931B (en) 2016-07-05 2016-07-05 Large open-circuit voltage nano heterojunction solar cell and preparation method thereof

Publications (2)

Publication Number Publication Date
CN106057931A true CN106057931A (en) 2016-10-26
CN106057931B CN106057931B (en) 2023-07-07

Family

ID=57186647

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610543913.7A Active CN106057931B (en) 2016-07-05 2016-07-05 Large open-circuit voltage nano heterojunction solar cell and preparation method thereof

Country Status (1)

Country Link
CN (1) CN106057931B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108447925A (en) * 2018-04-27 2018-08-24 安阳师范学院 Flexible heterojunction solar battery array based on horizontal arrangement nano wire film and preparation method thereof
CN109411357A (en) * 2018-10-26 2019-03-01 郑州大学 A kind of P-N hetero-junctions and preparation method thereof of nickel oxide nanowires and zinc oxide composition
CN109545869A (en) * 2018-10-24 2019-03-29 四川大学 A kind of flexible cadmium telluride solar cell of two-sided three terminal

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060145190A1 (en) * 2004-12-31 2006-07-06 Salzman David B Surface passivation for III-V compound semiconductors
KR100847741B1 (en) * 2007-02-21 2008-07-23 고려대학교 산학협력단 Point-contacted heterojunction silicon solar cell having passivation layer between the interface of p-n junction and method for fabricating the same
CN102034902A (en) * 2010-11-03 2011-04-27 上海大学 Method for preparing silicon-based SIS heterojunction photoelectric device
US20110139249A1 (en) * 2009-12-10 2011-06-16 Uriel Solar Inc. High Power Efficiency Polycrystalline CdTe Thin Film Semiconductor Photovoltaic Cell Structures for Use in Solar Electricity Generation
CN102640301A (en) * 2009-12-07 2012-08-15 应用材料公司 Method of cleaning and forming a negatively charged passivation layer over a doped region
EP2534697A2 (en) * 2010-02-09 2012-12-19 Helmholtz-Zentrum Berlin für Materialien und Energie GmbH Back contact solar cell having an unstructured absorber layer
CN102938429A (en) * 2012-12-21 2013-02-20 国电光伏(江苏)有限公司 Antireflection heterojunction solar cell and preparation method thereof
CN103258970A (en) * 2012-09-19 2013-08-21 苏州大学 Method for preparing core-shell organic/cadmium sulfide nanowire heterojunction arrays
US20130240348A1 (en) * 2009-11-30 2013-09-19 The Royal Institution For The Advancement Of Learning / Mcgill University High Efficiency Broadband Semiconductor Nanowire Devices
US20140026937A1 (en) * 2011-04-11 2014-01-30 Commissariat A L'energie Atomique Et Aux Energies Alternatives Semiconductor Heterostructure and Photovoltaic Cell Including Such A Heterostructure
CN103956391A (en) * 2014-04-11 2014-07-30 中国科学院宁波材料技术与工程研究所 AZO/Si heterojunction solar battery and manufacturing method thereof
WO2015088320A1 (en) * 2013-12-09 2015-06-18 Mimos Berhad Process of texturing silicon surface for optimal sunlight capture in solar cells
CN104952703A (en) * 2015-05-20 2015-09-30 安阳师范学院 Production method of IIB-VIB semiconductor/CdS nano P-N junction
KR101626248B1 (en) * 2015-01-09 2016-05-31 고려대학교 산학협력단 Silicon solar cell and method of manufacturing the same

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060145190A1 (en) * 2004-12-31 2006-07-06 Salzman David B Surface passivation for III-V compound semiconductors
KR100847741B1 (en) * 2007-02-21 2008-07-23 고려대학교 산학협력단 Point-contacted heterojunction silicon solar cell having passivation layer between the interface of p-n junction and method for fabricating the same
US20130240348A1 (en) * 2009-11-30 2013-09-19 The Royal Institution For The Advancement Of Learning / Mcgill University High Efficiency Broadband Semiconductor Nanowire Devices
CN102640301A (en) * 2009-12-07 2012-08-15 应用材料公司 Method of cleaning and forming a negatively charged passivation layer over a doped region
US20110139249A1 (en) * 2009-12-10 2011-06-16 Uriel Solar Inc. High Power Efficiency Polycrystalline CdTe Thin Film Semiconductor Photovoltaic Cell Structures for Use in Solar Electricity Generation
EP2534697A2 (en) * 2010-02-09 2012-12-19 Helmholtz-Zentrum Berlin für Materialien und Energie GmbH Back contact solar cell having an unstructured absorber layer
CN102034902A (en) * 2010-11-03 2011-04-27 上海大学 Method for preparing silicon-based SIS heterojunction photoelectric device
US20140026937A1 (en) * 2011-04-11 2014-01-30 Commissariat A L'energie Atomique Et Aux Energies Alternatives Semiconductor Heterostructure and Photovoltaic Cell Including Such A Heterostructure
CN103258970A (en) * 2012-09-19 2013-08-21 苏州大学 Method for preparing core-shell organic/cadmium sulfide nanowire heterojunction arrays
CN102938429A (en) * 2012-12-21 2013-02-20 国电光伏(江苏)有限公司 Antireflection heterojunction solar cell and preparation method thereof
WO2015088320A1 (en) * 2013-12-09 2015-06-18 Mimos Berhad Process of texturing silicon surface for optimal sunlight capture in solar cells
CN103956391A (en) * 2014-04-11 2014-07-30 中国科学院宁波材料技术与工程研究所 AZO/Si heterojunction solar battery and manufacturing method thereof
KR101626248B1 (en) * 2015-01-09 2016-05-31 고려대학교 산학협력단 Silicon solar cell and method of manufacturing the same
CN104952703A (en) * 2015-05-20 2015-09-30 安阳师范学院 Production method of IIB-VIB semiconductor/CdS nano P-N junction

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108447925A (en) * 2018-04-27 2018-08-24 安阳师范学院 Flexible heterojunction solar battery array based on horizontal arrangement nano wire film and preparation method thereof
CN108447925B (en) * 2018-04-27 2024-01-30 安阳师范学院 Flexible heterojunction solar cell array based on horizontally arranged nanowire films and preparation method thereof
CN109545869A (en) * 2018-10-24 2019-03-29 四川大学 A kind of flexible cadmium telluride solar cell of two-sided three terminal
CN109411357A (en) * 2018-10-26 2019-03-01 郑州大学 A kind of P-N hetero-junctions and preparation method thereof of nickel oxide nanowires and zinc oxide composition
CN109411357B (en) * 2018-10-26 2020-08-07 郑州大学 P-N heterojunction composed of nickel oxide nanowire and zinc oxide and preparation method thereof

Also Published As

Publication number Publication date
CN106057931B (en) 2023-07-07

Similar Documents

Publication Publication Date Title
Singh et al. Solar PV cell materials and technologies: Analyzing the recent developments
He et al. Enhanced electro‐optical properties of nanocone/nanopillar dual‐structured arrays for ultrathin silicon/organic hybrid solar cell applications
O'Donnell et al. Silicon nanowire solar cells grown by PECVD
TW201010094A (en) Nano or micro-structured PN junction diode array thin-film solar cell and manufacturing method thereof
CN103681889B (en) Electret-structure-introduced efficient solar cell and preparing method thereof
CN110518095B (en) Light processing method of silicon heterojunction solar cell
TW201140859A (en) Coaxial nanowire solar cell structure
CN106057931A (en) Large open-circuit voltage nano heterojunction solar energy cell and manufacturing method
El-Atab et al. Flexible and stretchable inorganic solar cells: Progress, challenges, and opportunities
US9691927B2 (en) Solar cell apparatus and method of fabricating the same
Bertolli Solar cell materials
KR101461602B1 (en) Quantum well structured solar cells and method for manufacturing same
CN103000709B (en) Back electrode, back electrode absorbing layer composite structure and solar cell
CN110905723A (en) Novel wind driven generator with fractal interface structure
CN110165020A (en) One kind being based on CdS/SnO2Mix the efficient Sb of N-type layer2Se3Hull cell and preparation method thereof
Jaiswal et al. Nanomaterials based solar cells
Jarkov et al. Conductive polymer PEDOT: PSS back contact for CdTe solar cell
CN101459206A (en) Manufacturing process for high-efficiency multi-junction solar cell
TWI298548B (en) A design of transparent conducting anti-reflection laminate and solar cell
JP2022535268A (en) High Efficiency Graphene/Wide Bandgap Semiconductor Heterojunction Solar Cell
Kumari et al. Effect of ZnO BSF layer on the performance of PEDOT: PSS/Si heterojunction solar cell
CN102683491A (en) Method for preparing indium arsenide/gallium arsenide quantum dot solar cell
CN205881919U (en) Big open circuit voltage nanometer heterojunction solar cell
CN110137295B (en) Molybdenum disulfide/gallium indium nitrogen or aluminum gallium arsenic multi-junction heterogeneous solar cell and preparation method thereof
Simashkevich et al. Low-Cost ITO/n-Si Solar Cells with Increased Sensitivity in UV Spectrum Range

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant