CN106057882A - 半导体组件 - Google Patents
半导体组件 Download PDFInfo
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- CN106057882A CN106057882A CN201610107906.2A CN201610107906A CN106057882A CN 106057882 A CN106057882 A CN 106057882A CN 201610107906 A CN201610107906 A CN 201610107906A CN 106057882 A CN106057882 A CN 106057882A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 115
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 46
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 46
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 26
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 21
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 21
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052733 gallium Inorganic materials 0.000 claims abstract description 20
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims abstract description 10
- 230000003139 buffering effect Effects 0.000 claims description 71
- 239000004411 aluminium Substances 0.000 claims description 28
- 230000000977 initiatory effect Effects 0.000 claims description 26
- 239000000956 alloy Substances 0.000 claims description 18
- 229910045601 alloy Inorganic materials 0.000 claims description 18
- 230000008859 change Effects 0.000 claims description 12
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 claims description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- 229910017083 AlN Inorganic materials 0.000 claims description 7
- 229910052582 BN Inorganic materials 0.000 claims description 7
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 238000002156 mixing Methods 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 16
- 230000015556 catabolic process Effects 0.000 abstract description 11
- 238000001816 cooling Methods 0.000 abstract description 4
- 230000008569 process Effects 0.000 abstract description 4
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 abstract 2
- FGUJWQZQKHUJMW-UHFFFAOYSA-N [AlH3].[B] Chemical compound [AlH3].[B] FGUJWQZQKHUJMW-UHFFFAOYSA-N 0.000 abstract 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 abstract 1
- 238000005336 cracking Methods 0.000 abstract 1
- 239000002019 doping agent Substances 0.000 abstract 1
- 229910052742 iron Inorganic materials 0.000 abstract 1
- 238000000407 epitaxy Methods 0.000 description 19
- 238000005516 engineering process Methods 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 229910002704 AlGaN Inorganic materials 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 239000000203 mixture Substances 0.000 description 6
- 238000012545 processing Methods 0.000 description 6
- 239000007789 gas Substances 0.000 description 4
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 238000003780 insertion Methods 0.000 description 3
- 230000037431 insertion Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052594 sapphire Inorganic materials 0.000 description 3
- 239000010980 sapphire Substances 0.000 description 3
- GETQZCLCWQTVFV-UHFFFAOYSA-N trimethylamine Chemical compound CN(C)C GETQZCLCWQTVFV-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000001186 cumulative effect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 230000001737 promoting effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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Abstract
本发明提供一种半导体组件,包含一基板、一初始层及一缓冲堆栈结构。初始层设置于基板之上且包含氮化铝。缓冲堆栈结构设置于初始层之上,缓冲堆栈结构包含多个基层及至少一掺杂层设置于相邻二层基层之间,基层包含氮化铝镓,掺杂层包含氮化铝镓或氮化硼铝镓。在缓冲堆栈结构之中,基层的铝浓度渐减且镓浓度渐增,基层实质上不含碳,掺杂层的掺质为碳或铁。本发明不仅提升半导体组件的崩溃电压,且一并兼顾半导体组件的整体翘曲,避免在完成磊晶制程后的冷却过程,半导体组件因过度翘曲而破裂。
Description
技术领域
本发明涉及一种半导体组件;尤其涉及一种具有基层(氮化铝镓)及掺杂层(氮化铝镓或氮化硼铝镓)的缓冲堆栈结构的半导体组件。
背景技术
氮化物半导体的特性在于它们的高饱和电子速度及宽能带间隙,因此氮化物半导体除了应用在发光半导体组件上,已经广泛地应用于高崩溃电压、高功率输出的化合物半导体组件。例如,在氮化镓(GaN)高电子迁移率晶体管(HEMT)中,GaN层及氮化铝镓(AlGaN)层依序磊晶成长在基板上,其中GaN层作为电子传输层(electron travel layer),AlGaN层作为一电子供应层(electron supplylayer)。AlGaN与GaN之间的晶格常数不同可以在AlGaN层中会产生应变,因而藉由压电极性而产生高浓度的二维电子气体(2DEG)。如此,GaN高电子迁移率晶体管适合应用于高输出功率装置。
现有技术在AlGaN构成的整个缓冲层中连续地掺杂掺质;然而,在整个AlGaN层中连续地掺杂掺质导致结晶度及粗糙度变差,并增加半导体组件的整体翘曲。
发明内容
本发明一实施的半导体组件包含一基板、一初始层及一缓冲堆栈结构。该初始层设置于该基板之上且包含氮化铝(AlN)。该缓冲堆栈结构设置于该初始层之上,该缓冲堆栈结构包含多个基层及至少一掺杂层,该至少一掺杂层设置于相邻二层基层之间,该基层包含氮化铝镓,该至少一掺杂层包含氮化铝镓或氮化硼铝镓(BAlGaN);其中在该缓冲堆栈结构之中,该基层的铝浓度渐减且镓浓度渐增,该基层实质上不含碳,该至少一掺杂层的掺质为碳或铁。
本发明另一实施的半导体组件包含一基板、一初始层及多个缓冲堆栈结构。该初始层设置于该基板之上且包含氮化铝。该多个缓冲堆栈结构设置于该初始层之上。至少一缓冲堆栈结构包含一第一基层、一第一掺杂层、一第二基层,该第一基层及该第二基层的铝浓度实质相同,该第一掺杂层夹置于该第一基层及该第二基层之间。该第一基层及该第二基层包含氮化铝镓,该第一掺杂层包含氮化铝镓或氮化硼铝镓,该第一掺杂层的掺质为碳或铁,该第一基层及该第二基层实质上不含碳。
本发明的半导体组件藉由在缓冲堆栈结构之中***具有掺质(碳或铁)的掺杂层,降低缓冲堆栈结构的导电度(即增加缓冲堆栈结构的绝缘度),进而有效地提升半导体组件的崩溃电压(Breakdown voltage)。现有技术在AlGaN构成的整个缓冲层中连续地掺杂掺质;然而,在整个AlGaN层中连续地掺杂掺质导致结晶度及粗糙度变差,并增加半导体组件的整体翘曲。相对地,本发明的半导体组件在具有掺质的掺杂层的上方,磊晶成长不具有掺质的基层,藉以修复磊晶层的结晶度、粗糙度(基层不具有掺质,因此结晶度、粗糙度提升)。本发明的技术在掺杂层(具有掺质因而结晶度及粗糙度较差)的上方磊晶成长不具有掺质的基层,藉以修复及提升磊晶层的结晶度、粗糙度之后,再磊晶成长另一层具有掺质的掺杂层。如此,本发明的技术交错地磊晶成长基层(不具有掺质)及掺杂层(具有掺质),即在缓冲堆栈结构中非连续性地掺杂掺质,提升半导体组件的崩溃电压(由具有掺质的掺杂层予以实现),且一并兼顾半导体组件的结晶度、粗糙度(由不具有掺质的基层予以实现)。
此外,本发明的半导体组件在具有掺质的掺杂层之间,***不具有掺质的基层,避免缓冲堆栈结构全部由具有掺质的掺杂层构成,即在缓冲堆栈结构中非连续性地掺杂掺质,因此半导体组件的整体翘曲(bowing)问题得以减缓。因此,本发明的技术交错地磊晶成长基层(不具有掺质)及掺杂层(具有掺质),除了提升半导体组件的崩溃电压,且一并兼顾半导体组件的整体翘曲,避免在完成磊晶制程后的冷却过程,半导体组件因过度翘曲而破裂。
上文已相当广泛地概述本发明的技术特征及优点,使下文的本发明详细描述得以获得较佳了解。构成本发明的权利要求所述的其它技术特征及优点将描述于下文。本发明所属技术领域中普通技术人员应了解,可相当容易地利用下文揭示的概念与特定实施例可作为修改或设计其它结构或制程而实现与本发明相同的目的。本发明所属技术领域中普通技术人员亦应了解,这类等效建构无法脱离所附的权利要求界定的本发明的精神和范围。
附图说明
图1显示本发明一实施例的半导体组件的剖示图;
图2至图4显示本发明的半导体组件的掺质的浓度变化;
图5显示本发明另一实施例的半导体组件的剖示图;
图6显示本发明另一实施例的半导体组件的剖示图。
附图标记:
10 半导体组件
11 基板
13 初始层
20 缓冲堆栈结构
21 基层
23 掺杂层
31 电子输送层
33 电子供应层
40 半导体组件
50 缓冲堆栈结构
51A 第一基层
51B 第二基层
51C 第三基层
53A 第一掺杂层
53B 第二掺杂层
60 半导体组件
70 缓冲堆栈结构
具体实施方式
为了使普通技术人员能彻底地了解本发明,将在下列的描述中提出详尽的步骤及结构。显然地,本发明的实现并未限定于相关领域的普通技术人员所熟习的特殊细节。另一方面,众所周知的结构或步骤并未描述于细节中,以避免造成本发明不必要的限制。本发明的较佳实施例会详细描述如下,然而除了这些详细描述之外,本发明还可以广泛地施行在其他实施例中,且本发明的范围不受限定,其以所附权利要求界定为准。
图1显示本发明一实施例的半导体组件10的剖示图。在本发明一实施例中,半导体组件10包含一基板11;基板11系一硅基板或具有硅表面的基板,例如Si(111)、Si(100)、Si(110)、纹理硅表面(texturedSi surface)、绝缘层上覆硅(Silicon on insulation,SOI)、蓝宝石上覆硅(Silicon on sapphire,SOS)、键合于其它材料(AlN、钻石或其它多晶材料)的硅晶圆。可用于取代Si基板的基板包括SiC基板、蓝宝石基板、GaN基板以及GaAs基板。基板可为半绝缘性基板或导电性基板。
半导体组件10包含一初始层13,设置于基板11的上,且包含氮化铝。在本发明一实施例中,初始层13以磊晶技术成长在具有(111)平面的上表面的Si基板上,具有大约200纳米的厚度。AlN的磊晶生长以三甲胺气体(TMA)与氨气(NH3)的混合气体作为反应气体,在Si基板上形成初始层13。初始层13的碳(Carbon)浓度实质小于1E16/cm3。
半导体组件10包含一缓冲堆栈结构20,设置于初始层13之上。在本发明一实施例中,半导体组件10包含至少一掺杂层23,设置于相邻二层基层21之间。在本发明一实施例中,缓冲堆栈结构20包含多个基层21及多个掺杂层23,交错地堆栈在初始层13之上。在本发明一实施例中,基层21包含氮化铝镓,掺杂层23包含氮化铝镓或氮化硼铝镓。基层21实质上不含碳,掺杂层23的掺质为碳或铁。在本发明一实施例中,掺杂层23可为C-AlGaN、C-BAlGaN、Fe-AlGaN或Fe-BAlGaN。
在本发明一实施例中,掺杂层23的厚度介于10埃至1微米之间,掺杂层23与基层21的厚度比例介于0.001至1.0之间。在本发明一实施例中,掺杂层23的掺质的浓度介于1E18/cm3至1E20/cm3,基层21的掺质的浓度小于1E18/cm3。
在本发明一实施例中,缓冲堆栈结构20包含4层基层21,其中基层21的铝浓度由下而上分别为x1、x2、x3、x4,镓浓度由下而上分别为1-x1、1-x2、1-x3、1-x4,其中浓度的关系可为x1>x2>x3>x4。换言之,缓冲堆栈结构20的基层21的铝浓度由下而上渐减且镓浓度由下而上渐增。
在本发明一实施例中,掺杂层23的的铝浓度由下而上分别为y1、y2、y3;其中铝浓度的关系可为y1=y2=y3、y1≠y2≠y3、y1>y2>y3或y1<y2<y3。在本发明一实施例中,x4<y3<x3<y2<x2<y1<x1。
在本发明一实施例中,缓冲堆栈结构20包含4层基层21及3层掺杂层23。4层基层21的厚度由下而上分别为da1、da2、da3、da4;其中厚度的关系可为da1=da2=da3=da4、da1≠da2≠da3≠da4、da1>da2>da3>da4或da1<da2<da3<da4。3层掺杂层23的厚度由下而上分别为dc1、dc2、dc3,其中厚度的关系可为dc1=dc2=dc3、dc1≠dc2≠dc3、dc1>dc2>dc3或dc1<dc2<dc3。
半导体组件10包含电子输送层31以及电子供应层33,设置于缓冲堆栈结构20之上。在半导体组件10中,介于电子输送层31与电子供应层33之间的边界附近产生二维电子气体,其中半导体组件10系以化合物半导体(此处为GaN)与电子供应层5的化合物半导体(此处为AlGaN)之间的材料异质间因自发极化与压电极化而产生二维电子气体。
在本发明一实施例中,缓冲堆栈结构20的底部系以不具有掺质的基层21接触初始层13;缓冲堆栈结构20的顶部以不具有掺质的基层21接触电子输送层31。换言之,半导体组件10的缓冲堆栈结构20并未以具有掺质的掺杂层23接触初始层13及电子输送层31。
图2至图4显示本发明的半导体组件10的掺质的浓度变化。在本发明一实施例中,掺质的浓度在缓冲堆栈结构20中呈非连续性变化,例如呈δ变化,如图2至图4所示。在本发明一实施例中,缓冲堆栈结构20的三层掺杂层23的掺质的浓度可以逐渐增加(例如图2)、逐渐减少(例如图3)、或维持实质相同(例如图4)。在本发明一实施例中,掺杂层23的掺质的浓度高于基层21的掺质的浓度;从基层21到掺杂层23,掺质的浓度增加;从掺杂层23到基层21,掺质的浓度减少。
本发明的半导体组件10藉由在缓冲堆栈结构20之中***具有掺质的掺杂层23,降低缓冲堆栈结构20的导电度(即增加缓冲堆栈结构20的绝缘度),进而有效地提升半导体组件10的崩溃电压。相较于不具有掺质的基层21,具有掺质的掺杂层23的结晶度及粗糙度较差;此外,具有掺质的掺杂层23亦增加半导体组件10的整体翘曲。因此,半导体组件的缓冲堆栈结构不宜全部采用具有掺质的掺杂层。
现有技术在AlGaN构成的整个缓冲层中连续地掺杂掺质;然而,在整个AlGaN层中连续地掺杂掺质导致结晶度及粗糙度变差,并增加半导体组件的整体翘曲。相对地,本发明的半导体组件10在具有掺质的掺杂层23的上方,磊晶成长不具有掺质的基层21,藉以修复磊晶层的结晶度、粗糙度(基层21不具有掺质,因此可以维持相对较佳的结晶度、粗糙度)。本发明的技术在掺杂层23(具有掺质因而结晶度及粗糙度较差)的上方磊晶成长不具有掺质的基层21,藉以修复及提升磊晶层的结晶度、粗糙度之后,再磊晶成长另一层具有掺质的掺杂层23。如此,本发明的技术交错地磊晶成长基层21(不具有掺质)及掺杂层23(具有掺质),即在缓冲堆栈结构20中非连续性地掺杂掺质,提升半导体组件10的崩溃电压(由具有掺质的掺杂层23予以实现),且一并兼顾半导体组件10的结晶度、粗糙度(由不具有掺质的基层21予以实现)。
此外,在具有掺质的掺杂层23之间,***不具有掺质的基层21,避免缓冲堆栈结构20全部由具有掺质的掺杂层23构成,即在缓冲堆栈结构20中非连续性地掺杂掺质,因此半导体组件10的整体翘曲问题得以减缓。因此,本发明的技术交错地磊晶成长基层21(不具有掺质)及掺杂层23(具有掺质),除了提升半导体组件10的崩溃电压,且一并兼顾半导体组件10的整体翘曲,避免在完成磊晶制程后的冷却过程,半导体组件10因过度翘曲而破裂。
图5显示本发明另一实施例的半导体组件40的剖示图。在图5所示的实施例中,与图1的半导体组件10相同的技术内容将不予赘述。在本发明的实施例中,半导体组件40可包含多个缓冲堆栈结构50。在本发明一实施例中,至少一缓冲堆栈结构50包含一第一基层51A、一第一掺杂层53A、一第二基层51B,第一掺杂层53A夹置于第一基层51A及第二基层之间51B,即第一掺杂层53A设置于缓冲堆栈结构50的内部。
相较于图1的半导体组件10采用基层21及掺杂层23的交错膜层结构实现缓冲堆栈结构20,图5的半导体组件40采用三明治膜层结构的缓冲堆栈结构50。在本发明的一实施例中,各缓冲堆栈结构50包含一第一基层51A、一第一掺杂层53A及一第二基层51B,第一基层51A及第二基层51B包含氮化铝镓,第一掺杂层53A包含氮化铝镓或氮化硼铝镓,第一掺杂层53A夹置于第一基层51A及第二基层51B之间,第一基层51A及第二基层51B的铝浓度实质相同,第一基层51A及第二基层51B实质上不含碳,第一掺杂层53A的掺质为碳或铁。在本发明一实施例中,第一掺杂层53A可为C-AlGaN、C-BAlGaN、Fe-AlGaN或Fe-BAlGaN。
在本发明一实施例中,缓冲堆栈结构50的第一掺杂层53A的厚度介于10埃至1微米之间,第一掺杂层53A与第一基层51A(第二基层51B)的厚度比例介于0.001至1.0之间。在本发明一实施例中,第一掺杂层53A的掺质的浓度介于1E18/cm3至1E20/cm3,第一基层51A(第二基层51B)的掺质的浓度小于1E18/cm3。
在本发明一实施例中,半导体组件40包含4个缓冲堆栈结构50,第一基层51A与第二基层51B的组成实质相同,铝浓度由下而上分别为x1、x2、x3、x4,镓浓度由下而上分别为1-x1、1-x2、1-x3、1-x4;其中浓度的关系可为x1>x2>x3>x4。换言之,缓冲堆栈结构50的4层第一基层51A(第二基层51B)的铝浓度由下而上渐减且镓浓度由下而上渐增。在本发明一实施例中,4层第一掺杂层53A的铝浓度由下而上分别为y1、y2、y3、y4;其中铝浓度的关系可为y1=y2=y3=y4、y1≠y2≠y3≠y4、y1>y2>y3>y4或y1<y2<y3<y4。
在本发明一实施例中,半导体组件40包含4个缓冲堆栈结构50,第一基层51A与第二基层51B的厚度实质相同,厚度由下而上分别为da1、da2、da3、da4;其中厚度的关系可为da1=da2=da3=da4、da1≠da2≠da3≠da4、da1>da2>da3>da4或da1<da2<da3<da4;4层第一掺杂层53A的厚度由下而上分别为dc1、dc2、dc3、dc4,其中厚度的关系可为dc1=dc2=dc3=dc4、dc1≠dc2≠dc3≠dc4、dc1>dc2>dc3>dc4或dc1<dc2<dc3<dc4。
在本发明一实施例中,缓冲堆栈结构50的底部以不具有掺质的第一基层51A接触初始层13;缓冲堆栈结构50的顶部以不具有掺质的第二基层51B接触电子输送层31。换言之,半导体组件40的缓冲堆栈结构50并未以具有掺质的第一掺杂层53A接触初始层13及电子输送层31。
在本发明一实施例中,掺质的浓度在多个缓冲堆栈结构50中呈非连续性变化,例如呈δ变化,如图2至图4所示。在本发明一实施例中,半导体组件40的四层第一掺杂层53A的掺质的浓度可以逐渐增加(例如图2)、逐渐减少(例如图3)、或维持实质相同(例如图4)。在本发明一实施例中,第一掺杂层53A的掺质的浓度高于第一基层51A(第二基层51B)的掺质的浓度;从第一基层51A到第一掺杂层53A,掺质的浓度增加;从第一掺杂层53A到第二基层51B,掺质的浓度减少。
本发明的半导体组件40藉由在缓冲堆栈结构50之中***具有掺质的第一掺杂层53A,降低缓冲堆栈结构50的导电度(即增加缓冲堆栈结构25的绝缘度),进而有效地提升半导体组件40的崩溃电压。相较于不具有掺质的第一基层51A(第二基层51B),具有掺质的第一掺杂层53A的结晶度及粗糙度较差;此外,具有掺质的第一掺杂层53A亦增加半导体组件40的整体翘曲。
现有技术在AlGaN构成的整个缓冲层中连续地掺杂掺质;然而,在整个AlGaN层中连续地掺杂掺质导致结晶度及粗糙度变差,并增加半导体组件的整体翘曲。相对地,本发明的半导体组件40在具有掺质的第一掺杂层53A的下方及上方,分别磊晶成长不具有掺质的第一基层51A及第二基层51B,藉以修复磊晶层的结晶度、粗糙度(第一基层51A及第二基层51B不具有掺质,因此可以维持相对较佳的结晶度、粗糙度)。本发明的技术在第一掺杂层53A(具有掺质因而结晶度及粗糙度较差)的下方及上方分别磊晶成长不具有掺质的第一基层51A及第二基层51B,藉以修复及提升磊晶层的结晶度、粗糙度之后,再磊晶成长另一层具有掺质的第一掺杂层53A。如此,本发明的技术交错地磊晶成长不具有掺质的膜层(第一基层51A及第二基层51B)与具有掺质的第一掺杂层53A,除了可以提升半导体组件40的崩溃电压(由具有掺质的第一掺杂层53A予以实现),且一并兼顾半导体组件40的结晶度、粗糙度(由不具有掺质的第一基层51A及第二基层51B予以实现)。
此外,本发明的半导体组件40在具有掺质的第一掺杂层53A的下方及上方磊晶成长第一基层51A及第二基层51B,避免缓冲堆栈结构50全部由具有掺质的第一掺杂层53A构成,即在缓冲堆栈结构50中非连续性地掺杂掺质,因此半导体组件40的整体翘曲问题得以减缓。因此,本发明的技术交错地磊晶成长不具有掺质的膜层(第一基层51A及第二基层51B)及具有掺质的第一掺杂层53A,除了可以提升半导体组件40的崩溃电压,且一并兼顾半导体组件40的整体翘曲,避免在完成磊晶制程后的冷却过程,半导体组件40因过度翘曲而破裂。
图6显示本发明另一实施例的半导体组件60的剖示图。在图6所示的实施例中,与图1的半导体组件10或图5的半导体组件40相同的技术内容将不予赘述。相较于图5的半导体组件40采用多个三明治膜层结构实现的缓冲堆栈结构50,图6的半导体组件60采用多个5层膜层结构实现的缓冲堆栈结构70。
在本发明的实施例中,半导体组件60的缓冲堆栈结构70除了第一基层51A、第一掺杂层53A、第二基层51B之外,另包含一第二掺杂层53B、一第三基层51C,该第二掺杂层53B夹置于该第二基层51B及该第三基层51C之间。
在本发明的实施例中,该第三基层51C包含氮化铝镓;第二掺杂层51B包含氮化铝镓或氮化硼铝镓。在本发明一实施例中,第二掺杂层51B的掺质为碳或铁,可为C-AlGaN、C-BAlGaN、Fe-AlGaN或Fe-BAlGaN。在各缓冲堆栈结构70之中,该第一基层51A、该第二基层51B及该第三基层51C的铝浓度实质相同,实质上不含碳。
简言之,图6的半导体组件60在氮化铝镓(AlGaN)构成的基层之中,***二层掺杂层而实现缓冲堆栈结构,其中二层掺杂层的掺质浓度可以相同或不同。相对地,图5的半导体组件40可视为在氮化铝镓构成的基层之中,***一层掺杂层而实现缓冲堆栈结构。此外,图6的半导体组件60亦可选择性地在氮化铝镓构成的基层之中,***三层或更多层的掺杂层而实现缓冲堆栈结构。
本发明的技术内容及技术特点已揭示如上,然而本发明所属技术领域中普通技术人员应了解,在不背离所附权利要求界定的本发明精神和范围内,本发明的启示及揭示可作种种的替换及修饰。例如,上文揭示的许多制程可以不同的方法实施或以其它制程予以取代,或者采用上述二种方式的组合。
此外,本案的权利范围并不局限于上文揭示的特定实施例的制程、机台、制造、物质的成份、装置、方法或步骤。本发明所属技术领域中普通技术人员应了解,基于本发明启示及揭示制程、机台、制造、物质的成份、装置、方法或步骤,无论现在已存在或日后开发者,其与本案实施例揭示以实质相同的方式执行实质相同的功能,而达到实质相同的结果,亦可使用于本发明。因此,以下的权利要求涵盖此类制程、机台、制造、物质的成份、装置、方法或步骤。
Claims (29)
1.一种半导体组件,其特征在于,包括:
一基板;
一初始层,设置于所述基板之上,所述初始层包含氮化铝;以及
一缓冲堆栈结构,设置于所述初始层之上,所述缓冲堆栈结构包含多个基层及至少一掺杂层,所述至少一掺杂层设置于相邻二层基层之间,所述基层包含氮化铝镓,所述掺杂层包含氮化铝镓或氮化硼铝镓;
其中在所述缓冲堆栈结构之中,所述多个基层的铝浓度渐减且镓浓度渐增,所述多个基层实质上不含碳,所述至少一掺杂层的掺质为碳或铁。
2.根据权利要求1所述的半导体组件,其特征在于,包含多个掺杂层,所述多个掺杂层与所述多个基层交错地堆栈在所述初始层之上。
3.根据权利要求1所述的半导体组件,其特征在于,所述至少一掺杂层的厚度介于10埃至1微米之间。
4.根据权利要求1所述的半导体组件,其特征在于,所述至少一掺杂层与所述基层的厚度比例介于0.001至1.0之间。
5.根据权利要求1所述的半导体组件,其特征在于,所述至少一掺杂层的掺质的浓度介于1E18/cm3至1E20/cm3。
6.根据权利要求1所述的半导体组件,其特征在于,所述多个基层的掺质的浓度小于1E18/cm3。
7.根据权利要求1所述的半导体组件,其特征在于,在所述缓冲堆栈结构之中,所述掺质的浓度呈波浪状变化。
8.根据权利要求1所述的半导体组件,其特征在于,在所述缓冲堆栈结构之中,所述掺质的浓度呈非连续性变化。
9.根据权利要求1所述的半导体组件,其特征在于,在所述缓冲堆栈结构之中,从所述基层到所述掺杂层,所述掺质的浓度增加。
10.根据权利要求1所述的半导体组件,其特征在于,在所述缓冲堆栈结构之中,从所述掺杂层到所述基层,所述掺质的浓度减少。
11.根据权利要求1所述的半导体组件,其特征在于,所述缓冲堆栈结构以所述基层接触所述初始层。
12.根据权利要求1所述的半导体组件,其特征在于,另包含一电子输送层,设置于所述缓冲堆栈结构之上,其中所述缓冲堆栈结构以所述基层接触所述电子输送层。
13.一种半导体组件,其特征在于,包括:
一基板;
一初始层,设置于所述基板之上,所述初始层包含氮化铝;以及
多个缓冲堆栈结构,设置于所述初始层之上;
其中至少一缓冲堆栈结构包含一第一基层、一第一掺杂层、一第二基层,所述第一基层及所述第二基层的铝浓度实质相同,所述第一掺杂层夹置于所述第一基层及所述第二基层之间;
其中所述第一基层及所述第二基层包含氮化铝镓,所述第一掺杂层包含氮化铝镓或氮化硼铝镓,所述第一掺杂层的掺质系碳或铁,所述第一基层及所述第二基层实质上不含碳。
14.根据权利要求13所述的半导体组件,其特征在于,各缓冲堆栈结构包含所述第一掺杂层,夹置于所述第一基层及所述第二基层之间。
15.根据权利要求13所述的半导体组件,其特征在于,所述第一掺杂层的厚度介于10埃至1微米之间。
16.根据权利要求13所述的半导体组件,其特征在于,所述第一掺杂层与所述第一基层的厚度比例介于0.001至1.0之间。
17.根据权利要求13所述的半导体组件,其特征在于,所述第一掺杂层与所述第二基层的厚度比例介于0.001至1.0之间。
18.根据权利要求13所述的半导体组件,其特征在于,所述第一掺杂层的掺质的浓度介于1E18/cm3至1E20/cm3。
19.根据权利要求13所述的半导体组件,其特征在于,所述第一基层及所述第二基层的碳的浓度小于1E18/cm3。
20.根据权利要求13所述的半导体组件,其特征在于,在所述多个缓冲堆栈结构之中,所述第一基层及所述第二基层的铝浓度渐减且镓浓度渐增。
21.根据权利要求13所述的半导体组件,其特征在于,在所述多个缓冲堆栈结构之中,所述掺质的浓度呈波浪状变化。
22.根据权利要求13所述的半导体组件,其特征在于,在所述多个缓冲堆栈结构之中,所述掺质的浓度呈非连续性变化。
23.根据权利要求13所述的半导体组件,其特征在于,在所述缓冲堆栈结构之中,从所述第一基层到所述第一掺杂层,所述掺质的浓度增加。
24.根据权利要求13所述的半导体组件,其特征在于,在所述缓冲堆栈结构之中,从所述第一掺杂层到所述第二基层,所述掺质的浓度减少。
25.根据权利要求13所述的半导体组件,其特征在于,所述缓冲堆栈结构以所述第一基层接触所述初始层。
26.根据权利要求13所述的半导体组件,其特征在于,另包含一电子输送层,设置于所述缓冲堆栈结构之上,其中所述缓冲堆栈结构以所述第二基层接触所述电子输送层。
27.根据权利要求13所述的半导体组件,其特征在于,所述至少一缓冲堆栈结构另包含一第二掺杂层及一第三基层,所述第二掺杂层夹置于所述第二基层及所述第三基层之间。
28.根据权利要求27所述的半导体组件,其特征在于,所述第二掺杂层包含氮化铝镓或氮化硼铝镓,所述第三基层实质上不含碳。
29.根据权利要求27所述的半导体组件,其特征在于,在各缓冲堆栈结构之中,所述第一基层、所述第二基层及所述第三基层的铝浓度实质相同。
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110062556A1 (en) * | 2009-09-14 | 2011-03-17 | Covalent Materials Corporation | Compound semiconductor substrate |
CN103022120A (zh) * | 2011-09-20 | 2013-04-03 | 先进动力设备技术研究协会 | 氮化物半导体元件及制造方法 |
US20130334495A1 (en) * | 2012-06-15 | 2013-12-19 | Dae-Ho Lim | Superlattice structure, semiconductor device including the same, and method of manufacturing the semiconductor device |
US20140061665A1 (en) * | 2012-09-03 | 2014-03-06 | Hitachi Metals, Ltd. | Nitride semiconductor wafer |
CN104137226A (zh) * | 2012-02-03 | 2014-11-05 | 创世舫电子有限公司 | 适用于具有异质衬底的iii族氮化物器件的缓冲层结构 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004165387A (ja) * | 2002-11-12 | 2004-06-10 | Furukawa Electric Co Ltd:The | GaN系電界効果トランジスタ |
TWI230978B (en) * | 2003-01-17 | 2005-04-11 | Sanken Electric Co Ltd | Semiconductor device and the manufacturing method thereof |
JP4525894B2 (ja) * | 2003-11-21 | 2010-08-18 | サンケン電気株式会社 | 半導体素子形成用板状基体及びこの製造方法及びこれを使用した半導体素子 |
JP5224311B2 (ja) * | 2007-01-05 | 2013-07-03 | 古河電気工業株式会社 | 半導体電子デバイス |
JP2009021279A (ja) * | 2007-07-10 | 2009-01-29 | Hitachi Cable Ltd | 半導体エピタキシャルウエハ |
JP2013145782A (ja) * | 2012-01-13 | 2013-07-25 | Sharp Corp | ヘテロ接合型電界効果トランジスタ用のエピタキシャルウエハ |
WO2013137476A1 (ja) * | 2012-03-16 | 2013-09-19 | 次世代パワーデバイス技術研究組合 | 半導体積層基板、半導体素子、およびその製造方法 |
JP6151487B2 (ja) * | 2012-07-10 | 2017-06-21 | 富士通株式会社 | 化合物半導体装置及びその製造方法 |
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JP2014072431A (ja) * | 2012-09-28 | 2014-04-21 | Fujitsu Ltd | 半導体装置 |
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110062556A1 (en) * | 2009-09-14 | 2011-03-17 | Covalent Materials Corporation | Compound semiconductor substrate |
CN103022120A (zh) * | 2011-09-20 | 2013-04-03 | 先进动力设备技术研究协会 | 氮化物半导体元件及制造方法 |
CN104137226A (zh) * | 2012-02-03 | 2014-11-05 | 创世舫电子有限公司 | 适用于具有异质衬底的iii族氮化物器件的缓冲层结构 |
US20130334495A1 (en) * | 2012-06-15 | 2013-12-19 | Dae-Ho Lim | Superlattice structure, semiconductor device including the same, and method of manufacturing the semiconductor device |
US20140061665A1 (en) * | 2012-09-03 | 2014-03-06 | Hitachi Metals, Ltd. | Nitride semiconductor wafer |
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