CN106024895A - 一种集成肖特基二极管的积累型屏蔽栅mosfet - Google Patents
一种集成肖特基二极管的积累型屏蔽栅mosfet Download PDFInfo
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Abstract
本发明属于半导体技术，特别涉及一种积累型的屏蔽栅MOSFET集成肖特基二极管，形成于硅衬底上且屏蔽栅MOSFET和肖特基二极管的形成区域分开且相邻。积累型屏蔽栅MOSFET具有屏蔽栅的结构，肖特基二极管具有和屏蔽栅MOSFET同样的沟槽结构；肖特基二极管通过源极金属填充到沟槽顶部来在沟槽侧面形成肖特基接触，减少了占用的芯片面积；同时，肖特基二极管的形成工艺与MOSFET形成工艺兼容，减少了工艺步骤。肖特基二极管反向偏置时，槽14内的多晶硅7与N+型漂移区2之间存在电场，N+型漂移区2产生耗尽，耗尽区向N+型漂移区2内扩展，最终完全耗尽，防护了肖特基结的击穿，减小了肖特基二极管反向的漏电流。
Description
技术领域
本发明属于半导体技术领域，特别涉及一种集成肖特基二极管的积累型屏蔽栅MOSFET。
背景技术
高性能转换器设计中的同步整流对于低电压、高电流应用至关重要，这是因为通过将肖特基整流替换为同步整流MOSFET能够显著提高效率和功率密度。在实际应用中，同步整流MOSFET的功率损耗主要由导通损耗、开关损耗以及体二极管导通损耗等组成。例如，在DC-DC转换电路中，低边的功率开关的功率损耗中，体二极管的导通损耗仍然影响MOSFET的总体损耗。随着功率开关应用中高频和大电流的要求的提高，降低功率损耗的需求受到了越来越多的重视。
为了降低功率MOSFET体二极管的功率损耗，采用MOSFET与肖特基二极管并联的方式，由于肖特基二极管的正向开启电压(约为0.35V)比PN结二极管的内建电势(约0.7V)小，因此减少体二极管正向开启电压，减小体二极管死区损耗。
传统的集成肖特基二极管的MOSFET中，源极金属和N型漂移区接触形成肖特基二极管，例如美国专利No.6531,102号专利中提出，漂移区的掺杂浓度需要进行调整以便和源极金属形成肖特基势垒。为了获得更低的导通电阻，US 7400,014号专利提出了一种积累型MOSFET集成肖特基二极管，如图2所示，漂移区电阻得以降低。但是该专利中，肖特基二极管在反偏时漏电流较大，同时，额外的肖特基沟槽34和槽36占用了较大的芯片面积，并且工艺步骤较为复杂。
发明内容
本发明的目的，就是为了解决肖特基二极管反偏时漏电较大，且工艺步骤复杂的问题，提出了一种集成肖特基二极管的积累型屏蔽栅MOSFET，工艺相对简单且容易控制，还节约了芯片面积。
本发明的技术方案：一种集成肖特基二极管的积累型屏蔽栅MOSFET，如图1所示，包括MOSFET区域12和肖特基区域13；所述MOSFET区域12和肖特基区域13均包括从下至上依次层叠设置的第一金属层11、N++型重掺杂衬底1、N+型漂移区2、N-型掺杂区3和第二金属层10；所述MOSFET区域12的N-型掺杂区3中具有第一槽5和N+型重掺杂区4；所述N+型重掺杂区4的上表面与第二金属层10接触；所述第一槽5位于N+型重掺杂区4之间，且第一槽5的下端延伸至N+型漂移区2中；所述第一槽5的上表面与第二金属层10接触，所述第一槽5中填充有介质6，所述第一槽5中还具有第一多晶硅7和第二多晶硅8，所述第一多晶硅7和第二多晶硅8均位于介质6中，且第二多晶硅8位于第一多晶硅7的上方；所述肖特基区域13的N-型掺杂区3中具有第二槽14，所述第二槽14的下端延伸至N+型漂移区2中；所述第二槽14的上表面与第二金属层10接触，第二槽14的上部填充有金属9，第二槽14的下部填充有介质6，且金属9的结深小于N-型掺杂区3的结深；所述第二槽14中的介质6中具有第一多晶硅7；所述第二金属层10与源电极相连，所述第一多晶硅7与源电极相连，所述第二多晶硅8与栅电极相连，所述第一金属层11与漏电极相连；所述N+型漂移区2的掺杂浓度小于N++型重掺杂衬底1的掺杂浓度两个数量级；所述的N-型掺杂区3的掺杂浓度小于N+型漂移区2的掺杂浓度一到两个数量级。
本发明总的技术方案，相对于传统结构，本发明的MOSFET具有屏蔽栅极结构，减小了栅极电荷。同时，积累型MOSFET的导通电阻较小，且不存在少子存储效应，提高了开关速度；同时，肖特基二极管的形成工艺与MOSFET形成工艺兼容，减少了工艺步骤。同时，位于肖特基二极管下方的多晶硅7与源电极相连，在肖特基二极管导通时，在多晶硅7两侧形成积累层，减小了肖特基二极管的导通压降。肖特基二极管反向偏置时，多晶硅7与N+型漂移区之间存在电场，N+型漂移区产生耗尽，耗尽区向N+型漂移区内扩展，最终完全耗尽，防护了肖特基结的击穿，减小了漏电流
所述介质6可以是二氧化硅，在不同位置其厚度不同。位于多晶硅8两侧时，厚度为5nn-100nm，在多晶硅7与多晶硅8之间的厚度为200nm-400nm，在多晶硅7与金属层9之间的厚度为200nm-400nm。
进一步的，所述肖特基区域与MOSFET区域分开且相邻。
本发明的有益效果为：提高了开关速度，减小了肖特基二极管的导通压降，肖特基二极管反向偏置时，防护了肖特基结的击穿，减小了漏电流。
附图说明
图1是本发明所提供的一种集成肖特基二极管的积累型屏蔽栅MOSFET的结构示意图；
图2是专利号US 7400,014提供的一种积累型的MOSFET结合肖特基二极管的结构示意图；
图3是本发明所提供的一种集成肖特基二极管的积累型屏蔽栅MOSFET在肖特基二极管导通时的电流图；
图4是本发明所提供的一种集成肖特基二极管的积累型屏蔽栅MOSFET在肖特基二极管反偏时的位于肖特基二极管区域N+型漂移区内的耗尽线图；
图5是本发明所提供的一种集成肖特基二极管的积累型屏蔽栅MOSFET的版图布局；
图6-9是本发明所提供的一种集成肖特基二极管的积累型屏蔽栅MOSFET的关键步骤的工艺流程图。
具体实施方式
下面结合附图对本发明进行详细的描述。
本发明所述的一种集成肖特基二极管的积累型屏蔽栅MOSFET，如图1所示，包括MOSFET区域12和肖特基区域13；所述MOSFET区域12和肖特基区域13均包括从下至上依次层叠设置的第一金属层11、N++型重掺杂衬底1、N+型漂移区2、N-型掺杂区3和第二金属层10；所述MOSFET区域12的N-型掺杂区3中具有第一槽5和N+型重掺杂区4；所述N+型重掺杂区4的上表面与第二金属层10接触；所述第一槽5位于N+型重掺杂区4之间，且第一槽5的下端延伸至N+型漂移区2中；所述第一槽5的上表面与第二金属层10接触，所述第一槽5中填充有介质6，所述第一槽5中还具有第一多晶硅7和第二多晶硅8，所述第一多晶硅7和第二多晶硅8均位于介质6中，且第二多晶硅8位于第一多晶硅7的上方；所述肖特基区域13的N-型掺杂区3中具有第二槽14，所述第二槽14的下端延伸至N+型漂移区2中；所述第二槽14的上表面与第二金属层10接触，第二槽14的上部填充有金属9，第二槽14的下部填充有介质6，且金属9的结深小于N-型掺杂区3的结深；所述第二槽14中的介质6中具有第一多晶硅7；所述第二金属层10与源电极相连，所述第一多晶硅7与源电极相连，所述第二多晶硅8与栅电极相连，所述第一金属层11与漏电极相连；所述N+型漂移区2的掺杂浓度小于N++型重掺杂区1的掺杂浓度两个数量级；所述的N-型掺杂区3的掺杂浓度小于N+型漂移区2的掺杂浓度一到两个数量级。
本发明的工作原理为：
本发明所提供的一种集成肖特基二极管的积累型屏蔽栅MOSFET，所述MOSFET的源极作为肖特基二极管的阳极，所述MOSFET背面的漏极作为肖特基二极管的阴极。
积累型MOSFET正向导通时，槽5两侧的N-漂移区内形成一层薄电子积累层，减小了MOSFET的正向导通电阻；此时，肖特基二极管的阴极相对于阳极接高电位，肖特基结反偏，肖特基二极管处于反向阻断状态。槽14内的多晶硅7与源极相连，为零电位，与N-漂移区之间存在横向电场，因此，N+漂移区内形成耗尽层，且耗尽层随着电压的增大逐渐向N-区体内扩展，最终槽14之间的N-漂移区完全耗尽，防护了肖特基结的击穿。因此源漏之间的电压较低时，金属层9与N-掺杂区3形成的肖特基结承担耐压，源漏之间的电压较高时，如图4所示，肖特基结下方N+型漂移区耗尽承受耐压，减小了肖特基二极管反向偏压时的泄露电流。
肖特基结二极管正向导通时，如图3所示，其阳极相对于阴极接高电位，即积累型MOSFET的源极相对于漏极接高电位。肖特基二极管导通，金属层9与N-掺杂区3之间形成的肖特基结处于正向偏置，电子越过势垒从半导体中进入金属界面；槽14内的多晶硅7与源极电位相连，在源极接高电位时，在槽14两侧形成电子积累层，降低了肖特基二极管正向导通压降，减小了肖特基二极管的导通损耗。
图5所示为本发明所述的一种集成肖特基二极管的积累型屏蔽栅MOSFET的版图，版图中包括了沟槽栅MOSFET的形成区域和肖特基二极管的形成区域，栅极区域位于沟槽栅MOSFET的形成区域中。从图5中可以看出MOSFET与肖特基二极管在版图布局上分属die上的不同区域，肖特基二极管的形成区域需要占据一定面积，但是相较于图2中减少了源极场板的区域，并且沟槽的侧面也作为肖特基接触区域，因而肖特基二极管的形成区域所占用的芯片面积能显著减小。
以图1所示的结构为例，本发明结构可以用以下方法制备得到，工艺步骤为：
1、单晶硅准备。采用N型重掺杂单晶硅衬底1，晶向为<100>。
2、外延生长。采用气相外延VPE等方法生长一定厚度和掺杂浓度的N型外延层，形成N+型漂移区2。继续外延生长，形成一定厚度和掺杂浓度的N—型掺杂区3.
3、N+源区的制备。砷注入制备N+型重掺杂区4。
4、槽5和槽14刻蚀。采用离子刻蚀等方法在N型外延层上刻蚀出一定深度和宽度的槽。如图6所示，在N+型漂移区2内刻蚀出积累型MOSFET及肖特基结所需的槽。
5、屏蔽栅电极的制备。如图7所示首先在整个硅片表面淀积氧化层，接着淀积一定厚度的多晶硅形成屏蔽栅电极，最后刻蚀掉硅片表面的多晶硅。
6、栅电极的制备。如图8所示，首先在整个硅片表面淀积氧化层，刻蚀掉槽14内的氧化层。接着在槽5内淀积多晶硅，光刻、刻蚀形成栅电极7，最后，在硅片表面继续淀积氧化层并进行机械磨平。
7、正面金属化阳极。在整个器件表面溅射一层金属铝，槽14内同时填充金属，与N-型掺杂区3形成肖特基接触,最后进行机械磨平，如图9所示。
8、背面减薄、金属化，形成漏电极11。
制作器件时，还可用碳化硅、砷化镓或锗硅等半导体材料替代体硅。
Claims (2)
1.一种集成肖特基二极管的积累型屏蔽栅MOSFET，包括MOSFET区域(12)和肖特基区域(13)；所述MOSFET区域(12)和肖特基区域(13)均包括从下至上依次层叠设置的第一金属层(11)、N++型重掺杂衬底(1)、N+型漂移区(2)、N-型掺杂区(3)和第二金属层(10)；所述MOSFET区域(12)的N-型掺杂区(3)中具有第一槽(5)和N+型重掺杂区(4)；所述N+型重掺杂区(4)的上表面与第二金属层(10)接触；所述第一槽(5)位于N+型重掺杂区(4)之间，且第一槽(5)的下端延伸至N+型漂移区(2)中；所述第一槽(5)的上表面与第二金属层(10)接触，所述第一槽(5)中填充有介质(6)，所述第一槽(5)中还具有第一多晶硅(7)和第二多晶硅(8)，所述第一多晶硅(7)和第二多晶硅(8)均位于介质(6)中，且第二多晶硅(8)位于第一多晶硅(7)的上方；所述肖特基区域(13)的N-型掺杂区(3)中具有第二槽(14)，所述第二槽(14)的下端延伸至N+型漂移区(2)中；所述第二槽(14)的上表面与第二金属层(10)接触，第二槽(14)的上部填充有金属(9)，第二槽(14)的下部填充有介质(6)，且金属(9)的结深小于N-型掺杂区(3)的结深；所述第二槽(14)中的介质(6)中具有第一多晶硅(7)；所述第二金属层(10)与源电极相连，所述第一多晶硅(7)与源电极相连，所述第二多晶硅(8)与栅电极相连，所述第一金属层(11)与漏电极相连；所述N+型漂移区(2)的掺杂浓度小于N++型重掺杂衬底(1)的掺杂浓度两个数量级；所述的N-型掺杂区(3)的掺杂浓度小于N+型漂移区(2)的掺杂浓度一到两个数量级。
2.根据权利要求1所述的一种集成肖特基二极管的积累型屏蔽栅MOSFET，其特征在于，所述肖特基区域与MOSFET区域分开且相邻。
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