CN106024637B - 薄膜晶体管及其制作方法 - Google Patents
薄膜晶体管及其制作方法 Download PDFInfo
- Publication number
- CN106024637B CN106024637B CN201610571403.0A CN201610571403A CN106024637B CN 106024637 B CN106024637 B CN 106024637B CN 201610571403 A CN201610571403 A CN 201610571403A CN 106024637 B CN106024637 B CN 106024637B
- Authority
- CN
- China
- Prior art keywords
- active layer
- source electrode
- lug boss
- layer
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 23
- 238000002360 preparation method Methods 0.000 title description 3
- 238000002161 passivation Methods 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000012212 insulator Substances 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 description 7
- 229910044991 metal oxide Inorganic materials 0.000 description 6
- 150000004706 metal oxides Chemical class 0.000 description 6
- 239000010408 film Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N SnO2 Inorganic materials O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000013517 stratification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
本发明公开了一种薄膜晶体管,其包括:在基板上的栅极、栅极绝缘层、设置于栅极绝缘的凸起部的两端的第一有源层和第二有源层、分别与第一有源层和第二有源层接触的第一源极和第二源极、钝化层、钝化层中的第一过孔和第二过孔、在所述钝化层上且分别通过第一过孔和第二过孔与第一有源层和第二有源层接触的漏极,漏极与第一有源层的接触平面与第一源极与第一有源层的接触平面之间的距离等于凸起部的高度,漏极与第二有源层的接触平面与第二源极与第二有源层的接触平面之间的距离等于凸起部的高度。本发明实现了短沟道的薄膜晶体管,从而使短沟道的薄膜晶体管具有更大的宽长比,具有更大的开态电流。
Description
技术领域
本发明属于半导体技术领域,具体地讲,涉及一种能够实现较短沟道的薄膜晶体管及其制作方法。
背景技术
金属氧化物半导体薄膜晶体管以其良好的器件性能,较低的工艺成本,被认为是下一代平板显示中的关键技术。然而,随着显示器性能的提高,要求金属氧化物半导体薄膜晶体管中的沟道具有更大的宽长比,而沟道的宽长比决定了该金属氧化物半导体薄膜晶体管的功能特性,在沟道的宽度W一定的条件下,缩短沟道的长度L能够使该金属氧化物半导体薄膜晶体管具有更大的宽长比W/L,从而具有更大的开态电流。
然而,传统的金属氧化物半导体薄膜晶体管在制作过程中,沟道的长度L直接受光刻工艺的限制,因此实现短沟道有较大的难度。
发明内容
为了解决上述现有技术存在的问题,本发明提供了一种薄膜晶体管,其包括:基板;在所述基板上的栅极;覆盖所述基板和所述栅极的栅极绝缘层,所述栅极绝缘层覆盖所述栅极的部分凸起,以形成凸起部,所述栅极绝缘层覆盖所述基板的部分未凸起,以形成平坦部;在所述凸起部上且分别位于所述凸起部两端的第一有源层和第二有源层,所述第一有源层和所述第二有源层沿着所述凸起部的侧壁延伸至所述平坦部上;与所述第一有源层接触的第一源极,以及与所述第二有源层接触的第二源极,所述第一源极与所述第二源极彼此连接;覆盖所述第一有源层、所述第二有源层、所述第一源极、所述第二源极和所述栅极绝缘层的钝化层;在所述钝化层中且暴露所述第一有源层的第一过孔,以及在所述钝化层中且暴露所述第二有源层的第二过孔;在所述钝化层上且分别通过所述第一过孔和所述第二过孔与所述第一有源层和所述第二有源层接触的漏极,所述漏极与所述第一有源层的接触平面与所述第一源极与所述第一有源层的接触平面之间的距离等于所述凸起部的高度,所述漏极与所述第二有源层的接触平面与所述第二源极与所述第二有源层的接触平面之间的距离等于所述凸起部的高度。
进一步地,所述第一源极位于延伸至所述平坦部上的所述第一有源层上,所述第二源极位于延伸至所述平坦部上的所述第二有源层上;所述第一过孔和所述第二过孔分别将位于所述凸起部上的第一有源层和第二有源层暴露。
进一步地,所述第一源极位于在所述凸起部上的所述第一有源层上,所述第二源极位于在所述凸起部上的所述第二有源层上;所述第一过孔和所述第二过孔分别将延伸至所述平坦部上的第一有源层和第二有源层暴露。
进一步地,所述第一源极位于所述平坦部与延伸至所述平坦部上的所述第一有源层之间,所述第二源极位于所述平坦部与延伸至所述平坦部上的所述第二有源层之间;所述第一过孔和所述第二过孔分别将位于所述凸起部上的第一有源层和第二有源层暴露。
进一步地,所述栅极的截面形状呈梯形状,所述凸起部的截面形状呈梯形状,所述凸起部的侧壁倾斜。
进一步地,所述栅极的中间部分凸起,且所述栅极的中间部分的截面形状呈梯形状,所述凸起部的截面形状呈梯形状,所述凸起部的侧壁倾斜。
本发明还提供了一种薄膜晶体管的制作方法,其包括:在基板上形成栅极;形成覆盖所述基板和所述栅极的栅极绝缘层;其中,所述栅极绝缘层覆盖所述栅极的部分凸起,以形成凸起部,所述栅极绝缘层覆盖所述基板的部分未凸起,以形成平坦部;在所述凸起部上形成分别位于所述凸起部两端的第一有源层和第二有源层;其中,所述第一有源层和所述第二有源层沿着所述凸起部的侧壁延伸至所述平坦部上;形成与所述第一有源层接触的第一源极,且形成与所述第二有源层接触的第二源极;其中,所述第一源极与所述第二源极彼此连接;形成覆盖所述第一有源层、所述第二有源层、所述第一源极、所述第二源极和所述栅极绝缘层的钝化层;在所述钝化层中形成暴露所述第一有源层的第一过孔,且在所述钝化层中形成暴露所述第二有源层的第二过孔;在所述钝化层上形成分别通过所述第一过孔和所述第二过孔与所述第一有源层和所述第二有源层接触的漏极;其中,所述漏极与所述第一有源层的接触平面与所述第一源极与所述第一有源层的接触平面之间的距离等于所述凸起部的高度,所述漏极与所述第二有源层的接触平面与所述第二源极与所述第二有源层的接触平面之间的距离等于所述凸起部的高度。
进一步地,所述第一源极和所述第二源极的形成方法包括:在延伸至所述平坦部上的所述第一有源层上形成所述第一源极,且在延伸至所述平坦部上的所述第二有源层上形成所述第二源极;所述第一过孔和所述第二过孔的形成方法包括:在所述钝化层中形成暴露出位于所述凸起部上的第一有源层的第一过孔,且在所述钝化层中形成暴露出位于所述凸起部上的第二有源层的第二过孔。
进一步地,所述第一源极和所述第二源极的形成方法包括:在所述凸起部上的所述第一有源层上形成所述第一源极,且在所述凸起部上的所述第二有源层上形成所述第二源极;所述第一过孔和所述第二过孔的形成方法包括:在所述钝化层中形成暴露出延伸至所述平坦部上的第一有源层的第一过孔,且在所述钝化层中形成暴露出延伸至所述平坦部上的第二有源层的第二过孔。
进一步地,所述第一源极和所述第二源极的形成方法包括:在所述平坦部与延伸至所述平坦部上的所述第一有源层之间形成所述第一源极,且在所述平坦部与延伸至所述平坦部上的所述第二有源层之间形成所述第二源极;所述第一过孔和所述第二过孔的形成方法包括:在所述钝化层中形成暴露出位于所述凸起部上的第一有源层的第一过孔,且在所述钝化层中形成暴露出位于所述凸起部上的第二有源层的第二过孔。
本发明的有益效果:本发明通过制作具有垂直结构的薄膜晶体管,从而保证了其中沟道的长度由栅极的侧壁长度所决定;相比现有技术中的薄膜晶体管其中的沟道长度由光刻工艺所控制,本发明的薄膜晶体管中沟道的长度不受光刻工艺的影响,可以实现短沟道,从而得到的短沟道的薄膜晶体管具有更大的宽长比,进而具有更大的开态电流。
附图说明
通过结合附图进行的以下描述,本发明的实施例的上述和其它方面、特点和优点将变得更加清楚,附图中:
图1a至图1g是根据本发明的实施例的薄膜晶体管的制作方法的流程图;
图2是根据本发明的另一实施例的薄膜晶体管的结构示意图;
图3是根据本发明的又一实施例的薄膜晶体管的结构示意图;
图4是根据本发明的又一实施例的薄膜晶体管的结构示意图。
具体实施方式
以下,将参照附图来详细描述本发明的实施例。然而,可以以许多不同的形式来实施本发明,并且本发明不应该被解释为限制于这里阐述的具体实施例。相反,提供这些实施例是为了解释本发明的原理及其实际应用,从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。
在附图中,为了清楚元件,可以夸大元件的形状和尺寸,并且相同的标号将始终被用于表示相同或相似的元件。
将理解的是,尽管在这里可使用术语“第一”、“第二”等来描述各种元件,但是这些元件不应受这些术语的限制。这些术语仅用于将一个元件与另一个元件区分开来。
图1a至图1g示出了根据本发明的实施例的薄膜晶体管的制作流程图。
首先,参照图1a,在基板1上形成栅极2。这里,栅极2的截面形状呈梯形状,但本发明并不限制于此。例如,作为本发明的另一实施方式,如图2所示,栅极2的中间部分凸起,即栅极2的中间部分与其两端具有台阶差,并且栅极2的中间部分的截面形状呈梯形状。
此外,栅极2可以由Al、Mo、Cu、Ag等金属材料制成。
接着,参照图1b,形成覆盖基板1和栅极2的栅极绝缘层3。这里,栅极绝缘层3覆盖栅极2的部分凸起,以形成凸起部31,而栅极绝缘层3直接覆盖基板1的部分未凸起,以形成平坦部32。一般而言,凸起部31的两侧均为平坦部32。
此外,栅极绝缘层3可以由SiNx、SiOx、Al2O3等绝缘材料制成。
接着,参照图1c,在凸起部31上形成分别位于凸起部31两端的第一有源层4a和第二有源层4b,第一有源层4a沿着凸起部31的左侧壁延伸至位于凸起部31左侧的平坦部32上,而第二有源层4b沿着凸起部31的右侧壁延伸至位于凸起部31右侧的平坦部32上。由于栅极2呈梯形状,对应地,凸起部31亦呈梯形状。
进一步地,第一有源层4a和第二有源层4b之间具有间隔,从而暴露出凸起部31。此外,第一有源层4a和第二有源层4b可以由ZnO基材料、In2O3基材料、SnO2基材料或者其他金属氧化物半导体材料制成。
接着,参照图1d,在延伸至位于凸起部31左侧的平坦部32上形成第一源极5a,且在延伸至位于凸起部31右侧的平坦部32上形成第二源极5b,第一源极5a和第二源极5b彼此连接。例如,第一源极5a和第二源极5b一体形成,并整体呈环状或U字型等半包围形状;这样,可通过一根导线与一体的第一源极5a和第二源极5b相连,以保证对第一源极5a和第二源极5b施加电压的稳定性。
作为本发明的另一实施方式,参照图3,在位于凸起部31上的第一有源层4a上形成第一源极5a,且在位于凸起部31上的第二有源层4b上形成第二源极5b,第一源极5a和第二源极5b彼此连接。
作为本发明的另一实施方式,请参照图4,在凸起部31左侧的平坦部32上形成第一源极5a,且在凸起部31右侧的平坦部32上形成第二源极5b。接着,在凸起部31上形成分别位于凸起部31两端的第一有源层4a和第二有源层4b,第一有源层4a沿着凸起部31的左侧壁延伸至第一源极5a上,而第二有源层4b沿着凸起部31的右侧壁延伸至第二源极5b上。
接着,参照图1e,形成覆盖第一有源层4a、第二有源层4b、第一源极5a、第二源极5b和栅极绝缘层3的钝化层6。
此外,钝化层6可以由SiNx、SiOx、Al2O3等绝缘材料制成。
接着,参照图1f,在钝化层6中形成暴露出凸起部31上的第一有源层4a的第一过孔6a,且在钝化层6中形成暴露出凸起部31上的第二有源层4b的第二过孔6b。需要说明的是,图1f所示的第一过孔6a和第二过孔6b的形成位置也适用于图4所示的实施例,具体如图4所示。
作为本发明的另一实施例,参照图3,在钝化层6中形成暴露出延伸至位于凸起部31左侧的平坦部32上的第一有源层4a的第一过孔6a,且在钝化层6中形成暴露出延伸至位于凸起部31右侧的平坦部32上的第二有源层4b的第二过孔6b。
最后,参照图1g,在钝化层6上形成漏极7,漏极7分别通过第一过孔6a和第二过孔6b与凸起部31上的第一有源层4a和第二有源层4b接触。这样,漏极7与凸起部31上的第一有源层4a的接触平面与第一源极5a与平坦部32上的第一有源层4a的接触平面之间的距离等于凸起部31的高度,漏极7与凸起部31上第二有源层4b的接触平面与第二源极5b与平坦部32上的第二有源层4b的接触平面之间的距离等于凸起部31的高度。
需要说明的是,图1所示的漏极7的形成位置也适用于图4所示的实施例,具体如图4所示。
此外,漏极7可以由ITO、IZO等透明金属氧化物半导体导电材料制成。需要说明的是,在本实施例中,利用同种材料同时制成漏极7和像素电极。
作为本发明的另一实施方式,参照图3,在钝化层6上形成漏极7,漏极7分别通过第一过孔6a和第二过孔6b与平坦部32上的第一有源层4a和第二有源层4b接触。
如此,当本实施例的薄膜晶体管在使用时,漏极7与第一源极5a或第二源极5b之间的沟道由凸起部31左侧壁或者右侧壁上的第一有源层4a或第二有源层4b构成,即沟道的长度由凸起部31左侧壁或者右侧壁的长度决定,而凸起部31左侧壁或者右侧壁的长度是由栅极2的左侧壁或者右侧壁的长度(即栅极2的高度)决定,因此沟道的长度由栅极2的左侧壁或者右侧壁的长度决定,从而通过控制栅极2的左侧壁或者右侧壁的长度来控制沟道的长度。这样,控制栅极2的左侧壁或者右侧壁的长度短,就能够使沟道的长度短。
综上所述,根据本发明的实施例,实现了短沟道的薄膜晶体管,从而使制作得到的薄膜晶体管具有更大的宽长比,具有更大的开态电流。
虽然已经参照特定实施例示出并描述了本发明,但是本领域的技术人员将理解:在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下,可在此进行形式和细节上的各种变化。
Claims (2)
1.一种薄膜晶体管,其特征在于,所述薄膜晶体管包括:
基板;
在所述基板上的栅极;所述栅极的中间部分凸起,且所述栅极的中间部分的截面形状呈梯形状;
覆盖所述基板和所述栅极的栅极绝缘层,所述栅极绝缘层覆盖所述栅极的部分凸起,以形成凸起部,所述栅极绝缘层覆盖所述基板的部分未凸起,以形成平坦部;所述凸起部的截面形状呈梯形状,所述凸起部的侧壁倾斜;
在所述凸起部上且分别位于所述凸起部两端的第一有源层和第二有源层,所述第一有源层和所述第二有源层沿着所述凸起部的侧壁延伸至所述平坦部上;
与所述第一有源层接触的第一源极,以及与所述第二有源层接触的第二源极,所述第一源极与所述第二源极彼此连接;
覆盖所述第一有源层、所述第二有源层、所述第一源极、所述第二源极和所述栅极绝缘层的钝化层;
在所述钝化层中且暴露所述第一有源层的第一过孔,以及在所述钝化层中且暴露所述第二有源层的第二过孔;
在所述钝化层上且分别通过所述第一过孔和所述第二过孔与所述第一有源层和所述第二有源层接触的漏极,所述漏极与所述第一有源层的接触平面与所述第一源极与所述第一有源层的接触平面之间的距离等于所述凸起部的高度,所述漏极与所述第二有源层的接触平面与所述第二源极与所述第二有源层的接触平面之间的距离等于所述凸起部的高度;
所述第一源极位于延伸至所述平坦部上的所述第一有源层上,所述第二源极位于延伸至所述平坦部上的所述第二有源层上;所述第一过孔和所述第二过孔分别将位于所述凸起部上的第一有源层和第二有源层暴露;或者所述第一源极位于在所述凸起部上的所述第一有源层上,所述第二源极位于在所述凸起部上的所述第二有源层上;所述第一过孔和所述第二过孔分别将延伸至所述平坦部上的第一有源层和第二有源层暴露。
2.一种薄膜晶体管的制作方法,其特征在于,包括:
在基板上形成栅极;所述栅极的中间部分凸起,且所述栅极的中间部分的截面形状呈梯形状;
形成覆盖所述基板和所述栅极的栅极绝缘层;其中,所述栅极绝缘层覆盖所述栅极的部分凸起,以形成凸起部,所述栅极绝缘层覆盖所述基板的部分未凸起,以形成平坦部;所述凸起部的截面形状呈梯形状,所述凸起部的侧壁倾斜;
在所述凸起部上形成分别位于所述凸起部两端的第一有源层和第二有源层;其中,所述第一有源层和所述第二有源层沿着所述凸起部的侧壁延伸至所述平坦部上;
形成与所述第一有源层接触的第一源极,且形成与所述第二有源层接触的第二源极;其中,所述第一源极与所述第二源极彼此连接;
形成覆盖所述第一有源层、所述第二有源层、所述第一源极、所述第二源极和所述栅极绝缘层的钝化层;
在所述钝化层中形成暴露所述第一有源层的第一过孔,且在所述钝化层中形成暴露所述第二有源层的第二过孔;
在所述钝化层上形成分别通过所述第一过孔和所述第二过孔与所述第一有源层和所述第二有源层接触的漏极;其中,所述漏极与所述第一有源层的接触平面与所述第一源极与所述第一有源层的接触平面之间的距离等于所述凸起部的高度,所述漏极与所述第二有源层的接触平面与所述第二源极与所述第二有源层的接触平面之间的距离等于所述凸起部的高度;
其中,所述第一源极和所述第二源极的形成方法包括:在延伸至所述平坦部上的所述第一有源层上形成所述第一源极,且在延伸至所述平坦部上的所述第二有源层上形成所述第二源极;
所述第一过孔和所述第二过孔的形成方法包括:在所述钝化层中形成暴露出位于所述凸起部上的第一有源层的第一过孔,且在所述钝化层中形成暴露出位于所述凸起部上的第二有源层的第二过孔;
或者所述第一源极和所述第二源极的形成方法包括:在所述凸起部上的所述第一有源层上形成所述第一源极,且在所述凸起部上的所述第二有源层上形成所述第二源极;
所述第一过孔和所述第二过孔的形成方法包括:在所述钝化层中形成暴露出延伸至所述平坦部上的第一有源层的第一过孔,且在所述钝化层中形成暴露出延伸至所述平坦部上的第二有源层的第二过孔。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610571403.0A CN106024637B (zh) | 2016-07-20 | 2016-07-20 | 薄膜晶体管及其制作方法 |
PCT/CN2016/094682 WO2018014385A1 (zh) | 2016-07-20 | 2016-08-11 | 薄膜晶体管及其制作方法 |
US15/128,202 US10312376B2 (en) | 2016-07-20 | 2016-08-11 | Thin film transistor and method for manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610571403.0A CN106024637B (zh) | 2016-07-20 | 2016-07-20 | 薄膜晶体管及其制作方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN106024637A CN106024637A (zh) | 2016-10-12 |
CN106024637B true CN106024637B (zh) | 2018-06-29 |
Family
ID=57116036
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201610571403.0A Expired - Fee Related CN106024637B (zh) | 2016-07-20 | 2016-07-20 | 薄膜晶体管及其制作方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10312376B2 (zh) |
CN (1) | CN106024637B (zh) |
WO (1) | WO2018014385A1 (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106340544B (zh) * | 2016-11-17 | 2020-03-31 | 京东方科技集团股份有限公司 | 一种薄膜晶体管及其制备方法、阵列基板 |
CN110993620A (zh) * | 2019-12-05 | 2020-04-10 | 深圳市华星光电半导体显示技术有限公司 | 阵列基板及其制备方法、显示面板 |
CN115274861A (zh) * | 2022-07-27 | 2022-11-01 | 武汉华星光电技术有限公司 | 半导体器件及电子器件 |
CN115458587A (zh) * | 2022-09-19 | 2022-12-09 | 武汉华星光电技术有限公司 | 显示面板 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6476418B1 (en) * | 1997-06-30 | 2002-11-05 | Nec Corporation | Thin film transistor for liquid crystal display |
JP4951878B2 (ja) * | 2005-05-31 | 2012-06-13 | ソニー株式会社 | 電界効果型トランジスタの製造方法 |
CN103489921A (zh) * | 2013-09-29 | 2014-01-01 | 合肥京东方光电科技有限公司 | 一种薄膜晶体管及其制造方法、阵列基板及显示装置 |
CN103594521A (zh) * | 2012-08-17 | 2014-02-19 | 瀚宇彩晶股份有限公司 | 半导体元件 |
CN104392999A (zh) * | 2014-09-30 | 2015-03-04 | 合肥京东方光电科技有限公司 | 一种阵列基板及其制作方法、显示装置 |
CN105185839A (zh) * | 2015-10-19 | 2015-12-23 | 京东方科技集团股份有限公司 | Tft及其制造方法、驱动电路和显示装置 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070187687A1 (en) * | 2006-02-15 | 2007-08-16 | Meng-Chi Liou | Pixel structure and liquid crystal display panel |
US9698173B2 (en) * | 2014-08-24 | 2017-07-04 | Royole Corporation | Thin film transistor, display, and method for fabricating the same |
TWI578504B (zh) * | 2016-02-05 | 2017-04-11 | 友達光電股份有限公司 | 畫素結構與其製造方法 |
-
2016
- 2016-07-20 CN CN201610571403.0A patent/CN106024637B/zh not_active Expired - Fee Related
- 2016-08-11 US US15/128,202 patent/US10312376B2/en not_active Expired - Fee Related
- 2016-08-11 WO PCT/CN2016/094682 patent/WO2018014385A1/zh active Application Filing
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6476418B1 (en) * | 1997-06-30 | 2002-11-05 | Nec Corporation | Thin film transistor for liquid crystal display |
JP4951878B2 (ja) * | 2005-05-31 | 2012-06-13 | ソニー株式会社 | 電界効果型トランジスタの製造方法 |
CN103594521A (zh) * | 2012-08-17 | 2014-02-19 | 瀚宇彩晶股份有限公司 | 半导体元件 |
CN103489921A (zh) * | 2013-09-29 | 2014-01-01 | 合肥京东方光电科技有限公司 | 一种薄膜晶体管及其制造方法、阵列基板及显示装置 |
CN104392999A (zh) * | 2014-09-30 | 2015-03-04 | 合肥京东方光电科技有限公司 | 一种阵列基板及其制作方法、显示装置 |
CN105185839A (zh) * | 2015-10-19 | 2015-12-23 | 京东方科技集团股份有限公司 | Tft及其制造方法、驱动电路和显示装置 |
Also Published As
Publication number | Publication date |
---|---|
WO2018014385A1 (zh) | 2018-01-25 |
US20180219103A1 (en) | 2018-08-02 |
CN106024637A (zh) | 2016-10-12 |
US10312376B2 (en) | 2019-06-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN106024637B (zh) | 薄膜晶体管及其制作方法 | |
CN103227147B (zh) | Tft-lcd阵列基板及其制造方法、液晶显示器 | |
CN106449763B (zh) | 一种薄膜晶体管及制造方法和显示器面板 | |
CN104009043B (zh) | 像素结构及其制作方法 | |
CN106415801A (zh) | 半导体装置及其制造方法 | |
CN108010850A (zh) | 薄膜晶体管及其制作方法、tft基板 | |
CN110190028A (zh) | 薄膜晶体管阵列基板制备方法 | |
CN110993695A (zh) | Gsd tft器件及其制作方法 | |
WO2019042251A1 (zh) | 薄膜晶体管、薄膜晶体管制备方法和阵列基板 | |
CN105824160B (zh) | 显示面板 | |
US20130168667A1 (en) | Thin film transistor | |
CN107946315A (zh) | 一种阵列基板、显示面板及电子设备 | |
CN109378320B (zh) | 一种阵列基板及其制备方法 | |
CN206619596U (zh) | 阵列基板和显示面板 | |
CN106784015B (zh) | 一种薄膜晶体管及其制作方法、显示基板及显示装置 | |
CN108122759B (zh) | 薄膜晶体管及其制作方法、阵列基板及显示装置 | |
CN104810375A (zh) | 一种阵列基板及其制作方法和一种显示装置 | |
CN104992985B (zh) | 薄膜晶体管及其制造方法、阵列基板 | |
TW201813000A (zh) | 薄膜電晶體基板及其製備方法 | |
TWI648722B (zh) | 畫素結構及其製造方法 | |
CN104377208B (zh) | 显示基板及其制造方法以及显示装置 | |
TWI506797B (zh) | 薄膜晶體管及其製造方法 | |
CN203026512U (zh) | 一种薄膜晶体管、阵列基板及显示装置 | |
CN105977262B (zh) | 一种显示装置、阵列基板及其制造方法 | |
WO2023197363A1 (zh) | 阵列基板及其制作方法、显示面板 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180629 |