CN106024627A - Manufacturing method of SiC-based super-junction IGBT (Insulated Gate Bipolar Transistor) with low off-state loss - Google Patents
Manufacturing method of SiC-based super-junction IGBT (Insulated Gate Bipolar Transistor) with low off-state loss Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
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Abstract
The invention relates to a manufacturing method of a SiC-based super-junction IGBT (Insulated Gate Bipolar Transistor) with low off-state loss. The manufactured SiC-based super-junction IGBT has low off-state loss. The manufacturing method comprises the steps of epitaxially growing a buffer layer of a first conductivity type at a SiC substrate of a second conductivity type; forming a drifting layer containing column regions of the first conductivity type and columns regions of the second conductivity type on the buffer layer, wherein the columns regions of the first conductivity type and the column regions of the second conductivity type are alternatively arranged in the transverse direction; epitaxially forming a body region layer of the second conductivity type on the drifting layer; forming a source region of the first conductivity type on the body region layer through ion implantation or epitaxial growth, and forming a base region of the second conductivity type through ion implantation; etching the SiC substrate so as to form a trench, wherein the trench crosses the body region layer and gets into the column region in depth; forming a gate oxidation layer in the trench; forming a gate electrode in the trench; forming source electrode metal contact in the source region and the base region, forming transmitting electrode metal contact in reverse side of the SiC substrate, and forming ohmic contact; and depositing a passivation layer on the grate electrode and the source electrode metal contact, and through-hole metal interconnection is performed.
Description
Technical field
The present invention relates to the manufacture method of a kind of SiC based high-power device, be specifically related to one and have relatively low
The manufacture method of SiC base superjunction igbt (SJIGBT) device of OFF state loss.
Background technology
Third generation ARTSemiconductor silicon carbide (SiC) compared to the Si of traditional sense have superior physically and electrically
Learn characteristic, such as features such as broad-band gap, high breakdown field strength, high heat conductance.Thus SiC based high-power device
So that the problem of the high dynamic loss that faced of Si power device and quiescent dissipation is relaxed, and
Core status is occupied in high power, high frequency, high temperature field of power electronics.
Although the super node MOSFET constant power device of Si base has developed the several years, but its electricity faced
Lotus imbalance problem limits the application in higher voltage field of the Si base superjunction devices.In recent years, SiC work
The development of technology makes to occur some super-junction structures in SiC base device.In order to meet big electric current,
The power demand of big voltage, a kind of new SiC base superjunction IGBT structure can have thinner epitaxial layer
Thickness, more effective conductance modulation are corresponding.And power IGBT device is in the special applications field of resistive load
Close, such as combustion furnace, space heating element etc., increasingly focus on the loss of its OFF state.Except by reducing material
The method of the minority carrier lifetime of material reduces outside OFF state loss, needs to seek a kind of SiC base superjunction knot
Design in structure parameter, both can apply to high power field, can meet again the demand of low OFF state loss.
Summary of the invention
For the problems referred to above, it is an object of the invention to, it is provided that a kind of Si C base superjunction I GBT device
Manufacture method so that made Si C base superjunction igbt meets the need of low OFF state loss
Ask.
In order to realize foregoing invention purpose, the present invention provides a kind of SiC base superjunction with the loss of low OFF state
The manufacture method of IGBT, it is characterised in that comprise the following steps: at the lining of SiC the second conduction type
The cushion of end Epitaxial growth the first conduction type；The cushion of described first conduction type is formed
Post district in laterally alternately arranging, containing the first conduction type and the drift in the post district of the second conduction type
Layer；Outside on the drift layer in the post district in the post district and the second conduction type that comprise described first conduction type
Prolong the body region layer forming the second conduction type；Conducted electricity described second by ion implanting or epitaxial growth
Form the source region of the first conduction type in the body region layer of type, and then form the second conduction by ion implanting
The base of type；Etching SiC substrate forms groove, and the degree of depth of described groove crosses described second conductive-type
The body region layer of type and enter in the post district of described first conduction type；Form gate oxidation in the trench
Layer；Gate electrode is formed in the described groove formed described gate oxide；At described first conduction type
Source region with on the base of the second conduction type formed source metal contact, conduct electricity at described SiC second
The back side of the substrate of type forms emitter metal contact, and forms it into Ohmic contact；And described
Gate electrode deposits passivation layer, and via metal interconnection on contacting with source metal.
Additionally, it is preferred that formed on the cushion of described first conduction type in laterally alternately arranging, containing
The step having the drift layer in the post district of the first conduction type and the post district of the second conduction type farther includes
Following steps: a) at the beginning of cushion Epitaxial growth first conduction type of described first conduction type
Beginning drift layer；B) deposition mask medium on the initial drift layer of described first conduction type, implements light
Carve graphical, etch described mask medium and form mask layer；And c) utilize acceleration high-energy, repeatedly
Injecting doping and form the drift layer of the second conduction type, the step of described a～c repeats, until finally
The thickness of the post district of described first conduction type formed and the drift layer of described second conduction type reaches
Predetermined thickness.
Additionally, it is preferred that formed on the cushion of described first conduction type in laterally alternately arranging, containing
The step having the drift layer in the post district of the first conduction type and the post district of the second conduction type farther includes
Following steps: in the initial drift of cushion Epitaxial growth first conduction type of described first conduction type
Move layer；Deposition mask medium on the initial drift layer of described first conduction type, implements photolithography patterning,
Etch described mask medium and form mask layer；Etch the initial drift layer of described first conduction type, formed
Groove, etching depth ends in the cushion of described first conduction type；And remove described mask layer,
The drift layer of selective epitaxial growth the second conduction type, the drift layer of the most described second conduction type
Fill described groove.
Additionally, it is preferred that the doping content of the substrate of described SiC the second conduction type is 9 × 1018cm-3～1
×1020cm-3, the doping content of the cushion of described first conduction type is 8 × 1017cm-3～1.2 ×
1018cm-3, the thickness of the cushion of described first conduction type is 1～2 μm, described first conduction type
The doping content in post district be 8 × 1015cm-3～5 × 1016cm-3, thickness is 14～16 μm, described
The doping content in the post district of two conduction types is 7.8 × 1015cm-3～5.1 × 1016cm-3, described first leads
The half cellular width that the electricity post district of type and the post district of described second conduction type are determined is 5～7 μm.
Additionally, it is preferred that the doping content of the substrate of described SiC the second conduction type is 1 × 1018cm-3～3
×1018cm-3, the doping content of the cushion of described first conduction type is 2 × 1017cm-3～3 ×
1017cm-3, the thickness of the cushion of described first conduction type is 1～2 μm, described first conduction type
The doping content in post district be 2 × 1015cm-3～3 × 1015cm-3, thickness is 50～55 μm, described
The doping content in the post district of two conduction types is 1.5 × 1015cm-3～3.5 × 1015cm-3, described first leads
The half cellular width that the electricity post district of type and the post district of described second conduction type are determined is 10～12 μm.
Additionally, it is preferred that the doping content of the substrate of described SiC the second conduction type is 6.5 × 1017
cm-3～8.5 × 1017cm-3, the doping content of the cushion of described first conduction type is 1.8 × 1017
cm-3～2.2 × 1017cm-3, the thickness of the cushion of described first conduction type is 1～2 μm, described
The doping content in the post district of one conduction type is 2 × 1015cm-3～4 × 1015cm-3, thickness is 95～100
μm, the doping content in the post district of described second conduction type is 1.8 × 1015cm-3～4.2 × 1015cm-3,
The half cellular width that the post district of described first conduction type and the post district of described second conduction type are determined
It is 20～24 μm.
Additionally, it is preferred that the post district of described first conduction type is identical with the width in the post district of the second conduction type.
Additionally, it is preferred that the doping content of the source region of described first conduction type is 1.0 × 1020cm-3～1.0 ×
1021cm-3, the degree of depth is 0.2～0.5 μm, the doping content of the base of described second conduction type is 1.0 ×
1019cm-3～1.0 × 1020cm-3, the degree of depth is 0.2～0.5 μm.
Additionally, it is preferred that Ni, 20～40nm that described source metal contact (10) is 60～100nm
The multiple layer metal of the Al of Ti, 60～100nm, described source metal contact (10) covers described first
The source region (6) of conduction type and the base (7) of the second conduction type.
The present invention has following beneficial effect: a, compared to Si base super junction power device, it blocks electricity
Press less by the influence of fluctuations of charge unbalance.So that the Consideration of technical process reduces.b、
Owing to using super-junction structure, Withstand voltage layer thickness required under equal blocking voltage is thinner, and Withstand voltage layer adulterates more
Height, thus there is relatively low on-state loss.C, emitter stage doping content based on optimization, it has
Low OFF state loss, the beneficially lifting of device dynamic performance.D, by optimize anode injection efficiency,
The parameter such as undoped buffer layer and thickness, regulates conductivity modulation effect so that in medium voltate and high pressure field
Epitaxial layer conducting carriers type different.Thus this superjunction IGBT has the pass of different temperature coefficients
State is lost, and the design to protection circuit has reference significance.E, SiC base superjunction IGBT uses groove-shaped
Grid structure, the beneficially optimization of device structure cell, and part doping use epitaxially grown method,
Reduce well region or the ion implantation technology of source region in Conventional power devices, thus reduce the lattice to wafer and damage
Wound, improves device on-state characteristic and yield.
Accompanying drawing explanation
Fig. 1 is the flow process of the manufacture method of SiC base superjunction IGBT with the loss of low OFF state of the present invention
Figure.
Fig. 2～Fig. 9 is the manufacture method of SiC base superjunction IGBT with the loss of low OFF state of the present invention
The schematic diagram of each step.Wherein, Fig. 2 is the schematic diagram making cushion on sic substrates.Fig. 3
It it is the schematic diagram making drift layer on the buffer layer.Fig. 4 .1～Fig. 4 .3 is the two kinds of methods making drift layer
Schematic diagram.Fig. 5 is the schematic diagram making body region layer.Fig. 6～Fig. 7 be in body region layer make source region and
The schematic diagram of base.Fig. 8 is the schematic diagram making groove.Fig. 9 is manufacturing gate oxide layers and gate electrode
Schematic diagram.Figure 10 is to make source metal to contact the schematic diagram contacted with emitter metal.Figure 11 is blunt
Change and the schematic diagram of metal interconnection.
Detailed description of the invention
For further illustrating the technology contents of the present invention, it is described in detail below in conjunction with embodiment and accompanying drawing.
With the first conduction type as N-shaped, the second conduction type is to illustrate that the present invention's has low pass as a example by p-type
The manufacture method of SiC base superjunction IGBT of state loss.
Fig. 1 is the flow process of the manufacture method of SiC base superjunction IGBT with the loss of low OFF state of the present invention
Figure.Below in conjunction with Fig. 2～Fig. 9, each step of the flow chart of Fig. 1 is illustrated.
S1: form n+ type cushion.With reference to Fig. 2, at the p+ type substrate 1 Epitaxial growth n+ of SiC
Type cushion 2.
S2: form drift layer.With reference to Fig. 3, n+ type cushion 2 is produced in laterally alternately arranging
Arrange, containing n-type post district 3 and the drift layer in p-type post district 4.Wherein n-type post district 3 and p-type post district 4
Width identical, net dopant concentration is approximately the same.
S3: form p-type body region layer.With reference to Fig. 5, utilize chemical gaseous phase deposition or other epitaxial growth materials
The method of material is in drift layer Epitaxial growth p-type body region layer 5.
S4: form n+ source region and p+ base.With reference to Fig. 5 and Fig. 6, pass through in p-type body region layer 5
Ion implanting forms n+ source region 6 and p+ base 7.Or, it is also possible to by the epitaxial growth of step S3
Method growth forms n+ source region 6, so can reduce injection number of times.
S5: form groove.With reference to Fig. 8, dry etching SiC substrate, form groove 701.Etched
The degree of depth of groove 701 need to cross and be deep in n-type post district 3 floor bottom p-type body region layer 5.
S6: form gate oxide.With reference to Fig. 9, by SiC substrate dry-oxygen oxidation and anneal, ultimately form
Gate oxide 8.
S7: form gate electrode.With reference to Fig. 9, utilize isotropic deposition technology to fill groove 701, return
Carve implant, and again deposit and return quarter, until planarizing and only retain the gate electrode 9 of trench portions.
S8: form source metal contact and contact with emitter metal.With reference to Figure 10, deposit in open region
Multiple layer metal, peels off and forms source metal contact 10, and source metal contact 10 need to cover n+ source region 6 He
P+ base 7.Form emitter metal contact at the back side of the p+ type substrate of SiC, and form it into ohm
Contact.
S9: deposit passivation layer via metal interconnection.With reference to Figure 11, at source metal contact 10, grid
Deposit passivation layer 12 on electrode 9, Etch Passivation 12 forms metal throuth hole 13, and then at passivation layer
Deposit thick metal layers, and photolithography patterning on 12, be interconnected and form metal pad region 14, complete device
Prepared by part.
The doping content of p+ type substrate 1 of SiC, the doping of n+ type cushion 2 that the present invention designs are dense
Spending can be according to different device from thickness, n-type post district 3, the doping content in p-type post district 4 and thickness
Pressure class requirement and set.It it is below specific embodiment.
First embodiment
Before making SiC base superjunction IGBT with the loss of low OFF state of the present invention, first RCA cleans
The p+ type substrate 1 (with reference to Fig. 2) of SiC.Particularly as follows:
A () cleans with acetone and EtOH Sonicate successively, then use deionized water rinsing.
B the substrate 1 of the SiC after organic ultrasonic is placed in concentrated sulphuric acid and hydrogen peroxide solution and at least boils by ()
10min。
C the substrate 1 boiling concentrated sulphuric acid is boiled more than 10min with a liquid and No. two liquid by () successively respectively,
Dry up stand-by after rinsing well with deionized water again with nitrogen.Number liquid be ammonia, hydrogen peroxide and go from
The mixed liquor of sub-water, No. two liquid are the mixed liquor of hydrochloric acid, hydrogen peroxide and deionized water,
Substrate d () will rinse after is put into Fluohydric acid. and is soaked at least 1min, removes surface oxide layer.
Wherein the doping content of p+ type substrate 1 need to meet specific value, to meet certain injection efficiency,
Substantially 9 × 1018cm-3～1 × 1020cm-3.The p+ type substrate 1 of SiC can be through machining and change
Learn the method for reaction sample is carried out a series of thinning, grind, polish, the technique such as cleaning, make sample
Surface reaches required thickness, flatness.
S1: with reference to Fig. 2, utilizes the method for chemical gaseous phase deposition or other epitaxial grown material SiC's
P+ type substrate 1 Epitaxial growth n+ type cushion 2.Epitaxially grown source is silane or trichlorosilane, second
Alkene etc. or propane etc., the thickness of n+ type cushion 2 is 1～2 μm, the doping content of n+ type cushion 2
It is 8 × 1017cm-3～1.2 × 1018cm-3, doped source is the sources of the gas such as ammonia, and epitaxial growth temperature is
1500 DEG C～1700 DEG C.
S2: with reference to Fig. 3, utilize the method for epitaxial grown material or combine additive method in step S1 institute
Produce in laterally alternately arranging, containing n-type post district 3 and p-type on the n+ type cushion 2 made
The drift layer in post district 4.The doping content in n-type post district 3 is 8 × 1015cm-3～5 × 1016cm-3, thickness
Being 14～16 μm, p-type post district 4 doping content is 7.8 × 1015cm-3～5.1 × 1016cm-3.N-type
The doping content in post district 3 and p-type post district 4 need to meet charge balance, n-type post district 3 and p-type post district 4
There is identical width.The half cellular width that wherein n-type post district 3 and p-type post district 4 are determined can be
5～7 μm.Manufacture method containing n-type post district 3 and the drift layer in p-type post district 4 is exemplified below.
Method one
A (), with reference to Fig. 4 .1, utilizes chemical gaseous phase deposition or the method epitaxial growth of other epitaxial grown material
Initial n-type drift layer 30.Epitaxial growth method is identical with step S1, and the doping of n-type drift layer 30 is dense
Degree is 8 × 1015cm-3～5 × 1016cm-3。
B () with reference to Fig. 4 .2, utilizes physics and the thicker silicon dioxide or many of chemical vapor deposition
The mask medium such as crystal silicon or metal medium, implement photolithography patterning, dry etching mask medium thus formed
Ion implantation mask layer 301.
C (), with reference to Fig. 4 .2, utilizes and accelerates high-energy, such as 1～7MeV, repeatedly inject doping and form p-type
Drift layer 40, utilizes photo-etching mark to control n-type post district 3, the arrangement width in p-type post district 4 formed.
The injection impurity of p-type drift layer 40 can be Al or B, and the impurity concentration injected needs to compensate (a)
The doping of middle n-type drift layer also presents p-type.
D (), with reference to Fig. 3, repeats the process of (a)～(c) until containing n-type post district 3 and the drift in p-type post district 4
Move layer and meet the parameter request of step S2.The ion that activated at injects, activated at method is referring to rear
Method in continuous step, finally produces on n+ type cushion 2 in the most alternately arrangement and contains
There are n-type post district 3 and the drift layer in p-type post district 4.The doping content in n-type post district 3 is 8 × 1015
cm-3～5 × 1016cm-3, thickness is 14～16 μm, and p-type post district 4 doping content is 7.8 × 1015
cm-3～5.1 × 1016cm-3, n-type post district 3, the doping in p-type post district 4 need to meet charge balance, n-type
Post district 3 and p-type post district 4 have identical width, and wherein n-type post district 3 and p-type post district 4 are determined
Half cellular width can be 5～7 μm.
Method two
A (), with reference to Fig. 4 .1, utilizes chemical gaseous phase deposition or the method epitaxial growth of other epitaxial grown material
Initial n-type drift layer 30, epitaxial growth method is identical with step S1, and the doping of n-type drift layer 30 is dense
Degree is 8 × 1015cm-3～5 × 1016cm-3, the thickness of n-type drift layer is 14～16 μm.
B (), with reference to Fig. 4 .3, utilizes the method for chemical gaseous phase deposition or other deposition materials to form thicker etching
The mask layer 401 of SiC, the mask layer 401 of etching SiC can be thick silicon dioxide or many
The laminated medium of crystal silicon and silicon oxide or the metal medium of other Ni, Ti etc., photolithography patterning,
Physically or chemically etching mask layer 401.
C (), with reference to the n-type drift layer of Fig. 4 .3, dry etching SiC, forms deeper groove 402, carve
The erosion degree of depth ends in the n+ type cushion 2 of Fig. 2, and etching width W1 keeps consistent with mesa width W2,
The method of dry etching SiC is referring to the method in subsequent step.
(d) reference Fig. 3, removal etching mask layer 401, selective epitaxial growth p-type drift layer 4,
P-type drift layer 4 just fills the groove 402 formed in (c) of described method two.Doped source used is
The sources of the gas such as trimethyl aluminium, epitaxial growth temperature is 1500 DEG C～1700 DEG C, finally on n+ type cushion 2
Produce in the most alternately arrangement and containing n-type post district 3 and the drift layer in p-type post district 4, n-
The doping content in Xing Zhu district 3 is 8 × 1015cm-3～5 × 1016cm-3, thickness is 14～16 μm, p-
The doping content in Xing Zhu district 4 is 7.8 × 1015cm-3～5.1 × 1016cm-3, n-type post district 3, p-type post district
The doping of 4 need to meet charge balance, n-type post district 3 and p-type post district 4 and have identical width, wherein
The half cellular width that n-type post district 3 and p-type post district 4 are determined can be 5～7 μm.
Method three
Finally can exist with the etching in the ion implanting in combined method one, method two selection type extension
Produce on n+ type cushion 2 in the most alternately arrangement and containing n-type post district 3 and p-type post district 4
Drift layer.The doping content in n-type post district 3 is 8 × 1015cm-3～5 × 1016cm-3, thickness is 14～16
μm, p-type post district 4 is doped to 7.8 × 1015cm-3～5.1 × 1016cm-3, n-type post district 3, p-type post
The doping in district 4 need to meet charge balance, n-type post district 3 and p-type post district 4 and have identical width, its
The half cellular width that middle n-type post district 3 and p-type post district 4 are determined can be 5～7 μm.
It is to be noted that method one to method three is merely illustrative formation containing n-type post district 3 He
The method of the drift layer in p-type post district 4, other similar deformation be included in the scope of protection of the invention it
In.
S3: with reference to Fig. 5, utilizes the method for chemical gaseous phase deposition or other epitaxial grown material in step S2
The drift layer Epitaxial growth p-type body region layer 5 containing n-type post district 3 and p-type post district 4.Used by mix
Miscellaneous source is the sources of the gas such as trimethyl aluminium, and epitaxial growth temperature is 1500 DEG C～1700 DEG C.P-type body region layer 5
Doping content is 1.5 × 1015cm-3～4 × 1017cm-3, the thickness of p-type body region layer 5 is 1.9～2.2 μm.
S4: with reference to Fig. 5, being shifted by litho pattern, formation injection is covered on p-type body region layer 5
Film layer 60.Injection masking layer 60 can be thickness silicon dioxide more than 1.5 μm or polysilicon Jie
Matter, can be about Ti/Au or the Al metal medium of 1 μm, it is also possible to be the group of silicide and metal
Close medium.
With reference to Fig. 5, utilize injection masking layer 60, be 25keV, injectant by Implantation Energy respectively
Amount is 3.4 × 1014cm-2, and Implantation Energy be 55keV, implantation dosage be 5.0 × 1014cm-2, with
And Implantation Energy is 130keV, implantation dosage is 8.9 × 1014cm-2Three nitrogen-atoms inject, formed
Doping is about 1.0 × 1020cm-3～1.0 × 1021cm-3N+ source region 6.The thickness of n+ source region 6 is 0.2～0.5
μm, removes after having injected and injects mask, clean substrate, and the method removing injection mask includes utilizing
The wet etching liquid of HF etc..
As selection, n+ source region 6 can also be deposited or thing by chemical gaseous phase according to the method for step S3
The membrane deposition methods such as physical vapor deposition, epitaxial growth is on the p-type body region layer 5 of step S3.Outward
The source of epitaxial growth is silane or trichlorosilane, ethylene etc. or propane etc., and the degree of depth of n+ source region 6 is 0.2～0.5
μm, the doping content of n+ source region 6 is about 1.0 × 1020cm-3～1.0 × 1021cm-3, doped source used is
The sources of the gas such as ammonia, epitaxial growth temperature is 1500 DEG C～1700 DEG C.
With reference to Fig. 6, it is to be formed by the method for high temperature tension based on n+ source region 6, then by light needle drawing
Shape shifts, and formation injection masking layer 50 on p-type body region layer 5, injection masking layer 50 can be
Thickness silicon dioxide more than 1.5 μm or polycrystalline silicon medium, can be about the Ti/Au of 1 μm
Or Al metal medium, it is also possible to it is the combining medium of silicide and metal.
With reference to Fig. 6, utilize injection masking layer 50, be 28keV, injectant by Implantation Energy respectively
Amount is 2.36 × 1013cm-2, and Implantation Energy be 60keV, implantation dosage be 4.6 × 1013cm-2, with
And Implantation Energy be 100keV, implantation dosage be 6.3 × 1013cm-2Three Al atoms inject, shape
Doping is become to be about 1.0 × 1019cm-3～1.0 × 1020cm-3P+ base 7, the degree of depth of p+ base 7 is
0.2～0.5 μm, injects atom and can also be chosen as B atom.
As selection, if n+ source region 6 is to be formed by epitaxially grown method, then injection masking layer 50 needs
Being positioned on n+ source region 6, implantation dosage need to improve more than an order of magnitude.
With reference to Fig. 7, removing and inject mask, clean surface, use carbon film or AlN film to cover, silane presses down
The methods such as system are at the high temperature of 1600 DEG C, and pressure is under 600～700Torr, about annealing half an hour.Activate
Above-described nitrogen-atoms injects, Al or B atom injects, and removes be covered in table after annealing completes
The carbon film in face, AlN film etc., clean surface.
S5: with reference to Fig. 8, shifted by litho pattern, shape on p-type body region layer 5 and n+ source region 6
Becoming the mask layer 70 of etching SiC, mask layer 70 can be silicon dioxide or the polysilicon of 2 μ m-thick
Metal medium with the laminated medium of silicon oxide or other Ni/Ti etc..
With reference to Fig. 8, by mask layer 70, dry etching SiC substrate, form groove 701.Dry method is carved
Erosion can be other physics such as reactive ion etching (RIE) or inductively coupled plasma (ICP) and
Chemical etching method, etching gas can be SF6、O2、Ar、CF4、CHF3、C4F8、Cl2、HBr
Deng.The degree of depth of the groove 701 etched need to be crossed and is deep into n-type post district 3 bottom p-type body region layer 5
In layer, the width of groove 701 is 2～3 μm.The width for half groove 701 shown in figure (with
The groove of lower same position is not in statement), the profile of groove 701 can be rectangle or have radiused
Bottom corner structure, need to be determined by etching condition.
S6: with reference to Fig. 9, removes mask layer 70, and standard cleaning (RCA) SiC substrate.SiC base
Sheet need to aoxidize formation sacrificial oxide layer about half an hour under the wet oxygen environment of about 1100 DEG C, and passes through
Described sacrificial oxide layer is removed in the ultrasonic rinsing of HF of dilution.The cleaning SiC substrate formed exists
Dry-oxygen oxidation 2～about 3 hours under conditions of 1200 DEG C～1300 DEG C, and 1200 DEG C～the temperature of 1300 DEG C
Anneal 2～3 hours under degree and NO atmospheric condition, ultimately form the gate oxide 8 of 60～100nm thickness.
S7: with reference to Fig. 9, utilize the groove 701 that isotropic deposition technology filling step S5 is formed,
Form gate electrode 9.Implant can be to have DOPOS doped polycrystalline silicon or the silicide of high conductance, utilizes dry method
The means such as etching return the implant deposited quarter, again deposit and return and carve, until planarizing and only retaining
The gate electrode 9 of trench portions.
S8: with reference to Figure 10, photolithography patterning, and remove the oxide layer of open region, profit with the HF of dilution
The membrane deposition method such as deposited by electron beam evaporation or sputtering, successively deposit 60～100nm Ni, 20～40nm Ti,
The multiple layer metal of 60～100nm Al, stripping formation source metal contact 10 or referred to as negative electrode, source electrode gold
Belong to contact 10 and need to cover n+ source region 6 and p+ base 7.As selection, it is permissible that source metal contacts 10
It is other metallic combinations such as AlTi, Ni, TiW.
With reference to Figure 10, the source metal contact 10 in gluing protection front, and remove p with the HF of dilution
The oxide layer at type substrate 1 back side, utilizes the membrane deposition method such as electron beam evaporation or sputtering to deposit overleaf
AlTi or 300～the Ni metal level of 400nm that 20nm is thick as emitter metal contact 11 or are referred to as
Anode.As selection, emitter metal contact 11 can be AlTi, Ni, TiW, AlTi etc. other
Metallic combination.
With reference to Figure 10, at N2Under environment, 900 DEG C～1100 DEG C annealing formed source metal contact 10,
Emitter metal contact 11, the time is 1 minute～3 minutes, and annealing atmosphere can be Ar or H2+N2。
S9: with reference to Figure 11, utilizes physical vapour deposition (PVD) or chemical gaseous phase deposition or other deposition process,
The SiO of more than 1 μm is deposited on source metal contact 10, gate electrode 92/Si3N4As passivation layer
12。
With reference to Figure 11, photolithography patterning, selective etching gas dry etching passivation layer, form metal and lead to
Hole 13.Lithographic method can be reactive ion etching (RIE) or inductively coupled plasma (ICP)
Deng physics and chemical etching method, etching gas can be fluorine-based gas.Utilize electron beam evaporation or spatter
The membrane deposition method such as penetrate on passivation layer 12, deposit the thick metal layers of 1.5 μm, and litho pattern
Change, be interconnected and form metal pad region 14, complete device and prepare.
It is pointed out that step S1～step S9 are only the manufacturing process of device active region, do not contain
The making of lid device periphery terminal area, but do not represent and there is no terminal.As selection, often can design
The knot termination extension (JTE) of rule, the floating structure such as field ring (FLRs), field plate (FP) are as terminal protection
Effect, states the most in the present invention.
Second embodiment
P+ to SiC before making SiC base superjunction IGBT with the loss of low OFF state of the present invention
The cleaning of type substrate 1 is identical with first embodiment, repeats no more here.
Wherein the doping content of p+ type substrate 1 need to meet specific value, to meet certain injection efficiency,
Substantially 1 × 1018cm-3～3 × 1018cm-3, the p+ type substrate 1 of SiC can through machining and
The method of chemical reaction sample is carried out a series of thinning, grind, polish, the technique such as cleaning, make sample
Product surface reaches required thickness, flatness.
S1: with reference to Fig. 2, utilizes the method for chemical gaseous phase deposition or other epitaxial grown material SiC's
P+ type substrate 1 Epitaxial growth n+ type cushion 2.Epitaxially grown source is silane or trichlorosilane, second
Alkene etc. or propane etc., the thickness of n+ type cushion 2 is 1～2 μm, n+ type cushion 2 be doped to 2
×1017cm-3～3 × 1017cm-3, doped source used is the sources of the gas such as ammonia, and wherein epitaxial growth temperature is
1500 DEG C～1700 DEG C.
S2: with reference to Fig. 3, utilize the method for epitaxial grown material or combine additive method in step S1 institute
Produce on the n+ type cushion 2 made in the most alternately arrangement and containing n-type post district 3 and p-
The drift layer in Xing Zhu district 4.The doping content in n-type post district 3 is 2 × 1015cm-3～3 × 1015cm-3, thick
Degree is 50～55 μm, and p-type post district 4 is doped to 1.5 × 1015cm-3～3.5 × 1015cm-3.N-type post district 3
Doping with p-type post district 4 need to meet charge balance, n-type post district 3 and p-type post district 4 and have identical
Width.The half cellular width that wherein n-type post district 3 and p-type post district 4 are determined can be 10～12 μm.
Manufacture method containing n-type post district 3 and the drift layer in p-type post district 4 and the side described in first embodiment
Method is identical.
Step S3～step S9 are identical with the corresponding steps in embodiment 1.
It is pointed out that step S1～step S9 are only the manufacturing process of device active region, do not contain
The making of lid device periphery terminal area, but do not represent and there is no terminal.As selection, often can design
The knot termination extension (JTE) of rule, the floating structure such as field ring (FLRs), field plate (FP) are as terminal protection
Effect, states the most in the present invention.
3rd embodiment
P+ to SiC before making SiC base superjunction IGBT with the loss of low OFF state of the present invention
The cleaning of type substrate 1 is identical with first embodiment, repeats no more here.
Wherein the doping content of p+ type substrate 1 need to meet specific value, to meet certain injection efficiency,
Substantially 6.5 × 1017cm-3～8.5 × 1017cm-3, the p+ type substrate 1 of SiC can be through machining
With the method for chemical reaction sample carried out a series of thinning, grind, polish, the technique such as cleaning, make
Sample surfaces reaches required thickness, flatness.
S1: with reference to Fig. 2, utilizes the method for chemical gaseous phase deposition or other epitaxial grown material SiC's
P+ type substrate 1 Epitaxial growth n+ type cushion 2.Epitaxially grown source is silane or trichlorosilane, second
Alkene etc. or propane etc., the thickness of n+ type cushion 2 is 1～2 μm, being doped to of n+ type cushion 2
1.8×1017cm-3～2.2 × 1017cm-3, doped source used is the sources of the gas such as ammonia, wherein epitaxial growth temperature
It it is 1500 DEG C～1700 DEG C.
S2: with reference to Fig. 3, utilize the method for epitaxial grown material or combine additive method in S1 step institute
Produce on the n+ type cushion 2 made in the most alternately arrangement and containing n-type post district 3 and p-
The drift layer in Xing Zhu district 4.The doping content in n-type post district 3 is 2 × 1015cm-3～4 × 1015cm-3, thick
Degree is 95～100 μm, and p-type post district 4 is doped to 1.8 × 1015cm-3～4.2 × 1015cm-3.N-type post district
3 and the doping in p-type post district 4 need to meet charge balance, n-type post district 3 and p-type post district 4 and have identical
Width.The half cellular width that wherein n-type post district 3 and p-type post district 4 are determined can be 20～24 μ
m.Described in manufacture method containing n-type post district 3 and the drift layer in p-type post district 4 and first embodiment
Method identical.
Step S3～step S9 are identical with the corresponding steps in embodiment 1.
It is pointed out that step S1～step S9 are only the manufacturing process of device active region, do not contain
The making of lid device periphery terminal area, but do not represent and there is no terminal.As selection, often can design
The knot termination extension (JTE) of rule, the floating structure such as field ring (FLRs), field plate (FP) are as terminal protection
Effect, states the most in the present invention.
More than describe the preferred embodiments of the present invention, but the spirit and scope of the present invention are not limited to here
Disclosed particular content.Those skilled in the art can make more reality according to the teachings of the present invention
Executing mode and application, these embodiments and application would be within the spirit and scope of the present invention.The present invention's
Spirit and scope are not limited by specific embodiment, and are defined by the claims.
Claims (9)
1. the manufacture method of SiC base superjunction IGBT with the loss of low OFF state, it is characterised in that
Comprise the following steps:
Cushion (2) at substrate (1) Epitaxial growth first conduction type of SiC the second conduction type；
Cushion (2) at described first conduction type is upper to be formed in laterally alternately arranging, containing the
The post district (3) of one conduction type and the drift layer in the post district (4) of the second conduction type；
Drift in the post district (4) in the post district (3) and the second conduction type comprising described first conduction type
Move the body region layer (5) being epitaxially formed the second conduction type on layer；
Above formed in the body region layer (5) of described second conduction type by ion implanting or epitaxial growth
The source region (6) of the first conduction type, and then the base (7) of the second conduction type is formed by ion implanting；
Etching SiC substrate forms groove (701), and the degree of depth of described groove crosses described second conduction type
Body region layer (5) and enter in the post district (3) of described first conduction type；
Gate oxide (8) is formed in described groove (701)；
Gate electrode (9) is formed in the described groove (701) forming described gate oxide (8)；
Formed on the source region (6) of described first conduction type and the base (7) of the second conduction type
Source metal contact (10), is formed at the back side of the substrate (1) of described SiC the second conduction type and launches
Pole metal contact (11), and form it into Ohmic contact；And
Deposit passivation layer on (10), and through hole gold is contacted with source metal at described gate electrode (9)
Belong to interconnection.
The making of SiC base superjunction IGBT with the loss of low OFF state the most according to claim 1
Method, it is characterised in that
Cushion (2) at described first conduction type is upper to be formed in laterally alternately arranging, containing the
The step of the drift layer in the post district (3) of one conduction type and the post district (4) of the second conduction type is further
Comprise the following steps:
A) cushion (2) Epitaxial growth the first conduction type initial of described first conduction type
Drift layer (30)；
B) at the upper deposition mask medium of initial drift layer (30) of described first conduction type, light is implemented
Carve graphical, etch described mask medium and form mask layer (301)；And
C) utilize acceleration high-energy, repeatedly inject doping and form the drift layer (40) of the second conduction type,
The step of described a～c repeats, until the post district (3) of described first conduction type ultimately formed
Predetermined thickness is reached with the thickness of the drift layer (40) of described second conduction type.
The making of SiC base superjunction IGBT with the loss of low OFF state the most according to claim 1
Method, it is characterised in that
Cushion (2) at described first conduction type is upper to be formed in laterally alternately arranging, containing the
The step of the drift layer in the post district (3) of one conduction type and the post district (4) of the second conduction type is further
Comprise the following steps:
Initial drift at cushion (2) Epitaxial growth first conduction type of described first conduction type
Move layer (30)；
The upper deposition mask medium of initial drift layer (30) at described first conduction type, implements light needle drawing
Shape, etches described mask medium and forms mask layer (401)；
Etching the initial drift layer (30) of described first conduction type, form groove (402), etching is deep
Degree ends in the cushion (2) of described first conduction type；And
Remove described mask layer (401), the drift layer (40) of selective epitaxial growth the second conduction type,
The drift layer (40) of the most described second conduction type fills described groove (402).
4. according to the SiC base superjunction with the loss of low OFF state according to any one of claims 1 to 3
The manufacture method of IGBT, it is characterised in that
The doping content of the substrate (1) of described SiC the second conduction type is 9 × 1018cm-3～1 × 1020
cm-3, the doping content of the cushion (2) of described first conduction type is 8 × 1017cm-3～1.2 × 1018
cm-3, the thickness of the cushion (2) of described first conduction type is 1～2 μm, described first conductive-type
The doping content in Xing Zhu district (3) is 8 × 1015cm-3～5 × 1016cm-3, thickness is 14～16 μm,
The doping content in the post district (4) of described second conduction type is 7.8 × 1015cm-3～5.1 × 1016cm-3,
The post district (3) of described first conduction type and the post district (4) of described second conduction type determined half
Cellular width is 5～7 μm.
5. according to the SiC base superjunction with the loss of low OFF state according to any one of claims 1 to 3
The manufacture method of IGBT, it is characterised in that
The doping content of the substrate (1) of described SiC the second conduction type is 1 × 1018cm-3～3 × 1018
cm-3, the doping content of the cushion (2) of described first conduction type is 2 × 1017cm-3～3 × 1017cm-3,
The thickness of the cushion (2) of described first conduction type is 1～2 μm, the post of described first conduction type
The doping content in district (3) is 2 × 1015cm-3～3 × 1015cm-3, thickness is 50～55 μm, described
The doping content in the post district (4) of two conduction types is 1.5 × 1015cm-3～3.5 × 1015cm-3, described
The half cellular width that the post district (3) of one conduction type and the post district (4) of described second conduction type are determined
Degree is 10～12 μm.
6. according to the SiC base superjunction with the loss of low OFF state according to any one of claims 1 to 3
The manufacture method of IGBT, it is characterised in that
The doping content of the substrate (1) of described SiC the second conduction type is 6.5 × 1017cm-3～8.5 ×
1017cm-3, the doping content of the cushion (2) of described first conduction type is 1.8 × 1017cm-3～2.2
×1017cm-3, the thickness of the cushion (2) of described first conduction type is 1～2 μm, described first
The doping content in the post district (3) of conduction type is 2 × 1015cm-3～4 × 1015cm-3, thickness is 95～100
μm, the doping content in the post district (4) of described second conduction type is 1.8 × 1015cm-3～4.2 × 1015
cm-3, the post district (3) of described first conduction type and the post district (4) of described second conduction type are determined
Half fixed cellular width is 20～24 μm.
7. according to the SiC base superjunction with the loss of low OFF state according to any one of claims 1 to 3
The manufacture method of IGBT, it is characterised in that
The post district (3) of described first conduction type is identical with the width in the post district (4) of the second conduction type.
8. according to the SiC base superjunction with the loss of low OFF state according to any one of claims 1 to 3
The manufacture method of IGBT, it is characterised in that
The doping content of the source region (6) of described first conduction type is 1.0 × 1020cm-3～1.0 × 1021cm-3,
The degree of depth is 0.2～0.5 μm, and the doping content of the base (7) of described second conduction type is 1.0 × 1019
cm-3～1.0 × 1020cm-3, the degree of depth is 0.2～0.5 μm.
9. according to the SiC base superjunction with the loss of low OFF state according to any one of claims 1 to 3
The manufacture method of IGBT, it is characterised in that
Described source metal contact (10) is the Ti of Ni, 20～40nm, 60～100 of 60～100nm
The multiple layer metal of the Al of nm, described source metal contact (10) covers the source of described first conduction type
The base (7) of district (6) and the second conduction type.
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| CN108091567A (en) * | 2017-12-13 | 2018-05-29 | 西安龙腾新能源科技发展有限公司 | Half superjunction FS IEGT structures and its manufacturing method |
| CN115424926A (en) * | 2022-09-26 | 2022-12-02 | 深圳安森德半导体有限公司 | IGBT based on Trench structure and IGBT manufacturing method |
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| WO2006006964A1 (en) * | 2004-06-22 | 2006-01-19 | Cree, Inc. | Silicon carbide devices and fabricating methods therefor |
| CN1790714A (en) * | 2004-12-13 | 2006-06-21 | 株式会社电装 | Semiconductor device and method of manufacturing the same |
| CN101501859A (en) * | 2006-08-17 | 2009-08-05 | 克里公司 | High power insulated gate bipolar transistors |
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| CN108091567A (en) * | 2017-12-13 | 2018-05-29 | 西安龙腾新能源科技发展有限公司 | Half superjunction FS IEGT structures and its manufacturing method |
| CN115424926A (en) * | 2022-09-26 | 2022-12-02 | 深圳安森德半导体有限公司 | IGBT based on Trench structure and IGBT manufacturing method |
| CN115424926B (en) * | 2022-09-26 | 2024-04-26 | 深圳安森德半导体有限公司 | IGBT based on Trench structure and IGBT manufacturing method |
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