CN106024902A - Manufacturing method of SiC-based punch-through trench MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with high blocking property - Google Patents

Manufacturing method of SiC-based punch-through trench MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with high blocking property Download PDF

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CN106024902A
CN106024902A CN201610587157.8A CN201610587157A CN106024902A CN 106024902 A CN106024902 A CN 106024902A CN 201610587157 A CN201610587157 A CN 201610587157A CN 106024902 A CN106024902 A CN 106024902A
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layer
sic
groove
main line
conduction type
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CN106024902B (en
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申占伟
张峰
陈彤
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Global Power Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

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Abstract

The invention relates to a manufacturing method of a SiC-based punch-through trench MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with a high blocking property. The manufactured MOSFET has a high blocking ability. The manufacturing method comprises the steps of epitaxially growing multiple differently doped SiC epitaxial layers on a SiC substrate of a first conductivity type so as to form a SiC substrate, wherein the differently doped SiC epitaxial layers comprise a buffer layer of the first conductivity type, a drifting layer of the first conductivity type, a body region layer of a second conductivity type and a source region layer of the first conductivity type from the bottom up, wherein the thickness of the drifting layer of the first conductivity type satisfies a certain punch-through condition; forming a main trench, wherein two trench corners of the main trench are provided with arc processing, and the bottom part of the trench is not provided with an arc processing structure; etching the SiC substrate to form a terminal structure; etching the SiC substrate to form a base region trench; forming a gate oxidation layer containing such three parts as a thick bottom silicon dioxide layer, a primary gate oxidation layer and a secondary gate oxidation layer in the main trench; forming a gate electrode; forming source electrode metal contact in the base region trench, forming drain electrode metal contact at the reverse side of the SiC substrate, and forming ohmic contact; and depositing a passivation layer, and performing through-hole metal connection.

Description

There is the manufacture method of the SiC base punch groove MOSFET of high blocking characteristics
Technical field
The present invention relates to the manufacture method of a kind of SiC trench FET (MOSFET), tool Body relates to a kind of having effectively protection channel bottom oxide layer and the SiC base punch groove of terminal structure The manufacture method of MOSFET.
Background technology
SiC surmounts the limit of Si base power device with its superior physically and electrically characteristic, and high pressure, High temperature field of power electronics occupies absolute advantages.At high-end switch power supply, hybrid-electric car and motor The field driven, SiC base MOSFET can reduce size, weight and encapsulation difficulty, meet simultaneously High frequency, high power, the demand of lower transition loss, especially for node electricity such as 1200V, 1700V Pressure and the current class of more than 100A, this advantage becomes apparent from.
Vertical device with Dual Implantations type (DMOSFET) and groove-shaped (UMOSFET) is mainly Main.For DMOSFET, introduce JFET region and can effectively protect grid oxygen, and for UMOSFET, More low on-resistance, bigger gully density can be realized in theory, thus realize higher current class. The grid oxygen of UMOSFET is exposed to drift layer, not only makes the grid leak transmission problems such as electric capacity is excessive restriction device Part switch transfer characteristic, makes electric field in oxide excessive, particularly groove under reverse high voltage simultaneously The two dimensional electric field of bottom is assembled and is caused device breakdown in advance, reduces the running voltage of device；Another Problem, the raceway groove of UMOSFET need to realize through dry etching, and the usual roughness of sidewall after etching is very Height, adds high temperature tension and the annealing damage to device, thus UMOSFET channel mobility is low Problem restrict the lifting of its on-state performance.
Summary of the invention
For the problems referred to above, it is an object of the invention to, it is provided that a kind of SiC base punch groove The manufacture method of MOSFET, the first design from structure make up that channel mobility is low and on-state characteristic The problem of difference, secondly designs effective method and protects the gate oxide in groove and terminal part so that Made SiC base punch groove MOSFET has higher blocking ability.
In order to realize foregoing invention purpose, the present invention provides a kind of SiC base break-through with high blocking characteristics The manufacture method of type groove MOSFET, it is characterised in that comprise the following steps: lead at SiC first The SiC epitaxial layer of the substrate Epitaxial growth multilamellar difference doping of electricity type, the SiC of cambium layer stack structure Substrate, is followed successively by from bottom to top: the cushion of the first conduction type, the drift layer of the first conduction type, The body region layer of the second conduction type, the source region layer of the first conduction type, the wherein drift of the first conduction type The thickness of layer meets certain break-through condition；Described SiC substrate is formed main line, described main line Sidewall be 11-20} face be, at two groove angles of main line, there is radiused structure, channel bottom without Radiused structure；Etch described SiC substrate, form terminal structure；Etch described SiC substrate, shape Become to expose the base groove of described second conductivity type body region layer upper surface；Bag is formed in described main line Include thick bottom silicon dioxide layer, primary gate oxide, the gate oxide of secondary gate oxide three part；? Form formation gate electrode in the described main line of described gate oxide；Source is formed in described base groove Pole metal contact, forms drain metal contacts at the back side of the substrate of described SiC the first conduction type, and Form it into Ohmic contact；And on described gate electrode contacts, deposit passivation layer with source metal, and Via metal interconnects.
Additionally, it is preferred that further include steps of, the described SiC substrate comprising described main line is entered Twice high annealing of row, for the first time at 1600 DEG C～1800 DEG C, SiH4Anneal half with in the atmosphere of Ar More than hour, second time is at 1400 DEG C～1600 DEG C, H2Atmosphere in anneal more than half an hour, formed Having radiused structure at two groove angles of described main line, channel bottom is without radiused structure.
Reactive ion etching method is utilized to etch described tap drain additionally, it is preferred that further include steps of Groove is more than 1 minute, is formed and has radiused structure, channel bottom at two groove angles of described main line Without radiused structure, etching gas is Cl2And O2, gas ratio is 7:1, and radio-frequency power is 100W ～250W, pressure is 40mTorr.
Additionally, it is preferred that further include steps of, the described SiC substrate comprising described main line is existed Dry-oxygen oxidation more than 2 hours under conditions of 1200 DEG C～1500 DEG C, wet etching removes removing oxide layer, repeats This process, has radiused structure until being formed at two groove angles of described main line, channel bottom without Radiused structure.
In described main line, fill silicon dioxide additionally, it is preferred that further include steps of and return quarter, Form thick bottom silicon dioxide layer；Dry-oxygen oxidation half an hour under conditions of 1100 DEG C～1300 DEG C, and Anneal 1～3 hour under 1200 DEG C～the temperature of 1300 DEG C and NO atmospheric condition, form primary gate oxide； On described primary gate oxide, at N2And O2Atmosphere in reactive sputtering Al source, and at 900 DEG C At a temperature of annealing obtain AlON, form secondary gate oxide, the thickness of described secondary gate oxide is 30 nm。
In described base groove, 60～100 are deposited successively additionally, it is preferred that further include steps of The multiple layer metal of nm Ni, 20～40nm Ti, 60～100nm Al, peels off the described source metal of formation and connects Touching, the contact of described source metal covers the upper surface of described base groove.
Additionally, it is preferred that the thickness of the drift layer of described first conduction type makes the resistance of described MOSFET Under disconnected state, the electric field break-through in the drift layer of described first conduction type is to described first conduction type In cushion, the thickness of the drift layer of described first conduction type and the drift layer of this first conduction type What doping content was determined is maximally depleted the ratio of slice width degree is 0.7～0.8.
Additionally, it is preferred that described terminal structure includes the terminal trenches of the same degree of depth by a dry etching formation, Terminal trenches near device active region is identical with the width of described main line, away from the end of device active region End groove is wide groove.
Additionally, it is preferred that described terminal structure includes the terminal of the different depth by least three dry etching formation Groove, the terminal trenches near device active region is identical with the width of described main line, active away from device The terminal trenches in district is wide groove, and last terminal trenches away from device active region is led described second Cut-off in the body region layer of electricity type.
The present invention has a following beneficial effect:
A, compared to common MOSFET element, its epitaxial layer, through appropriate design, meets break-through bar Part, and select certain raceway groove crystal face, increase channel mobility, thus be effectively improved the on-state of device Performance so that process costs reduces.
B, groove are only radiused at groove angle, use lamination oxide layer, thick bottom insulation layer, permissible It is effectively improved the reliability of gate oxide.
C, based on the groove-shaped MOSFET of SiC, new terminal structure is proposed, effectively outside protection device Enclose terminal, boost device blocking ability.
D, described SiC base trench MOSFET, well region or the many employings of source region doping are epitaxially grown Method, does not has the shielding implanted layer of conventional groove type MOSFET trench bottom simultaneously, reduces conventional SiC High temperature tension in base power device and annealing process, thus reduce the lattice damage to wafer, carry High device on-state characteristic and reduction cost.
Accompanying drawing explanation
Fig. 1 is the making of the SiC base punch groove MOSFET with high blocking characteristics of the present invention The flow chart of method.
Fig. 2～Fig. 9 is the manufacture method of the SiC base punch groove MOSFET with high blocking characteristics Schematic diagram.Wherein, Fig. 2 is the schematic diagram of SiC substrate of stepped construction；Fig. 3 .1～3.2 is to make The schematic diagram of main line 6；Fig. 4 .1～4.2 is the schematic diagram making terminal structure；Fig. 5 is to make base The schematic diagram of groove；Fig. 6 is the schematic diagram of the gate oxide making three layers；Fig. 7 is to make gate electrode Schematic diagram；Fig. 8 is to make source metal contact and the schematic diagram of drain metal contacts；Fig. 9 be passivation and The schematic diagram of metal interconnection.
Detailed description of the invention
For further illustrating the technology contents of the present invention, it is described in detail below in conjunction with embodiment and accompanying drawing. With the first conduction type as N-shaped, the second conduction type is to illustrate that the present invention's has high resistant as a example by p-type The manufacture method of the SiC base punch groove MOSFET of disconnected characteristic.
Fig. 1 is the making of the SiC base punch groove MOSFET with high blocking characteristics of the present invention The flow chart of method.Below in conjunction with Fig. 2～Fig. 9, each step of the flow chart of Fig. 1 is illustrated.
S1: the SiC substrate of cambium layer stack structure.With reference to Fig. 2, on the n++ type substrate 1 of SiC outside The SiC epitaxial layer of epitaxial growth multilamellar difference doping, the SiC substrate of cambium layer stack structure.Depend on from bottom to top Secondary it is: n+ type cushion 2, n-type drift layer 3, p-type body region layer 4, n+ type source region layer 5.Wherein n- The ratio being maximally depleted slice width degree that the doping of the thickness of type drift layer 3 and n-type drift layer 3 is determined is 0.7～0.8.
S2: form main line.With reference to Fig. 3 .1～Fig. 3 .2, the SiC substrate that step S1 is completed is made Make main line 6, the sidewall of main line 6 be required to be 11-20} face be, main line 6 needs guiding through p-type body region layer The bottom of 4 also enters in n-type drift layer 3, and, have at two groove angles 60,61 of main line 6 Having radiused structure, channel bottom 63 is without radiused structure.
S3: form terminal structure.With reference to Fig. 4 .1～Fig. 4 .2, implement photolithography patterning, deposit dry method Etching forms certain thickness silicon dioxide or polysilicon or the mask layer of metal medium, dry etching SiC Substrate, forms terminal structure 90 or 91.
S4: form base groove.With reference to Fig. 5, implementing photolithography patterning, dry etching forms mask layer 801, continue dry etching SiC substrate and form the base groove 802 of the upper surface exposing p-type body region layer 4.
S5: form the gate oxide of three layers.Reference Fig. 6, standard cleaning (RCA) SiC substrate, Main line 6 utilize the methods such as physically or chemically vapour deposition form thick bottom silicon dioxide layer 501, profit Form primary gate oxide 502 by the method such as high-temperature thermal oxidation and post-oxidation anneal, utilize ald Etc. (ALD) method forms secondary gate oxide 503.Thus, the final grid obtained in main line 6 Oxide layer includes thick bottom silicon dioxide layer 501, primary gate oxide 502, secondary gate oxide 503 Three parts.
S6: form gate electrode.With reference to Fig. 7, fill and formed gate oxide (501,502,503) Main line 6, utilize the methods such as dry etching to return the implant deposited quarter, again deposit and return carve, Until planarizing and only retain the implant of trench portions, thus form gate electrode 10.
S7: form source metal contact and drain metal contacts.With reference to Fig. 8, implement photolithography patterning, And by the oxide layer of the HF removal base groove 802 of dilution, utilize the thin film such as electron beam evaporation or sputtering Deposition process, deposits 70～90nm Ni, 30～50nm Ti, 80～100nm successively at base groove 802 The multiple layer metal of Al, peels off and forms source metal contact 11, and source metal contact 11 need to cover base ditch The upper surface of groove 802.
Gluing protection front source metal contact 11, and remove n++ type substrate 1 back side with the HF of dilution Oxide layer, utilize the membrane deposition method such as electron beam evaporation or sputtering deposited metal overleaf as leakage Pole metal contact 12.
Annealing source metal contact 11 and drain metal contacts 12 under the condition of nitrogen gas of 900 DEG C～1100 DEG C, Form it into Ohmic contact.
S8: deposit passivation layer via metal interconnection.With reference to Fig. 9, connect at gate electrode 10, source metal Touch and on 11, deposit SiO2And Si3N4Passivation layer 13, and through hole formation metal interconnection area 14, complete Prepared by device.
Doping and the thickness of n+ type cushion 2 of the SiC of present invention design, n-drift layer 3 doping with Thickness need to meet break-through design requirement in the bar state, depending on the different pressure class requirements of device System.It it is below specific embodiment.
Embodiment
S1: with reference to Fig. 2, utilizes the method for chemical gaseous phase deposition or other epitaxial grown material SiC's The SiC epitaxial layer of n++ type substrate 1 Epitaxial growth multilamellar difference doping, forms a kind of stepped construction. N++ type substrate 1 thickness is 350 μm～1000 μm of standard or passes through machining and chemical reaction Method sample is carried out a series of thinning, grind, polish, the technique such as cleaning, make sample surfaces reach To required thickness and flatness.Epitaxial growth method concrete on n++ type substrate 1 is as follows:
A (), with reference to Fig. 2, is epitaxially formed n+ type cushion 2 on n++ type substrate 1, epitaxially grown Source is silane or trichlorosilane, ethylene etc. or propane etc., and the thickness of n+ type cushion 2 is 1～2 μm, The doping content of n+ type cushion 2 is 1.0 × 1018cm-3～1.5 × 1018cm-3, doped source used is ammonia Deng source of the gas, epitaxial growth temperature is 1500 DEG C～1700 DEG C.
B (), with reference to Fig. 2, is epitaxially formed n-type drift layer 3 on n+ type cushion 2, epitaxially grown Source is silane or trichlorosilane, ethylene etc. or propane etc., and doped source used is the sources of the gas such as ammonia, and extension is raw Long temperature is 1500 DEG C～1700 DEG C.The thickness of n-type drift layer 3 need to make n-under the blocking state of device Electric field break-through in type drift layer 3 is in n+ type cushion 2, and the thickness of n-type drift layer 3 floats with n-type The ratio being maximally depleted slice width degree that the doping content of shifting layer 3 is determined is 0.7～0.8.As embodiment, The doping content of n-type drift layer 3 is 9.0 × 1015cm-3～1.1 × 1016cm-3, the thickness of n-type drift layer 3 Degree is 10～15 μm.
C (), with reference to Fig. 2, is epitaxially formed p-type body region layer 4, doped source used on n-type drift layer 3 For sources of the gas such as trimethyl aluminiums, epitaxial growth temperature is 1500 DEG C～1700 DEG C.The doping of p-type body region layer 4 Concentration is 1.5 × 1017cm-3～3.5 × 1017cm-3, the thickness of p-type body region layer 4 is 1.2～1.5 μm.
D (), with reference to Fig. 2, is epitaxially formed n+ source region layer 5, epitaxially grown source in p-type body region layer 4 For silane or trichlorosilane, ethylene etc. or propane etc., the thickness of n+ source region layer 5 is 0.2～0.5 μm, n+ The doping content of source region layer 5 is 1.0 × 1019cm-3～1.0 × 1020cm-3, doped source used is the gas such as ammonia Source, epitaxial growth temperature is 1500 DEG C～1700 DEG C.
The preparation of epitaxial material is completed by above step.
S2: with reference to Fig. 3 .1～Fig. 3 .2, makes main line 6 on the epitaxial material that step S1 is completed, The sidewall of main line 6 be required to be 11-20} face be, main line 6 needs guiding through the bottom of p-type body region layer 4 and goes forward side by side Entering in n-type drift layer 3, main line 6 need to meet and has radiused structure at two groove angles 60,61, And channel bottom 63 is without radiused structure.It is exemplified below several concrete implementation.
Implementation one
A (), with reference to Fig. 3 .1, utilizes physics and chemical gaseous phase deposition or the deposit of other membrane deposition methods certain The silicon dioxide of thickness or the mask medium such as polysilicon or metal, implement photolithography patterning and form mask layer 701.Silicon dioxide is as being more than 1.8 μm if mask layer 701, and earth silicon mask layer needs More than 1000 DEG C, O2Under conditions of anneal density.Metal as if mask layer 701 can be Al, Ni etc., thickness is at more than 800nm.Dry etching gas can be C4F8、CHF3、Cl2Deng gas Body.
B (), with reference to Fig. 3 .1, utilizes the mask layer 701 formed in (a), etch hands by physics, chemistry etc. Section, such as reactive ion etching (RIE) or inductively coupled plasma (ICP) etc., dry etching SiC Substrate, etches main line 6.Etching gas can be SF6/O2、NF3/Ar、CF4、CHF3/O2、 C4F8/O2Deng combination of gases.
As an example, SF is used6/O2The etching gas of/HBr, ICP power is 600W～1000W, Substrate bias power is 100W～300W, and temperature is 20 DEG C.Main line 6 needs guiding through bottom p-type body region layer 4 And enter in n-type drift layer 3, and arranging corresponding to the parameter in step S1, the degree of depth of main line 6 can To be 1.75～2.25m, width is 2～4 μm.
C (), with reference to Fig. 3 .2, removes the mask layer 701 in (b), by the SiC substrate warp containing main line 6 Cross the high-temperature annealing process of twice, the i.e. first step at 1600 DEG C～1800 DEG C, SiH4The atmosphere of/Ar is annealed More than half an hour so that at two groove angles 60,61, there is radiused structure, and smooth side wall； Second step at 1400 DEG C～1600 DEG C, H2Atmosphere in anneal more than half an hour, smooth surface again, The groove angle 60,61 with the most radiused structure, channel bottom 63 nothing is formed eventually in main line 6 Radiused structure.
Implementation two
In implementation two, preliminarily form method and (a), (b) two in implementation one of main line 6 Walking identical, except for the difference that the 3rd step in implementation two is:
C (), with reference to Fig. 3 .1～3.2, keeps mask layer 701, utilizes the etching of reactive ion etching (RIE) Means, selective etching gas is Cl2/O2, gas ratio is 7:1, and radio-frequency power is 100W～250W, Pressure is 40mTorr, and dry etching SiC main line 6 is more than 1 minute, finally shape in main line 6 Becoming to have the groove angle 60,61 of the most radiused structure, channel bottom 63 is without radiused structure.
Implementation three
In implementation three, preliminarily form method and (a), (b) two in implementation one of main line 6 Walking identical, except for the difference that the 3rd step in implementation three is:
C (), with reference to Fig. 3 .2, removes mask layer 701, by the SiC substrate containing main line 6 at 1200 DEG C ～dry-oxygen oxidation more than 2 hours under conditions of 1500 DEG C, it is certain thickness that wet etching removal is formed Oxide layer, wet etching liquid can be the solution containing HF.Repeat this process, finally at main line Forming the groove angle 60,61 with the most radiused structure in 6, channel bottom 63 is without radiused knot Structure.
Implementation four
The method that can combine above-mentioned implementation one, two, three, forms implementation four, is finally leading Forming the groove angle 60,61 with the most radiused structure in groove 6, channel bottom 63 is without radiused Structure.
S3: with reference to Fig. 4 .1～Fig. 4 .2, utilize physically or chemically vapour deposition or other membrane deposition methods Deposit certain thickness silicon dioxide or the mask medium such as polysilicon or metal medium, implement photolithography patterning Form mask layer, utilize this mask layer, by physically or chemically waiting etching means, such as reactive ion etching (RIE) or inductively coupled plasma (ICP) etc., dry etching SiC substrate, terminal knot is formed Structure 90 or 91.Described etching gas can be SF6/O2、NF3/Ar、CF4、CHF3/O2、C4F8/ O2Deng combination of gases, the terminal structure 90 or 91 that etching is formed has following several kind:
Kind one:
With reference to Fig. 4 .1, the terminal structure 90 of dry etching, is to be formed the unified degree of depth by a dry etching, Terminal trenches 901～903 near device active region is identical with the width of main line 6, away from device Terminal trenches 904 near active area is wide groove.Arrange corresponding to the parameter in step S1, terminal The degree of depth of groove 901～904 can be 0.5～0.6 μm.
Kind two:
With reference to Fig. 4 .2, the terminal structure 91 of dry etching, is to be formed different depth by least three dry etchings Terminal slot, as a example by scheming three grooves, the wherein terminal trenches near device active region 911～913 is identical with the width of main line 6, selects terminal trenches away from the conduct near device active region 914 can be wide groove, last terminal trenches 914 need to be ended in p-type body region layer 4.
Kind three:
By changing number and spacing or the terminal of kind two of the terminal trenches 901～903 of kind one The number of groove 911～913 and width, form new terminal structure.Described three kinds of terminal structures are only The specific embodiment of the present invention, is not limited to the present invention.
After terminal structure has etched, remove corresponding mask layer.
S4: with reference to Fig. 5, utilizes physics and chemical gaseous phase deposition or the deposit of other membrane deposition methods certain The silicon dioxide of thickness or the mask medium such as polysilicon or metal medium, implement photolithography patterning and form mask Layer 801, utilizes this mask layer 801, by physically or chemically waiting etching means, such as reactive ion etching (RIE) or inductively coupled plasma (ICP) etc., dry etching SiC substrate, formed and expose p The base groove 802 of type body region layer 4 upper surface.Described etching gas can be SF6/O2、NF3/Ar、 CF4、CHF3/O2、C4F8/O2Deng combination of gases, after having etched remove mask layer 801.
S5: form gate oxide.First standard cleaning (RCA) SiC substrate, specific as follows:
Clean with acetone and EtOH Sonicate the most successively, then use deionized water rinsing.
B. the SiC substrate after organic ultrasonic is placed in concentrated sulphuric acid and hydrogen peroxide solution and at least boils 10min.
C. the SiC substrate boiling concentrated sulphuric acid is boiled more than 10min respectively with a liquid and No. two liquid successively, Dry up stand-by after rinsing well with deionized water again with nitrogen.Number liquid be ammonia, hydrogen peroxide and go from The mixed liquor of sub-water, No. two liquid are the mixed liquor of hydrochloric acid, hydrogen peroxide and deionized water.
D. the substrate after rinsing is put into Fluohydric acid. and is soaked at least 1min, removes surface oxide layer.
With reference to Fig. 6, on the SiC substrate after standard cleaning (RCA), by physically or chemically Formed Deng membrane deposition method and the condition such as etch tool and thermal oxide there is low-leakage current, highly reliable The gate oxide of property.Specifically comprise the following steps that
(a) through standard cleaning (RCA) SiC substrate need under the wet oxygen environment of about 1100 DEG C oxygen Change and about half an hour, form sacrificial oxide layer, and removed described sacrifice oxygen by the ultrasonic rinsing of the HF diluted Change layer.
B () utilizes the methods such as physically or chemically vapour deposition to fill in the main line 6 that step S2 is formed Silicon dioxide 500, utilizes physically or chemically etch tool, is filled out in dry or wet etch main line 6 The silicon dioxide 500 filled, until retaining the part of p-type body region layer less than 4, forms thick bottom silicon dioxide Silicon layer 501.
(c) on the SiC substrate containing thick bottom silicon dioxide layer 501, at the bar of 1100 DEG C-1300 DEG C Under part about dry-oxygen oxidation half an hour, and move back at the temperature of 1200 DEG C-1300 DEG C and NO atmospheric condition Fire 1-3 hour, forms primary gate oxide 502.Described annealing atmosphere is not only NO, it is also possible to It is POCl3, H2, N2O, P2O5, Sb+NO etc..
(d) on primary gate oxide 502, at N2/O2Atmosphere in reactive sputtering Al source, and 900 In DEG C, annealing obtains AlON, forms secondary gate oxide 503.Secondary gate oxide 503 thickness is at 30nm Left and right, secondary gate oxide 503 can also be the Al deposited by the method for ald2O3Thin film.
The final gate oxide obtained include thick bottom silicon dioxide layer 501, primary gate oxide 502, Secondary gate oxide 503 3 part, can effectively protect the reliability of gate oxide under blocking state, carry Rise the blocking ability of groove MOSFET.
S6: with reference to Fig. 7, utilize isotropic deposition technology fill formed gate oxide (501,502, 503) main line 6, implant can be to have DOPOS doped polycrystalline silicon or the silicide of high conductance.Utilize dry The methods such as method etching return the implant deposited quarter, again deposit and return and carve, until planarizing and only protecting Stay the implant of trench portions, thus form gate electrode 10.
S7: with reference to Fig. 8, implements photolithography patterning, and removes base groove 802 with the HF of dilution Oxide layer, utilizes the membrane deposition method such as electron beam evaporation or sputtering, deposits successively at base groove 802 The multiple layer metal of 60～100nm Ni, 20～40nm Ti, 60～100nm Al, peels off and forms source metal Contact 11, source metal contact 11 need to cover the upper surface of base groove 802.As selection, source electrode Metal contact 11 can be other metallic combinations such as AlTi, Ni, TiW.
With reference to Fig. 8, the source metal contact 11 in gluing protection front, and remove n++ with the HF of dilution The oxide layer at type substrate 1 back side, utilizes the membrane deposition method such as electron beam evaporation or sputtering to deposit overleaf Ni metal level thick for AlTi, 300～400nm thick for 20nm is as drain metal contacts 12.As choosing Selecting, drain metal contacts 12 can be other metallic combinations such as AlTi, Ni, TiW, AlTi.
With reference to Fig. 8, at N2Under environment, 900 DEG C～1100 DEG C annealing formed source metal contact 11, Drain metal contacts 12, the time is 1～3 minute, and annealing atmosphere can also be Ar or H2+N2。
S8: with reference to Fig. 9, utilize other deposition process such as physical vapour deposition (PVD) or chemical gaseous phase deposition, SiO2 and Si3N4 more than source metal contact 11,1 μm deposited above of gate electrode 10 is as blunt Change layer 13.Implement photolithography patterning, selective etching gas dry etching passivation layer 13, form metal and lead to Hole.Lithographic method can be reactive ion etching (RIE) or inductively coupled plasma (ICP) etc. Other physics and chemical etching method, etching gas can be fluorine-based gas.Utilize electron beam evaporation or The membrane deposition methods such as sputtering deposit the thick metal layers of 1.5 μm, and litho pattern on passivation layer 13 Change, be interconnected and form metal pad region 14, this completes the preparation of device.
More than describe the preferred embodiments of the present invention, but the spirit and scope of the present invention are not limited to here Disclosed particular content.Those skilled in the art can make more reality according to the teachings of the present invention Executing mode and application, these embodiments and application would be within the spirit and scope of the present invention.The present invention's Spirit and scope are not limited by specific embodiment, and are defined by the claims.

Claims (9)

1. there is a manufacture method for the SiC base punch groove MOSFET of high blocking characteristics, its It is characterised by, comprises the following steps:
In the SiC extension that substrate (1) the Epitaxial growth multilamellar difference of SiC the first conduction type is adulterated Layer, the SiC substrate of cambium layer stack structure, it is followed successively by from bottom to top: the cushion (2) of the first conduction type, The drift layer (3) of the first conduction type, the body region layer (4) of the second conduction type, the first conduction type Source region layer (5), wherein the thickness of the drift layer (3) of the first conduction type meets certain break-through condition；
Forming main line (6) on described SiC substrate, the sidewall of described main line (6) is { 11-20} Face is, two groove angles (60, the 61) place of described main line has radiused structure, channel bottom (63) Without radiused structure；
Etch described SiC substrate, form terminal structure (90,91)；
Etch described SiC substrate, formed and expose described second conductivity type body region layer (4) upper surface Base groove (802)；
Described main line (6) is formed and includes thick bottom silicon dioxide layer (501), primary gate oxidation Layer (502), the gate oxide of secondary gate oxide (503) three part；
Gate electrode (10) is formed in the described main line (6) forming described gate oxide；
Form source metal contact (11) in described base groove (802), lead at described SiC first The back side of the substrate (1) of electricity type forms drain metal contacts (12), and forms it into Ohmic contact； And
Deposit passivation layer on (11), and through hole gold is contacted with source metal at described gate electrode (10) Belong to interconnection.
The SiC base punch groove MOSFET with high blocking characteristics the most according to claim 1 Manufacture method, it is characterised in that further include steps of
The described SiC substrate comprising described main line (6) is carried out twice high annealing, exists for the first time 1600 DEG C～1800 DEG C, SiH4More than half an hour of annealing in the atmosphere of Ar, second time exists 1400 DEG C～1600 DEG C, H2Atmosphere in anneal more than half an hour, form the two of described main line (6) Individual groove angle (60,61) place has radiused structure, and channel bottom (63) is without radiused structure.
The SiC base punch groove MOSFET with high blocking characteristics the most according to claim 1 Manufacture method, it is characterised in that further include steps of
Utilize reactive ion etching method to etch described main line (6) to be more than 1 minute, form described master Two groove angles (60, the 61) place of groove (6) has radiused structure, channel bottom (63) nothing Radiused structure, etching gas is Cl2And O2, gas ratio is 7:1, and radio-frequency power is 100W ～250W, pressure is 40mTorr.
The SiC base punch groove MOSFET with high blocking characteristics the most according to claim 1 Manufacture method, it is characterised in that further include steps of
The described SiC substrate that will comprise described main line (6) is dry under conditions of 1200 DEG C～1500 DEG C Oxygen aoxidizes more than 2 hours, and wet etching removes removing oxide layer, repeats this process, until forming described tap drain Two groove angles (60, the 61) place of groove (6) has radiused structure, and channel bottom (63) is without circle The structure of arcing.
The SiC base punch groove MOSFET with high blocking characteristics the most according to claim 1 Manufacture method, it is characterised in that further include steps of
In described main line (6), fill silicon dioxide and return quarter, forming thick bottom silicon dioxide layer (501)；
Dry-oxygen oxidation half an hour under conditions of 1100 DEG C～1300 DEG C, and 1200 DEG C～the temperature of 1300 DEG C Anneal 1～3 hour under degree and NO atmospheric condition, form primary gate oxide (502)；
On described primary gate oxide (502), at N2And O2Atmosphere in reactive sputtering Al source, And annealing obtains AlON at a temperature of 900 DEG C, form secondary gate oxide (503), described secondary The thickness of gate oxide (503) is 30nm.
The SiC base punch groove MOSFET with high blocking characteristics the most according to claim 1 Manufacture method, it is characterised in that further include steps of
Described base groove (802) deposits successively 60～100nm Ni, 20～40nm Ti, 60～100 The multiple layer metal of nm Al, peels off and forms described source metal contact (11), described source metal contact (11) Cover the upper surface of described base groove (802).
7. according to the SiC base punch with high blocking characteristics according to any one of claim 1～6 The manufacture method of groove MOSFET, it is characterised in that
The thickness of the drift layer (3) of described first conduction type makes the blocking state of described MOSFET Under described first conduction type drift layer (3) in slow to described first conduction type of electric field break-through Rush in layer (2), the thickness of the drift layer (3) of described first conduction type and this first conduction type The ratio being maximally depleted slice width degree that the doping content of drift layer (3) is determined is 0.7～0.8.
8. according to the SiC base punch with high blocking characteristics according to any one of claim 1～6 The manufacture method of groove MOSFET, it is characterised in that
Described terminal structure (90) includes the terminal trenches of the same degree of depth by a dry etching formation (901～904), the terminal trenches (901～903) near device active region and described main line (6) Width is identical, and the terminal trenches (904) away from device active region is wide groove.
9. according to the SiC base punch with high blocking characteristics according to any one of claim 1～6 The manufacture method of groove MOSFET, it is characterised in that
Described terminal structure (91) includes the terminal trenches of the different depth by least three dry etching formation (911～914), the terminal trenches (911～913) near device active region and described main line (6) Width is identical, and the terminal trenches (914) away from device active region is wide groove, away from device active region Last terminal trenches end in the body region layer (4) of described second conduction type.
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