CN105990298A - Chip packaging structure and preparation method thereof - Google Patents
Chip packaging structure and preparation method thereof Download PDFInfo
- Publication number
- CN105990298A CN105990298A CN201510064082.0A CN201510064082A CN105990298A CN 105990298 A CN105990298 A CN 105990298A CN 201510064082 A CN201510064082 A CN 201510064082A CN 105990298 A CN105990298 A CN 105990298A
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- CN
- China
- Prior art keywords
- chip
- packaging structure
- substrate
- spill substrate
- spill
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention relates to a chip packaging structure and a preparation method thereof, and belongs to the technical field of semiconductors. The chip packaging structure comprises a lead frame body, the lead frame body comprises a recessed substrate and pins, the recessed substrate is used to bear a chip, the pins are placed in the periphery of the recessed substrate, and each pin is connected to an input-output welding point of the chip via a metal electrode. The recessed substrate of the chip is fixed, an insulating layer is deposited on the chip and the upper surface of the substrate, the metal electrodes are prepared to connect the substrate with the chip, and thus, the chip is packaged; and the metal electrodes are used to replace metal leads, problems that the metal leads are shorted or collapse can be overcome, the yield rate of packaging is improved, and the chip packaging cost is reduced.
Description
Technical field
The present invention relates to electronic technology field, be specifically related to a kind of chip-packaging structure and preparation method thereof.
Background technology
Lead frame type package structure is a kind of principal mode of integrated antenna package, the lead-in wire of prior art
Frame-type encapsulating structure is as it is shown in figure 1, include packaging body 1, with the pin 4 of external connection, packaging body 1
Inside including pedestal 2, chip 3, chip 3 is adhered on pedestal 2, with pin 4 by metal lead wire 5
Connect；Wherein, in metal lead wire 5 passes through input and output pad and the pin of metal wire interconnection die 3
Lower limb, but this lead key closing process easily exists soldered ball defect, gold thread deforms, the problem such as subside, shadow
Ring encapsulation qualification rate.
Summary of the invention
It is an object of the invention to, it is provided that a kind of chip-packaging structure, solve above technical problem；
The present invention also aims to, it is provided that the preparation method of a kind of chip-packaging structure, solve above skill
Art problem.
Technical problem solved by the invention can realize by the following technical solutions:
A kind of chip-packaging structure, wherein, including,
One lead frame support body, described lead frame support body includes:
Spill substrate, is used for carrying chip；
A plurality of pins, are positioned at the periphery of described spill substrate, and each described pin passes through a gold medal
Belong to electrode to be connected with the input and output pad of chip.
The present invention, by designing the spill substrate of fixed chip, uses metal electrode to replace metal lead wire, real
The input and output pad of existing chip and the connection of each pin, it is to avoid metal lead wire short circuit, subside
Problem.
The chip-packaging structure of the present invention, each pin includes first and second, described first with
In being connected with external print circuit board, described second connects the defeated of described chip by described metal electrode
Enter to export pad.
The chip-packaging structure of the present invention, the cup depth of described spill substrate is more than the thickness of described chip.
The chip-packaging structure of the present invention, is provided with bonding thin between described chip with described spill substrate bottom
Film layer, the thickness of described adhering film layer and the thickness sum of described chip are equal to the recessed of described spill substrate
Fall into the degree of depth.
The chip-packaging structure of the present invention, the bottom of described spill substrate is along the lower surface of described encapsulating structure
Arrange.
The present invention also provides for the preparation method of a kind of chip-packaging structure, for preparing above-mentioned chip package
Structure, comprises the following steps:
Step 1, forms a lead frame support body with spill substrate, described lead-in wire by semiconductor technology
Distributive plural pin on frame body；
Step 2, is fixed on chip in described spill substrate by a predetermined technique, the limit of described chip
Gap is formed between the sidewall of edge and described spill substrate；
Step 3, depositing insulating layer in described gap；
Step 4, the upper surface in described chip and described spill substrate deposits multiple metal electrodes, each
Metal electrode is for connecting pin described in the input and output pad and of described chip；
Step 5, uses encapsulating material encapsulation.
The method for packing of the semiconductor device of the present invention, chip described in step 2 by bonding or welding
Mode is connected on described spill substrate.
Beneficial effect: owing to using above technical scheme, the present invention is by designing the spill base of fixed chip
Sheet, utilizes insulating barrier to fill substrate and chip gap, at chip and substrate upper surface depositing insulating layer and make
Make metal electrode to connect substrate and chip, it is achieved chip package.Metal electrode is used to replace metal lead wire,
Avoid the problems such as metal lead wire is short-circuit, subside, improve encapsulation yield, advantageously reduce chip package
Cost.
Accompanying drawing explanation
Fig. 1 is the lead-frame packages structural representation of prior art；
Fig. 2 is the encapsulating structure schematic diagram of the present invention；
Fig. 3 is the encapsulation schematic flow sheet of the present invention；
Fig. 4 is the encapsulating structure top view of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out
Clearly and completely describe, it is clear that described embodiment is only a part of embodiment of the present invention, and
It is not all, of embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art are not making
The every other embodiment obtained on the premise of going out creative work, broadly falls into the scope of protection of the invention.
It should be noted that in the case of not conflicting, the embodiment in the present invention and the spy in embodiment
Levy and can be mutually combined.
The invention will be further described with specific embodiment below in conjunction with the accompanying drawings, but not as the present invention's
Limit.
With reference to Fig. 2, a kind of chip-packaging structure, wherein, including,
One lead frame support body, lead frame support body includes:
Spill substrate 11a, is used for carrying chip 2a；
A plurality of pin 4a, are positioned at the periphery of spill substrate 11a, and each pin 4a passes through one
The input and output pad of metal electrode 5a and chip 2a is connected.
The present invention, by designing the spill substrate of fixed chip, uses metal electrode to replace metal lead wire,
Realize the input and output pad of chip and the connection of each pin, it is to avoid metal lead wire short circuit, collapse
Fall into etc. problem.
The chip-packaging structure of the present invention, each pin includes first and second, and first with outer
Portion's printed circuit board connects, second input and output welding being connected chip 2a by metal electrode 5a
Point.
The chip-packaging structure of the present invention, the cup depth of the spill substrate 11a thickness more than chip 2a.
The chip-packaging structure of the present invention, bottom chip 2a and spill substrate 11a between be provided with bonding thin
Film layer 6a, the thickness of adhering film layer 6a and the thickness sum of chip 2a are equal to spill substrate 11a's
The degree of depth.
The chip-packaging structure of the present invention, the bottom of spill substrate 11a is along the surface configuration of encapsulating structure.
Chip and outside area of dissipation can be increased, be conducive to promoting the hot property of chip-packaging structure.
The chip-packaging structure of the present invention, after forming metal electrode 5a, is encapsulated by encapsulating material 7a
To obtain the chip-packaging structure of the present invention.
The present invention also provides for the method for packing of a kind of chip-packaging structure, for preparing above-mentioned chip envelope
Assembling structure, comprises the following steps:
Step 1, forms a lead frame support body with spill substrate, lead frame by semiconductor technology
Distributive plural pin on body；
Step 2, is fixed on chip in spill substrate by a predetermined technique, the edge of chip and spill
Gap is formed between the sidewall of substrate；
Step 3, depositing insulating layer in gap；
Step 4, the upper surface in chip and spill substrate deposits multiple metal electrodes, each metal electrode
For connecting input and output pad and a pin of chip；
Step 5, uses encapsulating material encapsulation.
Concrete steps, with reference to shown in Fig. 3, by die bonding in spill substrate, can use silver slurry to exist
Under room temperature chip is bonding with spill substrate, reheat cured, or Au-Si gold alloy solder connection etc.
Other welding methods；In step s1, the height of the adhering film layer between chip and spill substrate should make
After die bonding, upper surface flushes with the sidewall of spill substrate；
Step s2, depositing insulating layer in the gap between the sidewall of chip and spill substrate；
Step s3, deposits the first metal electricity between the first setting position and the corresponding pin of chip
Pole；
Step s4, deposits the second metal electricity between the second setting position and the corresponding pin of chip
Pole；
According to the quantity of pin, Multiple depositions step can be comprised, it is achieved the input and output pad of chip with
Corresponding pin, does not repeats at this.
Step s5, depositing insulating layer between metal electrode.And after step s5, use encapsulation material
Material encapsulation.
The present invention uses metal electrode to replace metal lead wire, it is to avoid metal lead wire short circuit, the problem such as subside,
Improve encapsulation yield, advantageously reduce chip package cost.
The foregoing is only preferred embodiment of the present invention, not thereby limit embodiments of the present invention and
Protection domain, to those skilled in the art, it should can appreciate that all utilization description of the invention
And the equivalent done by diagramatic content and the scheme obtained by obvious change, all should comprise
Within the scope of the present invention.
Claims (7)
1. a chip-packaging structure, it is characterised in that include,
One lead frame support body, described lead frame support body includes:
Spill substrate, is used for carrying chip；
A plurality of pins, are positioned at the periphery of described spill substrate, and each described pin passes through a gold medal
Belong to electrode to be connected with the input and output pad of chip.
Chip-packaging structure the most according to claim 1, it is characterised in that each pin includes
One and second, described first is used for being connected with external print circuit board, and described second is passed through institute
State metal electrode and connect the input and output pad of described chip.
Chip-packaging structure the most according to claim 1, it is characterised in that described spill substrate
Cup depth is more than the thickness of described chip.
Chip-packaging structure the most according to claim 1, it is characterised in that described chip is with described
Adhering film layer, the thickness of described adhering film layer and the thickness of described chip it is provided with between spill substrate bottom
Degree sum is equal to the cup depth of described spill substrate.
Chip-packaging structure the most according to claim 1, it is characterised in that described spill substrate
Bottom is arranged along the lower surface of described encapsulating structure.
6. the preparation method of a chip-packaging structure, it is characterised in that be used for preparing claim 1 to
Chip-packaging structure described in 5 any one, comprises the following steps:
Step 1, forms a lead frame support body with spill substrate, described lead-in wire by semiconductor technology
Distributive plural pin on frame body；
Step 2, is fixed on chip in described spill substrate by a predetermined technique, the limit of described chip
Gap is formed between the sidewall of edge and described spill substrate；
Step 3, depositing insulating layer in described gap；
Step 4, the upper surface in described chip and described spill substrate deposits multiple metal electrodes, each
Metal electrode is for connecting pin described in the input and output pad and of described chip；
Step 5, uses encapsulating material encapsulation.
The preparation method of chip-packaging structure the most according to claim 6, it is characterised in that step
Chip described in 2 by bonding or welding by the way of be connected on described spill substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510064082.0A CN105990298A (en) | 2015-02-06 | 2015-02-06 | Chip packaging structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510064082.0A CN105990298A (en) | 2015-02-06 | 2015-02-06 | Chip packaging structure and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105990298A true CN105990298A (en) | 2016-10-05 |
Family
ID=57036143
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510064082.0A Pending CN105990298A (en) | 2015-02-06 | 2015-02-06 | Chip packaging structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105990298A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106898944A (en) * | 2017-03-01 | 2017-06-27 | 苏州达沃特光电科技有限公司 | The single capsulation structure for semiconductor laser and method of a kind of high efficiency and heat radiation |
| CN110211887A (en) * | 2019-06-11 | 2019-09-06 | 山东海声尼克微电子有限公司 | A kind of lock material hole copper sheet welding procedure for large-current electric source module wire bonding |
| CN112103210A (en) * | 2020-08-13 | 2020-12-18 | 张国华 | Chip bonding process equipment for semiconductor chip packaging |
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| JP2005050911A (en) * | 2003-07-30 | 2005-02-24 | Seiko Epson Corp | Semiconductor device |
| JP2005251910A (en) * | 2004-03-03 | 2005-09-15 | Seiko Epson Corp | Circuit board, its manufacturing method, electrooptical device, and electronic apparatus |
| CN202025735U (en) * | 2011-04-27 | 2011-11-02 | 江西省一元数码科技有限公司 | Novel lead framework structure |
| CN102290522A (en) * | 2011-09-16 | 2011-12-21 | 陆学中 | Wireless LED (Light Emitting Diode) packaging structure and manufacturing method thereof |
| CN102629599A (en) * | 2012-04-06 | 2012-08-08 | 天水华天科技股份有限公司 | Quad flat no lead package and production method thereof |
| CN103959450A (en) * | 2011-11-25 | 2014-07-30 | 富士机械制造株式会社 | Semiconductor package and method for manufacturing same |
-
2015
- 2015-02-06 CN CN201510064082.0A patent/CN105990298A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005050911A (en) * | 2003-07-30 | 2005-02-24 | Seiko Epson Corp | Semiconductor device |
| JP2005251910A (en) * | 2004-03-03 | 2005-09-15 | Seiko Epson Corp | Circuit board, its manufacturing method, electrooptical device, and electronic apparatus |
| CN202025735U (en) * | 2011-04-27 | 2011-11-02 | 江西省一元数码科技有限公司 | Novel lead framework structure |
| CN102290522A (en) * | 2011-09-16 | 2011-12-21 | 陆学中 | Wireless LED (Light Emitting Diode) packaging structure and manufacturing method thereof |
| CN103959450A (en) * | 2011-11-25 | 2014-07-30 | 富士机械制造株式会社 | Semiconductor package and method for manufacturing same |
| CN102629599A (en) * | 2012-04-06 | 2012-08-08 | 天水华天科技股份有限公司 | Quad flat no lead package and production method thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106898944A (en) * | 2017-03-01 | 2017-06-27 | 苏州达沃特光电科技有限公司 | The single capsulation structure for semiconductor laser and method of a kind of high efficiency and heat radiation |
| CN106898944B (en) * | 2017-03-01 | 2019-05-31 | 苏州达沃特光电科技有限公司 | A kind of the single capsulation structure for semiconductor laser and method of high efficiency and heat radiation |
| CN110211887A (en) * | 2019-06-11 | 2019-09-06 | 山东海声尼克微电子有限公司 | A kind of lock material hole copper sheet welding procedure for large-current electric source module wire bonding |
| CN112103210A (en) * | 2020-08-13 | 2020-12-18 | 张国华 | Chip bonding process equipment for semiconductor chip packaging |
| CN112103210B (en) * | 2020-08-13 | 2023-03-31 | 上饶市广丰时代科技有限公司 | Chip bonding process equipment for semiconductor chip packaging |
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| PB01 | Publication | ||
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20161005 |