CN105989798A - Bidirectional scanning signal emission circuit - Google Patents
Bidirectional scanning signal emission circuit Download PDFInfo
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- CN105989798A CN105989798A CN201510067624.XA CN201510067624A CN105989798A CN 105989798 A CN105989798 A CN 105989798A CN 201510067624 A CN201510067624 A CN 201510067624A CN 105989798 A CN105989798 A CN 105989798A
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Abstract
The invention discloses a bidirectional scanning signal emission circuit. The circuit comprises a first control module, a second control module and an output module; the first control module includes a pair of transistors, and first and second control signals whose logic states are opposite to each other are used to control ON-OFF of the transistors respectively so that a forward or backward scanning signal is transmitted to a first node between the transistors; the second control module includes a pair of control tubes in serial connection, a group of clock signals is transmitted to the control ends of the control tubes, and the ON-OFF states of the control tubes are determined, and one of the control tubes is connected to the first node; the output module is connected with the second control module and includes first and second output tubes and the output end, ON-OFF states the first and second output tubes are selected according to the ON-OFF states of the control tubes, and during ON-OFF switching of the first and second output tubes, a first or second reference voltage is output via the output end. Thus, competitiveness of the circuit is improved.
Description
Technical field
The present invention relates to circuit design field, be specifically related to a kind of bilateral scanning and launch signal circuit.
Background technology
Along with people are close to harsh pursuit to mobile phone screen, computer screen, AMOLED (Active Matrix/Organic Light Emitting Diode, active-matrix organic light emitting diode (AMOLED) panel) compare traditional liquid crystal panel, AMOLED has the plurality of advantages such as response speed is very fast, contrast is higher, visual angle is wider, gradually being favored by consumer, Ge great Display Technique enterprise all attaches great importance to this new Display Technique.
AMOLED is simple scanning pattern at present, and in order to improve the competitiveness of AMOLED, it is also desirable to use positive and negative scan pattern, bilateral scanning needs to design bilateral scanning circuit.
Summary of the invention
The present invention devises a kind of scanning that can be applicable to AMOLED and launches signal circuit, can realize the bilateral scanning of AMOLED circuit, improve product competitiveness.
The technical solution used in the present invention is:
A kind of bilateral scanning transmitting signal circuit, wherein, including:
First control module, there is pair of transistor, the opening and closing of the pair of transistor are controlled respectively, with at the primary nodal point that is transported between the pair of transistor connect by one of them one connected of the pair of transistor scanning signal forward or backwards by contrary the first control signal of two logical states, the second control signal；And
Second control module, there is the control pipe of pair of series, first clock signal, second clock signal are flowed to respectively the control end of the pair of control pipe, thereby determining unlatching and the closure state of the pair of control pipe, one of them of wherein said pair of control pipe is connected to described primary nodal point；
Output module, it is connected with described second control module, and described output module has the first outlet tube, the second outlet tube and an outfan, nationality is selected described first outlet tube, the turning on or off of described second outlet tube by the unlatching of the pair of control pipe and closure state, and described first outlet tube, described second outlet tube the handoff procedure turned on or off in, one first reference voltage or one second reference voltage are exported by described outfan.
Signal circuit is launched in above-mentioned bilateral scanning, and wherein, in described first control module, the source of one of them transistor is in order to receive forward scan signal and to be controlled by described second control signal；The source of another transistor is in order to receive reverse scan signal and to be controlled by described first control signal；
Wherein, when described first control signal is high level and described second control signal is low level, described first control module provides forward scan signal to described primary nodal point.
Signal circuit is launched in above-mentioned bilateral scanning, and wherein, when described first control signal is low level and described second control signal is high level, described first control module provides reverse scan signal to described primary nodal point.
Signal circuit is launched in above-mentioned bilateral scanning, and wherein, described second control module includes that the first control pipe and second being cascaded controls pipe, controls pipe and described second described first and controls have secondary nodal point between pipe；
Wherein, control the described first on off state controlling pipe by described first clock signal, and controllably the signal of scanning forward or backwards at described primary nodal point is exported；And control the described second on off state controlling pipe by described second clock signal.
Signal circuit is launched in above-mentioned bilateral scanning, wherein, also includes one the 5th transistor, and its source is connected to described first reference voltage, and drain terminal is connected to described second control module.
Signal circuit is launched in above-mentioned bilateral scanning, wherein, is in series with the 7th transistor and the 6th transistor between described second clock signal and described second outlet tube；
The control end of described 7th transistor is connected with source, and described control end is also connected to the control end of described 5th transistor；
Between 5th transistor, there is the 3rd node described in described 7th transistor AND gate.
Signal circuit is launched in above-mentioned bilateral scanning, wherein, also includes one the 9th transistor, and between described second reference voltage and described 3rd node, described 9th transistor is controlled by described first clock signal.
Signal circuit is launched in above-mentioned bilateral scanning, wherein, is provided with one the 8th transistor between the control end of described first reference voltage and described second outlet tube, and the control end of described 8th transistor is connected to described secondary nodal point.
Signal circuit is launched in above-mentioned bilateral scanning, wherein, also including 1 the tenth transistor, the control end of described tenth transistor connects described second reference voltage, drain terminal is directly connected to the control end of described 8th transistor, the control end of source described first outlet tube of connection.
Signal circuit is launched in above-mentioned bilateral scanning, and wherein, described first clock signal provides high level signal or low level signal to described 3rd node by the 11st transistor AND gate the tenth two-transistor being sequentially connected in series；
Described in described 11st transistor AND gate, the control end of the tenth two-transistor is all connected to described secondary nodal point.
Signal circuit is launched in above-mentioned bilateral scanning, wherein, is provided with the first electric capacity described in described 6th transistor AND gate between the control end of the first outlet tube.
Signal circuit is launched in above-mentioned bilateral scanning, wherein, is provided with the second electric capacity between the control end of described first reference voltage and described second outlet tube.
Signal circuit is launched in above-mentioned bilateral scanning, wherein, is provided with the 3rd electric capacity between source and the control end of described 7th transistor.
Accompanying drawing explanation
The detailed description made non-limiting example with reference to the following drawings by reading, the present invention and feature, profile and advantage will become more apparent upon.The part that labelling instruction identical in whole accompanying drawings is identical.The most deliberately it is drawn to scale accompanying drawing, it is preferred that emphasis is the purport of the present invention is shown.
The schematic diagram of a kind of AMOLED bilateral scanning circuit that Fig. 1 provides for the present invention；
Fig. 2 A is the break-make situation schematic diagram of each device of the first step in the sequential chart shown in corresponding diagram 2B；
The break-make situation schematic diagram of first step device in sequential chart shown in Fig. 2 B；
Fig. 3 A is the break-make situation schematic diagram of each device of second step in the sequential chart shown in corresponding diagram 3B；
The break-make situation schematic diagram of second step device in sequential chart shown in Fig. 3 B；
Fig. 4 A is the break-make situation schematic diagram of the 3rd each device of step in the sequential chart shown in corresponding diagram 4B；
The break-make situation schematic diagram of the 3rd step device in sequential chart shown in Fig. 4 B；
Fig. 5 A is the break-make situation schematic diagram of the 4th each device of step in the sequential chart shown in corresponding diagram 5B；
The break-make situation schematic diagram of the 4th step device in sequential chart shown in Fig. 5 B；
Fig. 6 A is the break-make situation schematic diagram of the 5th each device of step in the sequential chart shown in corresponding diagram 6B；
The break-make situation schematic diagram of the 5th step device in sequential chart shown in Fig. 6 B；
Fig. 7 A is the break-make situation schematic diagram of the 6th each device of step in the sequential chart shown in corresponding diagram 7B；
The break-make situation schematic diagram of the 6th step device in sequential chart shown in Fig. 7 B；
Fig. 8 A 8B is present invention analogous diagram under up sequential；
Fig. 9 A 9B is present invention analogous diagram under down sequential.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.It is, however, obvious to a person skilled in the art that the present invention can be carried out without these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, in order to explaination technical scheme.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these describe in detail, the present invention can also have other embodiments.
Signal circuit is launched in a kind of bilateral scanning, shown in reference Fig. 1, including:
First control module A1, there is pair of transistor M13 and M14, first control signal down contrary by two logical states and the second control signal up control this opening and closing to transistor M13 and M14 respectively, this to be transported to one of them forward scan signal en+1 connected or reverse scan signal en 1 of transistor M13 and M14 at this primary nodal point NET1 to connecting between transistor；
Second control module A2, there is control pipe M3 and M4 of pair of series, one of them source controlling pipe is connected to primary nodal point NET1, one group of clock signal cke1, cke2 are flowed to respectively this control end to controlling pipe M3 and M4, thereby determine this to controlling the unlatching of pipe M3 and M4 and closure state, wherein this is connected to primary nodal point NET1 to one of them controlling pipe M3 and M4；
Output module A3, it is connected with the second control module A2, and output module A3 has the first outlet tube M1, the second outlet tube M2 and an outfan en, output module A3 nationality is selected the first outlet tube M1, the turning on or off of the second outlet tube M2 by the unlatching of each control pipe M3 and M4 and closure state, and the first outlet tube M1, the second outlet tube M2 the handoff procedure turned on or off in, one first reference voltage VDD or one second reference voltage VEE is exported by outfan en.Wherein, the first reference voltage VDD is in a high levle, and the second reference voltage VEE first reference voltage VDD that compares is in a low level, and therefore the second reference voltage VEE is lower than the first reference voltage VDD.
As a kind of preferred embodiment of the present invention, in the first control module A1, the source of one of them transistor M14 is in order to receive forward scan signal en+1, and this transistor M14 is controlled by the second control signal down；The source of another transistor M13 is in order to receive a reverse scan signal en 1, and this transistor is controlled by the first control signal up；When the first control signal up is high level and the second control signal down is low level, transistor M14 opens, and the first control module A1 provides a forward scan signal en+1 to primary nodal point NET1.
On this basis, further, when the first control signal up is low level and the second control signal down is high level, transistor M14 opens, and the first control module A1 provides reverse scan signal en 1 to a primary nodal point NET1.
As a kind of preferred embodiment of the present invention, the second control module A2 includes that the first control pipe M3 and second being cascaded controls pipe M4, controls pipe M3 and second first and controls have secondary nodal point NET4 between pipe M4；
Wherein, controlled the on off state of the first control pipe M3 by the first clock signal cke1, and controllably the signal of scanning forward or backwards at primary nodal point NET1 is exported；And the on off state of the second control pipe M4 is controlled by second clock signal cke2.
As a kind of preferred embodiment of the present invention, also including one the 5th transistor M5, its source is connected to the first reference voltage VDD, and drain terminal is connected to the second control module A2, has node NET5 between the 5th transistor M5 and the second control module A2.
As a kind of preferred embodiment of the present invention, it is in series with the 7th transistor M7 and the 6th transistor M6 between second clock signal cke2 and the second outlet tube M2, between the 7th transistor M7 and the 6th transistor M6, there is node NET9；
The control end of the 7th transistor M7 is connected with source, and control end is also connected to the control end of the 5th transistor M5；
Between 7th transistor M7 and the 5th transistor M5, there is the 3rd node NET6.
As a kind of preferred embodiment of the present invention, also including one the 9th transistor M9, between the second reference voltage VEE and the 3rd node NET6, the 9th transistor M9 is controlled by the first clock signal cke1.
As a kind of preferred embodiment of the present invention, being provided with one the 8th transistor M8 between the control end of the first reference voltage VDD and the second outlet tube M2, the control end of the 8th transistor M8 is connected to secondary nodal point NET4.
As a kind of preferred embodiment of the present invention, also including 1 the tenth transistor M10, the control end of the tenth transistor M10 connects the second reference voltage VEE, and drain terminal is directly connected to the control end of the 8th transistor M8, and source connects the control end of the first outlet tube M1.
As a kind of preferred embodiment of the present invention, the first clock signal cke1 provides high level signal or low level signal to the 3rd node NET6 by the 11st transistor M11 being sequentially connected in series and the tenth two-transistor M12；
The control end of the 11st transistor M11 and the tenth two-transistor M12 is all connected to secondary nodal point NET4.
As a kind of preferred embodiment of the present invention, between the control end of the 6th transistor M6 and the first outlet tube M1, it is provided with the first electric capacity C2.
As a kind of preferred embodiment of the present invention, between the control end of the first reference voltage VDD and the second outlet tube M2, it is provided with one second electric capacity C3, between the second outlet tube M2 and the second electric capacity C3, there is node NET8.
As a kind of preferred embodiment of the present invention, between source and the control end of the 7th transistor M7, it is provided with the 3rd electric capacity C4.
Below in conjunction with the circuit diagram shown in Fig. 2 A to Fig. 7 B and oscillogram, the present invention concrete is controlled procedure declaration as follows:
The first step (Step1): with reference to shown in Fig. 2 A and Fig. 2 B: the first clock signal cke1 input low level signal, second clock signal cke2 input high level signal, therefore first controls pipe M3 unlatching, and second controls pipe M4 closes；First control signal down input high level signal, second control signal up input low level signal, transistor M14 is opened, and transistor M13 closes, the forward scan signal en 1 (i.e. Ste signal in Fig. 2 B) of high level signal is able to be circulated by transistor M14, and is connected to secondary nodal point NET4.Due to the first conducting controlling pipe M3, the forward scan signal en 1 of high level signal makes the 11st transistor M11 and the tenth two-transistor M12 turn off；Owing to the tenth transistor M10 is in open mode by the effect of the second reference voltage VEE of low level signal, therefore the forward scan signal en 1 of high level signal can continue through the tenth transistor M10 and arrive the control end of the first outlet tube M1, makes the first outlet tube M1 turn off；And the second outlet tube M2 is in the off state of high level so that circuit is maintained at the low level state in moment, the 3rd electric capacity C4 keeps NET6 to be low level at this.
Second step (Step2): with reference to shown in Fig. 3 A and Fig. 3 B, the first clock signal cke1 input high level signal, second clock signal cke2 input low level signal, therefore second controls pipe M4 unlatching, and first controls pipe M3 closes；First control signal down input high level signal, second control signal up input low level signal, 14th transistor M14 is opened, second outlet tube M13 closes, but owing to the first control pipe M3 is closed, therefore cause forward scan signal en 1 cannot control pipe M3 by first to circulate, therefore seldom repeat for the second control module A2.All opening owing to the 5th transistor M5 and second controls pipe M4, therefore the first reference voltage VDD of high level is able to carry out turning on and be conveyed to secondary nodal point NET4 by transistor M5, M4 so that first outlet tube M11, M12 turns off.First outlet tube M1 is turned off by the first reference voltage VDD of high level by the tenth transistor M10 opened simultaneously.And simultaneously, low level second clock signal cke2 arrives the control end of the second outlet tube M2 by transistor M7, the M6 opened, i.e. node NET8 is low level, and then opens the second outlet tube M2 so that the first reference voltage VDD of outfan en output high level；Wherein, the 3rd electric capacity C4 plays coupling, because second clock signal cke2 voltage step-down exports node NET9, and then couples the 3rd node NET6 voltage step-down by the 3rd electric capacity C4, so that lower voltage can export node NET9 and NET8.
3rd step (Step3): with reference to shown in Fig. 4 A and Fig. 4 B, the first clock signal cke1 input low level signal, second clock signal cke2 input high level signal, therefore first controls pipe M3 unlatching, and second controls pipe M4 closes；First control signal down input high level signal, second control signal up input low level signal, 14th transistor M14 is opened, second outlet tube M13 closes, the forward scan signal en 1 of high level signal is able to be circulated by the 14th transistor M14, and is connected to secondary nodal point NET4.Due to the first conducting controlling pipe M13, the forward scan signal en 1 of high level signal makes the 11st transistor M11 and the tenth two-transistor M12 turn off；Owing to the tenth transistor M10 is in open mode by the effect of low level second reference voltage VEE, therefore the forward scan signal en 1 of high level signal can continue through the tenth transistor M10 and arrive the control end of the first outlet tube M1, the first outlet tube M1 is made to turn off, wherein, it is low level that the effect of the second electric capacity C3 is to maintain the voltage of node NET8, such that it is able to open the second outlet tube M2.
4th step (Step4): with reference to shown in Fig. 5 A and Fig. 5 B, first clock signal cke1 input high level signal, second clock signal cke2 input low level signal, therefore second controls pipe M4 unlatching, first controls pipe M3 closes, owing to the first control pipe M3 is closed, therefore cause forward scan signal en 1 cannot control pipe M3 by first and circulate, therefore seldom repeat for the second control module A2.All opening owing to the 5th transistor M5 and second controls pipe M4, therefore the first reference voltage VDD of high level is able to carry out turning on and be conveyed to secondary nodal point NET4 by transistor M5, M4 so that first outlet tube M11, M12 turns off.First outlet tube M1 is turned off by the first reference voltage VDD of high level by the tenth transistor M10 opened simultaneously.And simultaneously, low level second clock signal cke2 arrives the control end of the second outlet tube M1 by transistor M7, the M6 opened, and then open the second outlet tube M1, make the first reference voltage VDD of outfan en output high level, wherein, the 3rd electric capacity C4 role is identical with its effect played in second step, specifically describes and refer to second step, repeating for reducing, at this, just it will not go into details.
5th step (Step5): with reference to shown in Fig. 6 A and Fig. 6 B, first clock signal cke1 input low level signal, second clock signal cke2 input high level signal, therefore first controls pipe M3 unlatching, second controls pipe M4 closes, and opens transistor M9 simultaneously；First control signal down input high level signal, second control signal up input low level signal, 14th transistor M14 is opened, second outlet tube M13 closes, the forward scan signal en 1 of low level signal is able to be circulated by the 14th transistor M14, and is connected to secondary nodal point NET4, and low level signal arrives the control end of the first outlet tube M1 by the tenth transistor M10, make the first outlet tube M1 open, export the second reference voltage VEE by outfan en.
null6th step (Step6): with reference to shown in Fig. 7 A and Fig. 7 B，First clock signal cke1 input high level signal，Second clock signal cke2 input low level signal，In circuit, the break-make situation of each device is with reference to shown in Fig. 7 B，First outlet tube M1 opens under low level state，And the second outlet tube M1 closes when high level，Make the second reference voltage VEE of outfan en output low level，Wherein，The effect of the first electric capacity C2 is coupling，Because second clock signal cke2 voltage step-down，And node NET12 now floats (floating)，So node NET12 can follow second clock signal cke2 voltage step-down to reduce，The control terminal voltage of such first outlet tube M1 can be lower，Thereby may be ensured that the low-voltage of the second reference voltage VEE can be input to outfan En.And the effect of the tenth transistor M10 can ensure that transistor seconds NET4 will not produce lower voltage; keep a constant low level; control pipe M3, the 11st transistor M11 and the tenth two-transistor M12 and the 8th transistor M8 so can be protected not to be affected by big cross-pressure.
Circuit provided by the present invention can realize bilateral scanning, controlling scanning direction by the signal of up and down is from top to bottom or from the bottom up, the sequential using Fig. 8 A and Fig. 9 A controls, produce the sequential of up and the down order of Fig. 8 B and Fig. 9 B, can be seen that, the sequential of up and down is just in turn, solves the desired problem solved of the present invention.
Bilateral scanning provided by the present invention is launched signal circuit and be can be applicable to, in AMOLED field, to drive AMOLED to be operated, improve product competitiveness.
Above presently preferred embodiments of the present invention is described.It is to be appreciated that the invention is not limited in above-mentioned particular implementation, the equipment and the structure that do not describe in detail the most to the greatest extent are construed as being practiced with the common mode in this area；Any those of ordinary skill in the art, without departing under technical solution of the present invention ambit, technical solution of the present invention is made many possible variations and modification by the method and the technology contents that all may utilize the disclosure above, or it being revised as the Equivalent embodiments of equivalent variations, this has no effect on the flesh and blood of the present invention.Therefore, every content without departing from technical solution of the present invention, the technical spirit of the foundation present invention, to any simple modification made for any of the above embodiments, equivalent variations and modification, all still falls within the range of technical solution of the present invention protection.
Claims (13)
1. signal circuit is launched in a bilateral scanning, it is characterised in that including:
First control module, has pair of transistor, by the first control that two logical states are contrary
Signal processed, the second control signal control the opening and closing of the pair of transistor respectively, with
One of them one connected of the pair of transistor scanning signal forward or backwards is transported to
At the primary nodal point connected between the pair of transistor；
Second control module, has the control pipe of pair of series, by the first clock signal, second
Clock signal flows to the control end of the pair of control pipe respectively, thereby determines the pair of control
The unlatching of tubulation and closure state, one of them of wherein said pair of control pipe is connected to described
Primary nodal point；And
Output module, is connected with described second control module, and described output module has first
Outlet tube, the second outlet tube and an outfan, nationality by the unlatching of the pair of control pipe and
Closure state selects described first outlet tube, the turning on or off of described second outlet tube, and
Described first outlet tube, described second outlet tube the handoff procedure turned on or off in, will
One first reference voltage or one second reference voltage are exported by described outfan.
2. signal circuit is launched in bilateral scanning as claimed in claim 1, it is characterised in that
In described first control module, the source of one of them transistor is in order to receive forward scan signal
And controlled by described second control signal；The source of another transistor is reversely swept in order to receive
Retouch signal and controlled by described first control signal；
Wherein, it is high level when described first control signal and described second control signal is low electricity
At ordinary times, described first control module provides forward scan signal to described primary nodal point.
3. signal circuit is launched in bilateral scanning as claimed in claim 2, it is characterised in that
When described first control signal is low level and described second control signal is high level, described
First control module provides reverse scan signal to described primary nodal point.
4. signal circuit is launched in bilateral scanning as claimed in claim 1, it is characterised in that
Described second control module includes that the first control pipe and second being cascaded controls pipe, in institute
State the first control pipe and described second and control, between pipe, there is secondary nodal point；
Wherein, the described first switch shape controlling pipe is controlled by described first clock signal
State, and controllably the signal of scanning forward or backwards at described primary nodal point is exported；
And control the described second on off state controlling pipe by described second clock signal.
5. signal circuit is launched in bilateral scanning as claimed in claim 1, it is characterised in that also
Including one the 5th transistor, its source is connected to described first reference voltage, and drain terminal is connected to institute
State the second control module.
6. signal circuit is launched in the bilateral scanning as described in claim 4 or 5, and its feature exists
In, it is in series with the 7th transistor and between described second clock signal and described second outlet tube
Six transistors；
The control end of described 7th transistor is connected with source, and described control end is also connected to
The control end of described 5th transistor；
Between 5th transistor, there is the 3rd node described in described 7th transistor AND gate.
7. signal circuit is launched in bilateral scanning as claimed in claim 6, it is characterised in that also
Including one the 9th transistor, between described second reference voltage and described 3rd node, institute
State the 9th transistor to be controlled by described first clock signal.
8. signal circuit is launched in bilateral scanning as claimed in claim 4, it is characterised in that institute
State and between the control end of the first reference voltage and described second outlet tube, be provided with one the 8th crystal
Pipe, the control end of described 8th transistor is connected to described secondary nodal point.
9. signal circuit is launched in bilateral scanning as claimed in claim 8, it is characterised in that also
Including 1 the tenth transistor, the control end of described tenth transistor connects described second with reference to electricity
Pressure, drain terminal are directly connected to the control end of described 8th transistor, source connects described first output
The control end of pipe.
10. signal circuit is launched in bilateral scanning as claimed in claim 6, it is characterised in that
Described first clock signal is carried by the 11st transistor AND gate the tenth two-transistor being sequentially connected in series
Described 3rd node is given for high level signal or low level signal；
The control end of the tenth two-transistor described in described 11st transistor AND gate is all connected to described
Secondary nodal point.
Signal circuit is launched in 11. bilateral scannings as claimed in claim 6, it is characterised in that
It is provided with the first electric capacity between the control end of the first outlet tube described in described 6th transistor AND gate.
Signal circuit is launched in 12. bilateral scannings as claimed in claim 1, it is characterised in that
It is provided with the second electric capacity between the control end of described first reference voltage and described second outlet tube.
Signal circuit is launched in 13. bilateral scannings as claimed in claim 6, it is characterised in that
It is provided with the 3rd electric capacity between source and the control end of described 7th transistor.
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| CN201510067624.XA CN105989798B (en) | 2015-02-09 | 2015-02-09 | A kind of bilateral scanning transmitting signal circuit |
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| CN105989798B (en) | 2018-10-16 |
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Address after: 201506, building two, building 100, 1, Jinshan Industrial Road, 208, Shanghai, Jinshan District Patentee after: Shanghai Hehui optoelectronic Co., Ltd Address before: 201506, building two, building 100, 1, Jinshan Industrial Road, 208, Shanghai, Jinshan District Patentee before: EverDisplay Optronics (Shanghai) Ltd. |