CN109243352B - Driving circuit, driving method thereof and display device - Google Patents
Driving circuit, driving method thereof and display device Download PDFInfo
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- CN109243352B CN109243352B CN201710560152.0A CN201710560152A CN109243352B CN 109243352 B CN109243352 B CN 109243352B CN 201710560152 A CN201710560152 A CN 201710560152A CN 109243352 B CN109243352 B CN 109243352B
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The embodiment of the invention discloses a driving circuit, a driving method thereof and a display device. Wherein, this drive circuit includes: the driving circuit comprises a driving signal input unit, a first control unit, a second control unit, a first holding unit, a second holding unit and a pressure difference control unit which are connected in series, wherein the output end of the first holding unit is connected with the output end of the driving circuit; the input end of the second holding unit is connected with the first end of the differential pressure control unit, and the output end of the second holding unit is connected with the output end of the driving circuit; the second end of the differential pressure control unit is connected with the second level signal input end of the driving circuit, the control end of the first holding unit is connected with the second node, and the control end of the second holding unit is connected with the first node; the voltage difference control unit is used for controlling the voltage difference change between the input end and the output end of the second holding unit. The embodiment of the invention can avoid the circuit characteristic drift, which causes the abnormal output of the driving circuit and the abnormal work of the display panel.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a driving circuit, a driving method thereof and a display device.
Background
The smart phone, the smart television and the like can display various pictures through the display panel. When pixels on the display panel are lit, a gate driving circuit is generally required to output a scanning signal, the scanning signal is transmitted to the pixel driving circuit through a scanning line, a thin film transistor of the pixel driving circuit is controlled to be turned on, and a data signal on a data line is written into the pixels to control the brightness of the pixels, so that various pictures are displayed.
The gate driving circuit generally includes a pull-up module, a pull-down module, a pull-up control module, and a pull-down control module, wherein an output terminal of the pull-up module is connected to an output terminal of the pull-down module to output a driving signal, and each module generally includes a transistor circuit. The pull-up control component controls the pull-up component to output a high level, and the pull-down control component controls the pull-down component to output a low level. Some products, such as virtual reality products, often require the display panel to maintain a black screen state for a long time, and at this time, the gate driving circuit is required to output a high level for a long time. The output end of the gate driving circuit outputs high level for a long time, which causes the drain-source voltage of the thin film transistor in the pull-down component with the pull-down function to bear a constant voltage for a long time, resulting in the characteristic drift of the thin film transistor, causing the output abnormality of the gate driving circuit, and the display panel can not work normally.
Disclosure of Invention
Embodiments of the present invention provide a driving circuit, a driving method thereof, and a display device, so as to improve stability of circuit performance of a display panel and solve a problem of circuit characteristic drift caused when an output terminal of the driving circuit maintains a constant output state for a long time.
In a first aspect, an embodiment of the present invention provides a driving circuit, including:
the control end of the driving signal input unit is connected with the first clock signal input end of the driving circuit, the input end of the driving signal input unit is connected with the trigger signal input end of the driving circuit, and the output end of the driving signal input unit is connected with the first node;
the first control end and the second control end of the first control unit are respectively connected with the first clock signal input end and the second clock signal input end of the driving circuit, the input ends of the first control unit and the second control unit are connected with the second level signal input end of the driving circuit, and the output ends of the first control unit and the second control unit are connected with the second node and used for controlling the potential of the second node;
the input end of the second control unit is connected with the second clock signal input end, and the output end of the second control unit is connected with the first node and used for controlling the potential of the first node;
the voltage difference control circuit comprises a first holding unit, a second holding unit and a voltage difference control unit which are connected in series, wherein the input end of the first holding unit is connected with the first level signal input end of the driving circuit, and the output end of the first holding unit is connected with the output end of the driving circuit; the input end of the second holding unit is connected with the output end of the differential pressure control unit, and the output end of the second holding unit is connected with the output end of the driving circuit; a first input end of the differential pressure control unit is connected with a second level signal input end of the driving circuit, a control end of the first holding unit is connected with the second node, and a control end of the second holding unit is connected with the first node; the voltage difference control unit is used for controlling the voltage difference change between the input end and the output end of the second holding unit.
In a second aspect, an embodiment of the present invention further provides a display device, including the driving circuit provided in any embodiment of the present invention.
In a third aspect, an embodiment of the present invention further provides a driving method for a driving circuit, for driving the driving circuit provided in any embodiment of the present invention, where the driving method includes:
in the pull-up output stage, the second holding unit is turned off, the first holding unit is turned on, and the driving circuit outputs a first level signal; the voltage difference control unit is switched on or switched off to control the voltage difference between the input end and the output end of the second holding unit to change;
in the pull-down output stage, the first holding unit is turned off, the second holding unit and the differential pressure control unit are turned on, and the driving circuit outputs a second level signal.
According to the embodiment of the invention, the voltage difference between the input end and the output end of the second holding unit is changed rather than kept constant by introducing the voltage difference control unit, so that the problems that the output of the driving circuit is abnormal and the display panel cannot work normally due to circuit characteristic drift caused by the fact that the input end and the output end of the second holding unit bear a constant voltage for a long time when the output end of the driving circuit outputs a first level signal for a long time, for example, a high level signal, are solved, and the stability and the reliability of the driving circuit are improved.
Drawings
Fig. 1 is a schematic structural diagram of a driving circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another driving circuit according to an embodiment of the present invention;
FIG. 3 is a timing waveform diagram of various control signals and output signals corresponding to FIG. 2;
fig. 4 is a schematic diagram illustrating the on/off states of the transistors in the driving circuit corresponding to the stage t1 in fig. 2;
fig. 5 is a schematic diagram illustrating the on/off states of the transistors in the driving circuit corresponding to the stage t2 in fig. 2;
fig. 6 is a schematic diagram illustrating the on/off states of the transistors in the driving circuit corresponding to the stage t3 in fig. 2;
fig. 7 is a schematic diagram illustrating the on/off states of transistors in the driving circuit corresponding to the stage t4 in fig. 2;
fig. 8 is a schematic diagram illustrating the on/off states of transistors in the driving circuit corresponding to the stage t5 in fig. 2;
fig. 9 is a schematic diagram of the on/off states of the transistors in the driving circuit corresponding to the stage t6 in fig. 2;
fig. 10 is a schematic diagram illustrating the on/off states of the transistors in the driving circuit corresponding to the stage t7 in fig. 2;
fig. 11 is a schematic diagram illustrating the on/off states of transistors in the driving circuit corresponding to the stage t8 in fig. 2;
fig. 12 is a schematic diagram illustrating the on/off states of the transistors in the driving circuit corresponding to the stage t9 in fig. 2;
fig. 13 is a schematic diagram illustrating the on/off states of the transistors in the driving circuit corresponding to the stage t10 in fig. 2;
fig. 14 is a schematic diagram illustrating the on/off states of transistors in the driving circuit corresponding to the stage t11 in fig. 2;
fig. 15 is a schematic diagram illustrating the on/off states of the transistors in the driving circuit corresponding to the stage t12 in fig. 2;
fig. 16 is a schematic structural diagram of a display device according to an embodiment of the present invention;
fig. 17 is a flowchart of a driving method of a driving circuit according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a schematic structural diagram of a driving circuit according to an embodiment of the present invention, as shown in fig. 1, the driving circuit includes: a driving signal input unit 110, a first control unit 120, a second control unit 130, a first holding unit 140, a second holding unit 150, and a differential pressure control unit 160.
The control end Ctrl of the driving signal input unit 110 is connected to the first clock signal input end CKE1 of the driving circuit, the input end In is connected to the trigger signal input end STE of the driving circuit, and the output end Out is connected to the first node NET 1; a first control unit 120, having a first control terminal Ctrl1 and a second control terminal Ctrl2 connected to a first clock signal input terminal CKE1 and a second clock signal input terminal CKE2 of the driving circuit, respectively, an input terminal In connected to a second level signal input terminal VEE of the driving circuit, and an output terminal Out connected to a second node NET2, for controlling the potential of the second node NET 2; a second control unit 130, an input terminal In of which is connected to the second clock signal input terminal CKE2 and an output terminal Out of which is connected to the first node NET1, for controlling the potential of the first node NET 1; a first holding unit 140, a second holding unit 150, and a voltage difference control unit 160 connected In series, wherein an input terminal In of the first holding unit 140 is connected to a first level signal input terminal VDD of the driving circuit, and an output terminal Out of the first holding unit 140 is connected to an output terminal En of the driving circuit; an input end In of the second holding unit 150 is connected with an output end Out of the differential pressure control unit 160, and an output end Out of the second holding unit 150 is connected with an output end En of the driving circuit; the first input end In1 of the differential pressure control unit 160 is connected to the second level signal input end VEE of the driving circuit, the control end Ctrl of the first holding unit 140 is connected to the second node NET2, and the control end Ctrl of the second holding unit 150 is connected to the first node NET 1; the voltage difference control unit 160 is used to control a change In the voltage difference between the input terminal In and the output terminal Out of the second holding unit 150.
It should be noted that, under the voltage control action of the second node NET2, the first holding unit 140 may write the first level signal input by the first level signal input terminal VDD into the output terminal En of the driving circuit; the second holding unit 150 and the differential voltage control unit 160 may write the second level signal input from the second level signal input terminal VEE into the output terminal En of the driving circuit under the voltage control of the first node NET 1. The first level signal and the second level signal have unequal voltages, and the first level signal and the second level signal may be direct current signals. The trigger signal input terminal STE can input a trigger signal. The first clock signal input terminal CKE1 and the second clock signal input terminal CKE2 input the first clock signal and the second clock signal, respectively. The first clock signal and the second clock signal may be pulse signals with equal periods and equal pulse widths and different phases, for example, the phases of the first clock signal and the second clock signal are different by 180 °. The driving signal input unit 110 may write a high level signal or a low level signal of the trigger signal into the first node NET1 under the action of the trigger signal and the first clock signal, and give an initial potential to the first node NET1, thereby controlling the potential of the first node NET 1. The first control unit 120 may write a level signal of the second clock signal to the second node NET2 by the first clock signal and the second clock signal, thereby controlling the potential of the second node NET 2. The second control unit 130 controls, such as pulls down or pulls up, the potential of the level signal that triggers writing of the signal to the first node NET1 by the second clock signal. When the output end En of the driving circuit outputs the written first level signal, the voltage difference control unit 160 is configured to control the voltage of the input end In of the second holding unit 150 so that the voltage difference between the input end In and the output end Out of the second holding unit 150 varies instead of being kept constant. For example, when the output terminal of the driving circuit outputs the first level signal for a long time, the level signal of the output terminal Out of the second holding unit 150 is a high level signal, and if the input terminal of the second holding unit 150 also keeps inputting the low level signal, a constant voltage is applied between the input terminal and the output terminal of the second holding unit 150 for a long time, which causes circuit characteristic drift, causes abnormal output of the driving circuit, and the display panel cannot work normally. Since the voltage difference control unit can control the voltage of the input terminal In of the second holding unit 150, so that the voltage difference between the input terminal In and the output terminal Out of the second holding unit 150 is changed rather than kept constant, the problem of circuit characteristic drift caused by the fact that the input terminal In and the output terminal Out of the second holding unit 150 bear a higher constant voltage for a long time can be solved, and the reliability of the driving circuit is improved.
Optionally, as shown In fig. 1, the differential pressure control unit 160 further includes a second input terminal In2, a first control terminal Ctrl1, and a second control terminal Ctrl2, the second input terminal In2 of the differential pressure control unit 160 is connected to the first clock signal input terminal CKE1, the first control terminal Ctrl1 of the differential pressure control unit 160 is connected to the first node NET1, and the second control terminal Ctrl2 of the differential pressure control unit 160 is connected to the second node NET 2.
When the output end En of the driving circuit outputs a high-level signal, the differential pressure control unit 160 writes the first clock signal input from the first clock signal input end CKE1 into the output end Out of the differential pressure control unit 160 under the action of the voltage of the second node NET2, so that the voltage difference between the input end In and the output end Out of the second holding unit 150 is variable rather than constant.
Optionally, as shown In fig. 1, the differential pressure control unit 160 further includes a second input terminal In2, a first control terminal Ctrl1, and a second control terminal Ctrl2, the second input terminal In2 of the differential pressure control unit 160 is connected to the second clock signal input terminal CKE2, the first control terminal Ctrl1 of the differential pressure control unit 160 is connected to the first node NET1, and the second control terminal Ctrl2 of the differential pressure control unit 160 is connected to the second node NET 2.
When the output end En of the driving circuit outputs a high-level signal, the differential pressure control unit 160 writes the second clock signal input from the second clock signal input end CKE2 into the output end Out of the differential pressure control unit 160 under the action of the voltage of the second node NET2, so that the voltage difference between the input end In and the output end Out of the second holding unit 150 is variable rather than constant.
The present embodiment provides still another driving circuit, and referring to fig. 2, the present embodiment is optimized based on the above embodiments, and specifically, the driving signal input unit includes a first transistor M1, the first control unit includes a second transistor M2, a third transistor M3, a fourth transistor M4, a twelfth transistor M12, a thirteenth transistor M13 and a first capacitor C1, the second control unit includes a second capacitor C2, the first holding unit includes a fifth transistor M5, the second holding unit includes a sixth transistor M6, and the differential pressure control unit includes a seventh transistor M7 and an eighth transistor M8.
The gate of the first transistor M1 is connected to the first clock signal input terminal CKE1, the first pole is connected to the trigger signal input terminal STE, and the second pole is connected to the first node NET 1; the gate of the second transistor M2 is connected to the first clock signal input terminal CKE1, the second pole is connected to the second level signal input terminal VEE, and the first pole is connected to the gate of the third transistor M3; a first pole of the third transistor M3 is connected to the second clock signal input terminal CKE2, a second pole is connected to the first pole of the first capacitor C1, and a second pole of the first capacitor C1 is connected to the gate of the third transistor M3; the gate of the fourth transistor M4 is connected to the second clock signal input terminal CKE2, the first pole is connected to the first pole of the first capacitor C1, and the second pole is connected to the gate of the fifth transistor M5; a gate of the twelfth transistor M12 is connected to the first node NET1, a first pole is connected to the gate of the third transistor M3, and a second pole is connected to the first pole of the thirteenth transistor M13; a gate of the thirteenth transistor M13 is connected to the first node NET1, and a second pole is connected to the first clock signal input terminal CKE 1; a second pole of the fifth transistor M5 is connected to the first level signal input terminal VDD, and a first pole is connected to the output terminal En of the driving circuit; the gate of the sixth transistor M6 is connected to the first pole of the second capacitor C2, the second pole is connected to the output end En of the driving circuit, and the first pole is connected to the second pole of the seventh transistor M7; the second pole of the second capacitor C2 is connected to the second clock signal input CKE 2; the gate of the seventh transistor M7 is connected to the first node NET1, and the first pole is connected to the second level signal input terminal VEE; the gate of the eighth transistor M8 is connected to the second node NET2, and the first pole is connected to the first clock signal input terminal CKE1 or the second clock signal input terminal CKE 2; the second pole is connected to the second pole of the seventh transistor M7.
Wherein each transistor can be a P-type transistor.
It should be noted that the first level signal input terminal VDD may also be an input low level signal, the second level signal input terminal VEE may also be an input high level signal, and accordingly, each transistor may also be an N-type transistor.
In the embodiment of the present invention, a high level signal is input from a first level signal input terminal VDD, a low level signal is input from a second level signal input terminal VEE, a first clock signal is input from a first clock signal input terminal VEE, a second clock signal is input from a second clock signal input terminal VEE, each transistor is a P-type transistor, and a first electrode of each transistor is a drain electrode and a second electrode thereof is a source electrode. When the first clock signal is a low level signal, the first transistor M1 is turned on, and a high level signal or a low level signal of the trigger signal input from the trigger signal input terminal is written into the first node NET 1. When the first clock signal is a high signal, the first transistor M1 will be turned off, and the first node NET1 will maintain the voltage at the previous moment. When the first node NET1 is at a high level, if the first clock signal is a low level signal, the second transistor M2 will be turned on, and the low level signal inputted from the second level signal input terminal VEE will be written into the gate of the third transistor M3, i.e. into the third node NET3, and when the second clock signal is a low level signal, the third transistor M3 and the fourth transistor M4 will be turned on simultaneously, and the low level signal of the second clock signal can be written into the second node NET 2. When the second node NET2 is at low level and the first node NET1 is at high level, the fifth transistor M5 is turned on, the sixth transistor M6 is turned off, the seventh transistor M7 is turned off, the eighth transistor M8 is turned on, a high level signal inputted from the first level signal input terminal VDD is written into the output terminal En of the driving circuit, the output terminal En of the driving circuit outputs a high level signal, and the first clock signal or the second clock signal is written into the first pole of the sixth transistor M6, since the first clock signal and the second clock signal are pulse signals and are non-constant voltages, the voltage of the first pole of the sixth transistor M6 is changed, so that the voltage difference between the drain and the source of the sixth transistor M6 is non-constant, and when the output terminal of the driving circuit outputs a high level signal for a long time, a constant voltage is applied between the drain and the source of the sixth transistor M6 for a long time, the transistor characteristic drift is caused, the output of the driving circuit is abnormal, and the display panel can not work normally. When the second node NET2 is at a high level, the first node NET1 is at a low level, and the second clock signal is at a high level, the sixth transistor M6 is turned on, the fifth transistor M5 is turned off, the seventh transistor M7 is turned on, the eighth transistor M8 is turned off, and the voltage output by the output end En of the driving circuit is the sum of the absolute value of the voltage of the low-level signal and the absolute value of the turn-on voltage Vth; meanwhile, when the second clock signal is changed from the original high-level signal to the low-level signal, under the pull-down action of the second capacitor C2, the gate voltage of the sixth transistor M6 is pulled down, so that the low-level signal input by the second level signal input terminal VEE is written into the output terminal En of the driving circuit, and the output terminal En of the driving circuit outputs the low-level signal. The turn-on voltage Vth is a gate-source voltage at which the transistor starts to conduct under the action of a drain-source voltage. When the first node NET1 is at a low level and the first clock signal is at a high level, the twelfth transistor M12 and the thirteenth transistor M13 are turned on, so that the high level signal of the first clock signal can be written into the third node NET3, and the third transistor M3 is turned off, thereby preventing the third transistor M3 and the fourth transistor M4 from being turned on simultaneously and writing the low level signal of the second clock signal into the second node NET2 when the second clock signal is at a low level. When the second node NET2 and the first node NET1 are both low, the sixth transistor M6, the fifth transistor M5, the seventh transistor M7 and the eighth transistor M8 are all turned off, and the output end En of the driving circuit maintains the output voltage at the previous time. The first capacitor C1 has the effect of holding the voltage of the third node NET 3.
Preferably, the first control unit further includes a ninth transistor M9; the gate of the ninth transistor M9 is connected to the first node NET1, the first pole is connected to the first level signal VDD input terminal, and the second pole is connected to the second node NET 2.
When the first clock signal and the trigger signal are both low level signals, the first transistor M1 is turned on, and the low level signal of the trigger signal is written into the first node NET1, so that the ninth transistor M9 is turned on, and the high level signal input from the first level signal input terminal VDD is written into the second node NET 2.
Further, the first control unit 120 further includes a third capacitor C3, a first pole of the third capacitor C3 is connected to the first level signal VDD input terminal, and a second pole of the third capacitor C3 is connected to the gate of the fifth transistor M5. The third capacitor C3 has the effect of holding the voltage of the second node NET 2.
Optionally, the driving circuit provided in the embodiment of the present invention further includes a voltage stabilizing unit, where the voltage stabilizing unit includes a tenth transistor M10 and an eleventh transistor M11; a gate of the tenth transistor M10 is connected to the gate of the third transistor M3, a second pole is connected to the first level signal VDD input terminal, and a first pole is connected to the second pole of the eleventh transistor M11; the gate of the eleventh transistor M11 is connected to the second clock signal input terminal CKE2, and the first pole is connected to the first node NET 1.
It should be noted that, when the first node NET1 is at a high level and the third node NET3 is at a low level, and the second clock signal is at a low level, the tenth transistor M10 and the eleventh transistor M11 are turned on, so that the high level signal input from the first level signal input terminal VDD can be written into the first node NET1, which has the function of stabilizing the high voltage of the first node NET 1.
Illustratively, fig. 3 is a timing diagram provided by an embodiment of the present invention. Wherein ck1 represents the first clock signal inputted from the first clock signal input terminal CKE1, ck2 represents the second clock signal inputted from the second clock signal input terminal CKE2, st represents the signal inputted from the trigger signal input terminal STE, and the following description will be given by taking the circuit diagrams and timing diagrams shown in fig. 2 to 15 as an example that the first level signal input terminal VDD inputs a high level signal, the second level signal input terminal VEE inputs a low level signal, and the first pole of the eighth transistor M8 is connected to the first clock signal input terminal CKE1, and the specific control process of the driving circuit of the present invention is described as follows:
stage t 1: the trigger signal st is a high-level signal, the first clock signal ck1 is a low-level signal, the second clock signal ck2 is a high-level signal, the on-off condition of each transistor in the circuit is shown in fig. 4, the first transistor M1 is turned on under the action of the low-level signal of the first clock signal ck1, the high-level signal of the trigger signal st is written into the first node NET1, the sixth transistor M6 is turned off, the high-level signal input by the first level signal input end VDD is written into the second node NET2, namely the gate of the fifth transistor M5, the fifth transistor M5 is turned off, and the output end En of the driving circuit keeps outputting the low-level signal; the second transistor M2 is turned on by the low level signal of the first clock signal ck1, and writes the low level signal inputted from the second level signal input terminal VEE into the third node NET 3.
Stage t 2: the trigger signal st is a high-level signal, the first clock signal ck1 is a high-level signal, the second clock signal ck2 is a high-level signal, the on-off conditions of the transistors in the circuit are shown in fig. 5, the first transistor M1 and the second transistor M2 are turned off under the action of the high-level signal of the first clock signal ck1, the first node NET1 is kept at a high level, and the sixth transistor M6, the twelfth transistor M12 and the thirteenth transistor M13 are turned off; since the second clock signal ck2 is a high level signal, the fourth transistor M4 is turned off, the second node NET2 is kept at a high level, the fifth transistor M5 is turned off, and the output end En of the driving circuit keeps outputting a low level signal. The third node NET3 is kept at a low level, and the third transistor M3 is turned on. Both the first node NET1 and the second node NET2 are kept high, and the seventh transistor M7 and the eighth transistor M8 are turned off.
Stage t 3: the trigger signal st is a high-level signal, the first clock signal ck1 is a high-level signal, the second clock signal ck2 is a low-level signal, the on-off conditions of the transistors in the circuit are shown in fig. 6, the first clock signal ck1 is a high level, and the first transistor M1 and the second transistor M2 are turned off; the fourth transistor M4 is turned on by a low-level signal of the second clock signal ck2, the third node NET3 maintains a low level at the previous moment, the third transistor M3 is turned on by a low-level signal of the third node NET3, a low-level signal of the second clock signal ck2 is written into the second node NET2, so that the fifth transistor M5 is turned on, a high-level signal input from the first level signal input terminal VDD is written into the output terminal En of the driving circuit, and the output terminal En of the driving circuit outputs a high-level signal; the tenth transistor M10 is turned on by a low level signal of the third node NET3, the eleventh transistor M11 is turned on by a low level signal of the second clock signal CKE2, a high level signal inputted from the first level signal input terminal VDD is written into the first node NET1, and the sixth transistor M6, the ninth transistor M9, the twelfth transistor M12, and the thirteenth transistor M13 are turned off; the seventh transistor M7 is turned off by a low-level signal of the first node NET1, the eighth transistor M8 is turned on by a low-level signal of the second node NET2, a high-level signal of the first clock signal ck1 is written into the drain of the sixth transistor M6, and a voltage difference between the drain and the source of the sixth transistor M6 is 0.
Stage t 4: the trigger signal st is a high-level signal, the first clock signal ck1 is a high-level signal, the second clock signal ck2 is a high-level signal, the on-off state of each transistor in the circuit is as shown in fig. 7, the fourth transistor M4 is turned off under the action of the high-level signal of the second clock signal ck2, the second node NET2 keeps a low level, the eleventh transistor M11 is turned off under the action of the high-level signal of the second clock signal ck2, the first node NET1 keeps a high level, the third node NET3 keeps a low level, the on-off states of other transistors are the same as the previous stage, the high-level signal input by the first-level signal input end VDD is written into the output end En of the driving circuit, and the voltage difference between the source and the drain of the sixth transistor M6 is 0.
Stage t 5: the trigger signal st is a high-level signal, the first clock signal ck1 is a low-level signal, the second clock signal ck2 is a high-level signal, the on-off conditions of the transistors in the circuit are shown in fig. 8, the first transistor M1 is turned on under the action of the low-level signal of the first clock signal ck1, the high-level signal of the trigger signal st is written into the first node NET1, and the sixth transistor M6 is turned off; the second transistor M2 is turned on by a low level signal of the first clock signal ck1, a low level signal input from the second level signal input terminal VEE is written into the third node NET3, the second node NET2 maintains a low level, the fifth transistor M5 is turned on, the output terminal En of the driving circuit is written into a high level signal input from the first level signal input terminal VDD, the eighth transistor M8 is turned on by a low level signal of the second node NET2, a low level signal of the first clock signal ck1 is written into the drain of the sixth transistor M6, and a voltage difference between the source and the drain of the sixth transistor M6 is a difference between the high level signal and the low level signal.
Stage t 6: the trigger signal st is a high-level signal, the first clock signal ck1 is a high-level signal, the second clock signal ck2 is a high-level signal, the on-off condition of each transistor in the circuit is shown in fig. 9, the first transistor M1 is turned off under the action of the high-level signal of the first clock signal ck1, the first node NET1 keeps a high level, the second transistor M2 is turned off under the action of the high-level signal of the first clock signal ck1, the third node NET3 keeps a low level, the second clock signal ck2 is a high level, the fourth transistor M4 is turned off, the second node NET2 keeps a low level, the fifth transistor M5 is turned on, the high-level signal input at the first-level signal input terminal VDD is written into the output terminal En of the driving circuit, and the source of the sixth transistor M6 is a high level. The eighth transistor M8 is turned on by the low level signal of the second node NET2, the high level signal of the first clock signal ck1 is written into the drain of the sixth transistor M6, and the voltage difference between the source and the drain of the sixth transistor M6 is 0.
At the stage t7, when the trigger signal st is a low level signal, the first clock signal ck1 is a high level signal, and the second clock signal ck2 is a low level signal, the on-off conditions of the transistors in the circuit are as shown in fig. 10, the first clock signal ck1 is a high level signal, the first transistor M1 and the second transistor M2 are turned off, the first node NET1 keeps a high level, the sixth transistor M6 is turned off, the third node NET3 keeps a low level, and the third transistor M3 is turned on; the fourth transistor M4 is turned on under the action of the low-level signal of the second clock signal ck2, the low-level signal of the second clock signal ck2 is written into the second node NET2 through the turned-on third transistor M3 and the turned-on fourth transistor M4, the fifth transistor is turned on, and the output end En of the driving circuit is written into the high-level signal input by the first level signal input end VDD; the tenth transistor M10 is turned on by a low-level signal of the third node NET3, the eleventh transistor M11 is turned on by a low-level signal of the second clock signal ck2, a high-level signal input from the first level signal input terminal VDD is written into the first node NET1, the high voltage of the first node NET1 is further stabilized, the seventh transistor M7 is turned off by a high-level signal of the first node NET1, the eighth transistor M8 is turned on by a low-level signal of the second node NET2, the high-level signal of the first clock signal ck1 is written into the drain of the sixth transistor M6, and the voltage difference between the drain and the source of the sixth transistor M6 is made 0.
Stage t 8: the trigger signal st is a low-level signal, the first clock signal ck1 is a high-level signal, the second clock signal ck2 is a high-level signal, the on-off conditions of the transistors in the circuit are shown in fig. 11, the fourth transistor M4 is turned off under the action of the high-level signal of the second clock signal ck2, and the second node NET2 keeps a low level; the first node NET maintains a high level, and the third node NET3 maintains a level; the on/off states of the other transistors are the same as the previous stage, the output end En of the driving circuit writes the high level signal input by the first level signal input end VDD, and the turned-on eighth transistor M8 writes the high level signal of the first clock signal ck1 into the drain of the sixth transistor M6, so that the voltage difference between the drain and the source of the sixth transistor M6 is 0.
Stage t 9: the trigger signal st is a low-level signal, the first clock signal ck1 is a low-level signal, the second clock signal ck2 is a high-level signal, the on-off conditions of the transistors in the circuit are shown in fig. 12, the first transistor M1 is turned on under the action of the low-level signal of the first clock signal ck1, the low-level signal of the trigger signal st is written into the first node NET1, the sixth transistor M6 and the ninth transistor M9 are turned on, the second clock signal ck2 is a high-level signal, the fourth transistor M4 is turned off, the high-level signal input from the first level signal input end VDD is written into the second node NET2 by turning on the ninth transistor M9, and the fifth transistor M5 is turned off; under the action of the low level signal of the first node NET1, the seventh transistor M7 is also turned on, the output end En of the driving circuit outputs a low level signal (the low level signal input by the second level signal input end VEE charges the source of the sixth transistor M6, the potential of the source of the sixth transistor M6 gradually decreases until the difference between the gate and the source of the sixth transistor is equal to the turn-on voltage Vth (threshold voltage), and the source voltage of the sixth transistor M6, that is, the voltage of the output end En of the specific driving circuit is the sum of the absolute value of the voltage of the low level signal of the second level signal input end VEE and the turn-on voltage Vth); the second transistor M2 is turned on by a low level signal of the first clock signal ck1, a low level signal inputted from the second level signal input terminal VEE is written into the third node NET3, the tenth transistor M10 is turned on, the eighth transistor M8 is turned off by a high level signal of the second node NET2, and the twelfth transistor M12 and the thirteenth transistor M13 are turned on because the first node NET1 is at a low level.
Stage t 10: the trigger signal st is a low level signal, the first clock signal ck1 is a high level signal, the second clock signal ck2 is a high level signal, the on/off state of each transistor in the circuit is as shown in fig. 13, because the first clock signal ck1 is a high level signal, the first transistor M1 is turned off and the second transistor M2 is turned off, the first node NET1 keeps a low level, the second node NET2 writes a high level signal input by the first level signal input terminal VDD, the twelfth transistor M12 and the thirteenth transistor M13 are turned on under the action of the low level signal of the first node NET1, the high level signal of the first clock signal ck1 is written into the third node NET3, and the third transistor M3 and the tenth transistor M10 are turned off under the action of the high level signal of the third node NET3, the on-off states of other transistors are the same as the last time period, and the output voltage of the output end En of the driving circuit is the sum of the voltage of the low-level signal and the absolute value of the starting voltage Vth.
Stage t 11: the trigger signal st is a low-level signal, the first clock signal ck1 is a high-level signal, the second clock signal ck2 is a low-level signal, the on-off conditions of the transistors in the circuit are shown in fig. 14, the low-level signal of the first node NET1 changes from the high-level signal to the low-level signal with the second clock signal ck2 under the coupling action of the second capacitor C2, the potential of the first node NET1 is pulled down to be lower, the sixth transistor is more sufficiently turned on, so that the low-level signal input by the second-level signal input end VEE is written into the output end En of the driving circuit, the output end En of the driving circuit outputs the low-level signal, and the on-off states of other transistors are the same as the on-off state in the last time.
Stage t 12: the trigger signal st is a low level signal, the first clock signal ck1 is a high level signal, the second clock signal ck2 is a high level signal, the on-off state of each transistor in the circuit is as shown in fig. 15, the fourth transistor M4 is turned off as the second clock signal ck2 changes from the low level signal to the high level signal, the low level signal of the first node NET1 changes to the original potential height under the coupling action of the second capacitor C2, the low level signal of the second level signal VEE is written into the output end En of the driving circuit in the previous time period, the voltage between the source and the gate of the sixth transistor M6 is smaller than the absolute value of the starting voltage Vth, so the sixth transistor M6 is turned off, the seventh transistor M7 is also turned off, and the output end En of the driving circuit keeps at the low level.
The subsequent phases repeat phases 9-12 until the next high phase of the trigger signal. According to the embodiment of the invention, the voltage difference control unit is introduced, so that the voltage difference between the input end and the output end of the second holding unit is changed but not kept constant, and the problem that when the output end of the driving circuit outputs the first level signal for a long time, the constant voltage is borne between the input end and the output end of the second holding unit for a long time, so that the circuit characteristic drifts, the abnormal output of the driving circuit is caused, and the display panel cannot work normally is avoided.
Fig. 16 is a schematic structural diagram of a display device according to an embodiment of the present invention, where the display device 210 includes a driving circuit 220 according to any embodiment of the present invention. As shown in fig. 16, the display device 210 includes a display region 212 and a non-display region 211, the driving circuit 220 is located in the non-display region 211, and the output end of the driving circuit 220 can be connected to a plurality of gate scan lines 221 located in the display region 212 in the display device 210 in a one-to-one correspondence manner, for charging the gate scan lines, so as to drive the pixels in the display region to emit light for display. The display device may be one of a mobile phone, a tablet computer, and a virtual reality apparatus. The display device provided by the embodiment of the present invention includes the driving circuit in the above embodiment, and therefore, the display device provided by the embodiment of the present invention also has the beneficial effects described in the above embodiment, and details are not described herein again.
Fig. 17 is a flowchart of a driving method of a driving circuit according to an embodiment of the present invention, where the driving method may be used to drive the driving circuit according to any embodiment of the present invention, and specifically includes the following steps:
step 310, in a pull-up output stage, the second holding unit is turned off, the first holding unit is turned on, and the driving circuit outputs a first level signal; the voltage difference control unit is turned on or off to control a change in the voltage difference between the input terminal and the output terminal of the second holding unit.
And 320, in a pull-down output stage, the first holding unit is turned off, the second holding unit and the differential pressure control unit are turned on, and the driving circuit outputs a second level signal.
The first level signal may be a high level signal, and the second level signal may be a low level signal.
It should be noted that, the driving method of the driving circuit provided in the embodiment of the present invention is used for driving the driving circuit provided in any embodiment of the present invention, and has the beneficial effects described in the above embodiments, and details are not repeated herein.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (11)
1. A driver circuit, comprising:
the control end of the driving signal input unit is connected with the first clock signal input end of the driving circuit, the input end of the driving signal input unit is connected with the trigger signal input end of the driving circuit, and the output end of the driving signal input unit is connected with the first node;
a first control unit, a first control end and a second control end of which are respectively connected with a first clock signal input end and a second clock signal input end of the driving circuit, an input end of which is connected with a second level signal input end of the driving circuit, and an output end of which is connected with a second node, and is used for controlling the potential of the second node;
a second control unit, an input end of which is connected with the second clock signal input end, and an output end of which is connected with the first node, and is used for controlling the electric potential of the first node;
the voltage difference control circuit comprises a first holding unit, a second holding unit and a voltage difference control unit which are connected in series, wherein the input end of the first holding unit is connected with the first level signal input end of the driving circuit, and the output end of the first holding unit is connected with the output end of the driving circuit; the input end of the second holding unit is connected with the output end of the differential pressure control unit, and the output end of the second holding unit is connected with the output end of the driving circuit; a first input end of the differential pressure control unit is connected with a second level signal input end of the driving circuit, a second input end of the differential pressure control unit is connected with a first clock signal input end or a second clock signal input end of the driving circuit, a first control end of the differential pressure control unit is connected with the first node, a second control end of the differential pressure control unit is connected with the second node, a control end of the first holding unit is connected with the second node, and a control end of the second holding unit is connected with the first node; the voltage difference control unit inputs signals through a second input end, a first control end and a second control end to control the voltage difference change between the input end and the output end of the second holding unit.
2. The driving circuit of claim 1, wherein the differential pressure control unit further comprises a second input terminal, a first control terminal, and a second control terminal, the second input terminal of the differential pressure control unit is connected to the first clock signal input terminal, the first control terminal of the differential pressure control unit is connected to the first node, and the second control terminal of the differential pressure control unit is connected to the second node.
3. The driving circuit of claim 1, wherein the differential pressure control unit further comprises a second input terminal, a first control terminal, and a second control terminal, the second input terminal of the differential pressure control unit is connected to the second clock signal input terminal, the first control terminal of the differential pressure control unit is connected to the first node, and the second control terminal of the differential pressure control unit is connected to the second node.
4. The drive circuit according to claim 1, wherein the drive signal input unit includes a first transistor, the first control unit includes a second transistor, a third transistor, a fourth transistor, a twelfth transistor, a thirteenth transistor, and a first capacitor, the second control unit includes a second capacitor, the first holding unit includes a fifth transistor, the second holding unit includes a sixth transistor, and the voltage difference control unit includes a seventh transistor and an eighth transistor;
the grid electrode of the first transistor is connected with the first clock signal input end, the first pole of the first transistor is connected with the trigger signal input end, and the second pole of the first transistor is connected with the first node;
a gate of the second transistor is connected to the first clock signal input terminal, a second pole of the second transistor is connected to the second level signal input terminal, and a first pole of the second transistor is connected to a gate of the third transistor;
a first pole of the third transistor is connected with the second clock signal input end, a second pole of the third transistor is connected with a first pole of the first capacitor, and a second pole of the first capacitor is connected with a grid electrode of the third transistor;
the grid electrode of the fourth transistor is connected with the second clock signal input end, the first pole of the fourth transistor is connected with the first pole of the first capacitor, and the second pole of the fourth transistor is connected with the grid electrode of the fifth transistor;
a gate of the twelfth transistor is connected to the first node, a first pole of the twelfth transistor is connected to the gate of the third transistor, and a second pole of the twelfth transistor is connected to the first pole of the thirteenth transistor;
a gate of the thirteenth transistor is connected to the first node, and a second pole of the thirteenth transistor is connected to the first clock signal input terminal;
a second pole of the fifth transistor is connected with the first level signal input end, and a first pole of the fifth transistor is connected with the output end of the driving circuit;
the grid electrode of the sixth transistor is connected with the first electrode of the second capacitor, the second electrode of the sixth transistor is connected with the output end of the driving circuit, and the first electrode of the sixth transistor is connected with the second electrode of the seventh transistor;
a second pole of the second capacitor is connected with the second clock signal input end;
the grid electrode of the seventh transistor is connected with the first node, and the first pole of the seventh transistor is connected with the second level signal input end;
a gate of the eighth transistor is connected to the second node, and a first electrode of the eighth transistor is connected to the first clock signal input terminal or the second clock signal input terminal; the second pole is connected to the second pole of the seventh transistor.
5. The drive circuit according to claim 4, wherein the first control unit further includes a ninth transistor;
and the grid electrode of the ninth transistor is connected with the first node, the second pole of the ninth transistor is connected with the first level signal input end, and the first pole of the ninth transistor is connected with the second node.
6. The driving circuit according to claim 4, wherein the first control unit further comprises a third capacitor, a first pole of the third capacitor is connected to the first level signal input terminal, and a second pole of the third capacitor is connected to the gate of the fifth transistor.
7. The driving circuit according to claim 4, further comprising a voltage stabilization unit including tenth and eleventh transistors;
a gate of the tenth transistor is connected to a gate of the third transistor, a second pole of the tenth transistor is connected to the first level signal input terminal, and a first pole of the tenth transistor is connected to the second pole of the eleventh transistor;
a gate of the eleventh transistor is connected to the second clock signal input terminal, and a first electrode is connected to the first node.
8. The driving circuit according to claim 1, wherein the first level signal input terminal inputs a high level signal, and the second level signal input terminal inputs a low level signal.
9. A drive circuit according to claim 4, each transistor being a P-type transistor.
10. A display device comprising the driver circuit according to any one of claims 1 to 9.
11. A driving method of a driving circuit for driving the driving circuit according to any one of claims 1 to 9, comprising:
in the pull-up output stage, the second holding unit is turned off, the first holding unit is turned on, and the driving circuit outputs a first level signal; the voltage difference control unit is switched on or switched off to control the voltage difference between the input end and the output end of the second holding unit to change;
in the pull-down output stage, the first holding unit is turned off, the second holding unit and the differential pressure control unit are turned on, and the driving circuit outputs a second level signal.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101673582A (en) * | 2009-10-28 | 2010-03-17 | 友达光电股份有限公司 | Shift cache circuit |
| CN104021764A (en) * | 2014-06-18 | 2014-09-03 | 上海和辉光电有限公司 | Light-emitting signal control circuit |
| CN105989798A (en) * | 2015-02-09 | 2016-10-05 | 上海和辉光电有限公司 | Bidirectional scanning signal emission circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100705628B1 (en) * | 2003-12-30 | 2007-04-11 | 비오이 하이디스 테크놀로지 주식회사 | Driving circuit of Liquid Crystal Display |
| KR101545697B1 (en) * | 2008-08-29 | 2015-08-21 | 삼성디스플레이 주식회사 | liquid crystal display |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101673582A (en) * | 2009-10-28 | 2010-03-17 | 友达光电股份有限公司 | Shift cache circuit |
| CN104021764A (en) * | 2014-06-18 | 2014-09-03 | 上海和辉光电有限公司 | Light-emitting signal control circuit |
| CN105989798A (en) * | 2015-02-09 | 2016-10-05 | 上海和辉光电有限公司 | Bidirectional scanning signal emission circuit |
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