CN105981170A - 具有半导体芯片端子的dc-dc转换器 - Google Patents

具有半导体芯片端子的dc-dc转换器 Download PDF

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Publication number
CN105981170A
CN105981170A CN201580007418.8A CN201580007418A CN105981170A CN 105981170 A CN105981170 A CN 105981170A CN 201580007418 A CN201580007418 A CN 201580007418A CN 105981170 A CN105981170 A CN 105981170A
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Prior art keywords
terminal
chip
fet
pad
lead
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CN201580007418.8A
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CN105981170B (zh
Inventor
奥斯瓦尔多·乔治·洛佩斯
乔纳森·阿尔梅里亚·努吉尔
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Texas Instruments Deutschland GmbH
Texas Instruments Inc
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Texas Instruments Inc
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Priority claimed from US14/173,147 external-priority patent/US9184121B2/en
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Priority to CN201911107083.3A priority Critical patent/CN110911377B/zh
Publication of CN105981170A publication Critical patent/CN105981170A/zh
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  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Dc-Dc Converters (AREA)

Abstract

在所描述实例中，一种电力供应***(200)具有QFN引线框架，所述QFN引线框架具有引线及垫(201)。面向电路板的垫表面具有凹入的部分，所述凹入部分具有深度(270)及适于并排附接同步FET(210)半导体芯片及控制FET(220)半导体芯片的轮廓。所述控制FET(220)的输入端子(220a)及所述同步FET(210)的接地输出端子(210a)与所述垫(201)切换节点端子的未凹入部分共面，使得所有端子可直接附接到电路板的触点。驱动器与控制件芯片垂直堆叠到相对垫表面且囊封在封装化合物中。

Description

具有半导体芯片端子的DC-DC转换器
本发明一般来说涉及半导体装置及工艺，且更特定来说，涉及薄经封装同步降压转换器的结构及制作方法。
背景技术
在受欢迎电力供应电路系列当中具有用于将一个DC电压转换为另一DC电压的电力切换装置。特定来说，具有两个电力MOS场效应晶体管(FET)的电力块适于新兴的电力递送要求，所述两个电力MOSFET串联连接且通过共同切换节点而耦合在一起。此组合件也称作半桥。当添加有调节驱动器与控制器时，所述组合件被称为供电级，或更常见地，所述组合件被称为同步降压转换器。在同步降压转换器中，控制FET芯片(其也称作高侧切换器)连接在供应电压VIN与LC输出滤波器之间，且同步(sync)FET芯片(其也称作低侧切换器)连接在LC输出滤波器与接地电位之间。控制FET芯片的栅极及同步FET芯片的栅极连接到半导体芯片，所述半导体芯片包含用于转换器的驱动器及控制器的电路。所述芯片也连接到接地电位。
对于许多现在的电力切换装置，电力MOSFET的芯片及驱动器与控制器IC的芯片水平地并排组装为个别组件。每一芯片通常附接到金属引线框架的矩形形状垫或正方形形状垫。所述垫由作为输入/输出端子的引线环绕。在其它电力切换装置中，电力MOSFET芯片及驱动器与控制器IC水平地并排组装在单个引线框架垫上，所述引线框架垫又在全部四个侧上由用作装置输出端子的引线环绕。所述引线是常见形状的而不具有悬臂延伸部，且是以四方扁平无引线(QFN)或小轮廓无引线(SON)装置的方式而布置。从芯片到引线的电连接可由接合线提供，所述接合线将显著寄生电感引入(由于接合线的长度及电阻)到电力电路中。
在一些最近引入的先进组装中，夹子替代了许多连接线。这些夹子较宽且由厚金属制成，且因此引入最小寄生电感。每一组合件通常封装在塑料囊封中，且采用经封装组件作为用于电力供应***的板组合件的离散构建块。
在其它最近引入的方案中，控制FET芯片及同步FET芯片彼此上下垂直地组装为引线框架垫上方的堆叠。控制FET芯片或同步FET芯片(两者中具有物理上较大面积的一者)附接到引线框架垫。夹子提供到切换节点及堆叠顶部的连接。不管物理大小如何，由于考虑到工作循环及传导损失，因此与控制FET芯片的作用区相比，同步FET芯片需要较大作用区。当同步芯片及控制芯片两者均经组装源极向下时，将较大(物理上及作用区两者均较大)同步芯片组装到引线框架垫上，且较小(物理上及作用区两者均较小)控制芯片使其源极系接到同步芯片的漏极，从而形成切换节点，且将较小控制芯片的漏极连接到输入供应器VIN。将第一夹子连接到两个芯片之间的切换节点。将堆叠顶部上的经伸长第二夹子系接到输入供应器VIN。所述垫处于接地电位且用作操作上所产生热量的散热器(spreader)。驱动器与控制件IC芯片接近芯片堆叠及夹子而水平地并排组装且通过接合线与FET栅极及引线框架引线连接。由于夹子及线接合的形式及材料，因此夹子及线接合具有电阻及电感，所述电阻及电感促成***的寄生效应。
图1A中展示典型转换器(通常标示为100)。控制MOS场效应晶体管(FET)110堆叠于同步(sync)MOSFET 120上。此实例性模块的控制FET芯片110相对于同步FET芯片120具有较小面积。QFN金属引线框架具有矩形扁平垫101，矩形扁平垫101用作输出端子且被指定为封装的散热器。引线102a及102b沿垫的两个相对侧以线性方式定位。FET芯片的堆叠是依据所谓的源极向下配置而实现。同步FET 120的源极通过焊料层121而焊接到引线框架垫101。低侧夹子140(其通过焊料层122焊接到同步FET 120的漏极上)通过焊料层111而附接控制FET 110的源极。因此，低侧夹子140用作转换器的切换节点端子。高侧夹子160通过焊料层112而连接到控制FET 110的漏极。高侧夹子160附接到引线框架的引线102b，因此，高侧夹子160连接到输入供应器VIN。低侧夹子140与高侧夹子160是成套放置的。驱动器与控制器芯片130通过焊料层132而附接到垫101。线133提供芯片端子与FET栅极端子(110b、120b、120d)的连接。图1的转换器具有1.5mm的高度191以及拥有6mm的长度192及5mm的宽度193的矩形占用面积。在具有较小芯片的其它已知转换器中，可将驱动器芯片放置在第二夹子的顶部中以节省板面积，但接合线不得不过度的长，使得在囊封工艺期间存在线弯曲(wire sweep)及电短路的显著风险。图1B展示沿标记为1B-1B的假想线的剖面。
在另一最近引入的电力***中，驱动器与控制件芯片被包含在垂直堆叠中在第二夹子的顶部上。此组合件结构节省引线框架垫及印刷电路板的有效面积，但具有极长下坡式接合线的风险，且因此在囊封工艺期间具有线弯曲及后续电短路的风险。
发明内容
在所描述实例中，DC-DC转换器使用具有引线及垫的QFN引线框架。面向电路板的垫表面具有凹入的部分，所述凹入部分具有深度及适于并排附接同步FET芯片及控制FET芯片的轮廓。所述控制FET的输入端子及所述同步FET的接地输出端子与所述垫的未凹入部分共面，所述垫是系接到切换节点端子。由于所述共面性，因此所有端子可直接且同时附接到电路板的触点。所述直接附接显著减小热电阻且改进到电路板的散热片的热耗散。因此，增强(超过1MHz)转换器的操作频率。驱动器与控制件芯片垂直地堆叠到相对垫表面且囊封在封装化合物中。
在制作电力供应***的方法的所描述实例中，QFN引线框架的垫具有第一表面及第二表面。已预先压印所述第一垫表面以具有凹入的部分，所述凹入部分具有深度及适于附接半导体芯片的轮廓。驱动器与控制件芯片被附接到所述第二垫表面、被线接合到相应引线且被囊封在封装化合物中，所述封装化合物使所述第一垫表面不囊封。第一FET芯片(同步FET芯片)以其漏极端子附接到所述第一垫表面的所述凹入部分，使得所述第一FET芯片的源极端子及栅极端子与所述第一垫表面的未凹入部分共面。同样，第二FET芯片(控制FET芯片)以其源极端子附接到所述第一垫表面的所述凹入部分，使得所述第二FET芯片的漏极端子及栅极端子与所述第一垫表面的所述未凹入部分共面。
附图说明
图1A是常规经封装DC-DC同步降压转换器的透视俯视图，其中驱动器与控制器芯片邻近于引线框架垫上的经垂直堆叠FET芯片及两个夹子而组装。
图1B是图1A的常规经封装经堆叠FET芯片及夹子的横截面。
图2A是根据实例性实施例的经封装DC-DC同步降压转换器的透视俯视图，其中驱动器与控制器芯片附接到引线框架垫的顶侧且封装化合物囊封芯片及线接合。
图2B是图2A的DC-DC转换器的透视仰视图，其中两个邻近FET芯片附接到引线框架垫的底侧且共面的FET端子不囊封以可附接到电路板。
图3是图2A及2B的经封装转换器的横截面，其中邻近FET芯片的端子附接到电路板的相应触点。
图4显示图2A及2B的同步降压转换器的电路图，其识别因免除夹子而产生的电寄生效应的消除。
图5是经冲压且经压印引线框架的透视仰视图，其展示相对于引线凹入的垫部分及其余垫部分。
图6是在芯片已附接到引线框架垫的顶侧之后将驱动器与控制件芯片的端子线接合到相应引线的透视俯视图。
图7是在囊封驱动器与控制件芯片之后的引线框架的透视仰视图，其显示引线框架垫的经预先压印凹部部分。
图8是图7在沉积用于附接同步FET芯片及控制FET芯片的粘合剂聚合物层之后的透视仰视图。
具体实施方式
第US 14/173,147号申请案描述相关标的物且特此以引用的方式并入。
申请人认识到，在新应用(例如汽车产品)中采用DC-DC转换器的持续趋势加速了朝向小型化、较低电力、较高频率及经减小成本的长期推进。此趋势的征兆为推动减小转换器的高度及减小电寄生效应。
申请人进一步认识到，当可消除常规转换器中所使用的金属夹子而不消除所述夹子的功能时，可实现减小DC-DC转换器的高度的阶梯功能改进。当申请人发现一种用以通过将同步FET芯片及控制FET芯片并排组装在引线框架垫的经预先压印凹部中来消除两个夹子同时保有夹子的功能的方法时，申请人解决了在减小电寄生电阻及电感的同时减小产品的高度的问题。作为意料之外的益处，结果证明：直接附接电路板的FET端子的新能力不仅减小转换器的寄生效应而且大体上增加从作用转换器操作到电路板的散热片中的热耗散。因此，转换器的电力输送及操作频率得以改进。
图2A及2B是作为实例性实施例的电力供应模块(通常标示为200)的透视图，图2A为俯视图，图2B为仰视图。出于解释原因，模块200展示为具有透明囊封290。优选实际囊封使用适于传递模塑技术的黑色环氧树脂制剂。图2A及2B的实例性模块具有介于0.7mm到0.8mm的范围内的厚度291以及拥有4.8mm的模块长度292及3.0mm的宽度293的矩形占用面积。其它垫可为正方形形状的。
经由透明囊封可见通常适于四方扁平无引线(QFN)类型模块及小轮廓无引线(SON)类型模块的金属引线框架。所述引线框架包含矩形垫201以及引线202及203。图2B中可见的垫表面是第一表面201a，及图2A中可见的垫表面是第二表面201b。引线框架优选地由铜或铜合金制成。替代金属选择包含铝、铁镍合金及KovarTM。引线框架的两个表面可经制备以例如通过粗糙表面而促进环氧树脂粘合剂附接。当其它实施例可使用焊料作为附接物时，引线框架表面制备可包含锡层或者镍、钯及金的镀敷层序列。此外，至少一个表面可具有金属层，所述金属层经沉积以例如通过银镀敷层而增强导热性。用于图2A及2B中所展示的实例性实施例的开始金属的优选厚度介于0.2mm到0.4mm的范围内，但其它实施例可使用较厚或较薄引线框架金属。从低成本及批量处理的角度来看，优选地以薄片金属开始并通过冲压或蚀刻将引线框架制作为条带，且在囊封工艺之后通过对所述条带进行修整而将用于模块的引线框架单个化。将垫201电系接到电力供应***的切换节点端子VSW。
如图2B中所展示，第一垫表面201a具有部分201c，部分201c相对于部分201d偏离一阶梯270。此外，部分201c具有适于附接半导体芯片的轮廓(长度271及宽度272)。在引线框架的制作工艺期间优选地通过压印而实现使垫偏离的工艺。或者，可使用蚀刻工艺。举例来说，可执行化学蚀刻工艺，使得仅不受氧化金属或极薄金层保护的那些表面(例如铜或铝)被侵蚀。
在图2B的实例中，两个半导体场效应晶体管(FET)的芯片被附接到引线框架垫的凹入部分201c。第一芯片210为漏极向下FET，其表示同步降压转换器的同步FET(低侧FET)。第二芯片220为源极向下FET，其表示同步降压转换器的控制FET(高侧FET)。
图2B展示同步FET(低侧FET)芯片210，其中FET芯片的漏极端子附接到第一垫表面201a的凹入部分201c。在此说明中，同步芯片210被称为第一FET芯片。对于图2B中所展示的实施例，第一芯片210具有～3.5×2.84mm的大小及～0.1mm的厚度。对于其它实施例，芯片大小及芯片厚度可具有显著较大或较小值。优选地通过传导性粘合剂(环氧树脂)层211而实现附接，传导性粘合剂(环氧树脂)层211可被聚合(被固化)；而替代方案为z轴传导性聚合物。粘合剂层的优选厚度为至少25μm。传导性粘合剂提供高导热性以用于散热，这是因为传导性粘合剂填充有金属(优选地，银)粒子。优选地，传导性粘合剂对于装置200的所有附接工艺均相同，使得可同时针对所有附接通过单个工艺而执行聚合工艺。在附接之后，源极端子210a及栅极端子210b与第一垫表面的未凹入部分的表面201a共面。在翻动成品装置之后，源极端子210a可用于被附接(通过焊料或传导性粘合剂)到电路板上的接地输出端子VOUT(PGND)。此附接动作还将同步FET栅极端子210b系接到板上的相应端子。
邻近于第一FET芯片210，图2B展示控制FET(高侧FET)芯片220，其中FET芯片的源极端子附接到第一垫表面201a的凹入部分201c。在此说明中，控制FET芯片220被称为第二FET芯片。对于图2B中所展示的实施例，第二芯片220具有～2.5×1.8mm的大小及0.1mm的厚度。对于其它实施例，芯片大小及芯片厚度可具有显著较大或较小值。优选地通过传导性粘合剂(环氧树脂)层221而实现附接，传导性粘合剂(环氧树脂)层221可被聚合(被固化)；而替代方案为z轴传导性聚合物。粘合剂层的优选厚度为至少25μm。传导性粘合剂提供高导热性以用于散热，这是因为传导性粘合剂填充有金属(优选地，银)粒子。在附接之后，漏极端子220a及栅极端子220b与第一垫表面的未凹入部分的表面201a共面。在翻动成品装置之后，漏极端子220a可用于被附接(通过焊料或传导性粘合剂)到电路板上的输入端子VIN。此附接动作还将控制FET栅极端子210b系接到板上的相应端子。
如图2A中所展示，集成电路(IC)芯片230被附接到引线框架垫201的第二表面201b，从而为电力供应***提供驱动器与控制器功能。芯片230优选地通过～25μm厚度的传导性粘合剂(环氧树脂)层231而附接到垫201的第二表面201b，传导性粘合剂(环氧树脂)层231可被聚合(被固化)；而替代方案为z轴传导性聚合物。传导性粘合剂提供高导热性以用于将热量从芯片230散布到垫201，这是因为传导性粘合剂填充有金属(优选地，银)粒子。芯片230可为矩形且可为0.2mm厚，或芯片230可为正方形形状的。其它实施例可具有较小或较大且较厚或较薄的芯片。如图2A中所展示，芯片230的端子线接合到相应引线203。接合线233的优选直径为～25μm，但可较小或较大。此接合配置暗指所谓的下坡式接合操作，下坡式接合操作在模塑操作期间需要谨慎以避免线弯曲以及线与芯片230的相关触及，但图2A中的接合由于经伸长线及小高度差而实际上仅具有低风险。
图3展示关于其中转换器的薄度非常宝贵或其中必须使转换器的冷却最大化以用于实现高操作频率的应用的实例性实施例的技术优点。在此实施例中，驱动器与控制器芯片如图2A中组装于引线框架的顶部上，且封装的高度介于0.7mm到0.8mm的范围内。低侧FET 210及高侧FET 220两者均附接到引线框架垫的凹入部分的表面201a。在垫对面的FET端子210a及220a与垫表面的未凹入部分的表面201a共面。端子210a及220a是暴露的，因此端子210a及220a可易于分别附接到电路板(PC板)300的垫310及320。同时，垫的未凹入部分及引线附接到板300的垫301。可通过传导性聚合物或通过焊料而执行附接。如图3指示，这些板垫中的至少几个板垫经扩展为散热器或被连接到PC板中的散热片。FET端子到电路(PC)板的直接附接以及PC板中的散热器及散热片的有效冷却允许良好冷却，且因此允许FET的低结温度以及转换器的高效率及高频率操作(1MHz及1MHz以上)。
根据图2A及2B而组装同步降压转换器减小常规组合件中普遍的寄生电感。图4具体说明相对于图1中所展示的常规组合件的改进。电改进源自省略常规组合件的垂直堆叠中所需的两个夹子。
通过消除高侧夹子(在图1A中标示为160)，高侧FET 210的漏极端子220a被直接安装到板的VIN端子330上。高侧夹子电阻被消除，且高侧源极电阻几乎可以忽略。因此，避免了来自所省略夹子的～0.5mΩ的寄生电阻及～0.6nH的寄生电感。输入端子VIN的寄生电阻及电感已实际上消失。
通过消除低侧夹子(在图1A中标示为140)，低侧FET的源极端子210a被直接安装到板的接地VOUT端子310上。低侧夹子电阻被消除，且低侧源极电阻几乎可以忽略。因此，避免了来自所省略夹子的～0.5mΩ的寄生电阻及～0.6nH的寄生电感。输出端子VOUT的寄生电阻及电感已实际上消失。
同时，垫的未凹入部分201a附接到板300的垫301。因此，引线框架的垫系接到切换节点端子VSW(在图4中标示为301)。连接的电阻及电感较小，例如分别为～0.2mΩ及～0.45nHy。优选地，可使用相同附接材料(传导性粘合剂或焊料)用于端子的附接。以相同方式，通过低电阻连接将引线203附接到板垫303。
另一实施例是制作电力供应DC-DC转换器***的方法，其中组装两个半导体芯片，使得两个芯片的端子可直接附接到电路板。与其它技术相比，所述芯片被嵌入引线框架垫的外部凹部中，所述引线框架垫还用作切换节点端子。以此方式，消除了常规两个夹子，且减少了工艺步骤的数目，因此所述方法与其它技术相比为低成本的且产生具有小高度及小面积的装置。
图5、6及7展示组装工艺流程的一些步骤。工艺流程在图5中通过提供引线框架而开始，所述引线框架通常适用于QFN及SON装置。图5的视图展示引线框架的第一表面201a。图6中展示第二表面201b。图5的实例性引线框架具有矩形垫201。对于其它装置，引线框架可具有正方形形状垫。垫201将系接到切换端子VSW。引线框架优选地由铜或铜合金制成；但替代金属选择包含铝、铁镍合金及KovarTM。引线框架的两个表面可经制备以(例如)通过镍、钯及金的镀敷层序列而促进焊料附接。引线框架金属的开始厚度介于0.2mm到0.4mm的范围内。优选地以薄片金属开始并通过冲压或蚀刻将引线框架制作为条带，且在囊封工艺之后通过对所述条带进行修整而将用于模块的引线框架单个化。图4的俯视图展示第二表面201b。第一表面201a打算保持暴露在装置封装外部。
第一垫表面201a具有部分201c，部分201c相对于部分201d偏离一阶梯270。若将部分201d的区域用作参考平面，则部分201c的区域相对于部分201d的区域显现为凹入的。此外，部分201c具有适于附接至少两个半导体芯片的轮廓(长度271及宽度272)。在引线框架的制作工艺期间优选地通过压印技术而实现垫的偏离。阶梯270可小于、等于或大于开始金属厚度。选择阶梯270的高度，使得所述高度等于以下各项的和：将附接的半导体芯片的高度；及粘合剂附接层的高度。
或者，可使用蚀刻工艺。举例来说，可执行化学蚀刻工艺，使得仅不受氧化金属或极薄金层保护的那些表面(例如铜或铝)被侵蚀。对于一些应用，所蚀刻阶梯可约为垫厚度的一半。因此，具有此类凹部部分的引线框架有时被称为半蚀刻或部分蚀刻的引线框架。
图6是引线框架的第二表面201b的俯视图。图6展示将具有驱动器与控制器IC的芯片230附接到引线框架垫的第二表面201b以及通过接合线将芯片端子连接到相应引线框架引线的工艺。对于附接工艺，优选地采用～25μm厚度的传导性粘合剂(环氧树脂)层231，传导性粘合剂(环氧树脂)层231可被聚合(被固化)；而替代方案为z轴传导性聚合物。
在图7(仰视图)中所展示的下一工艺包含将驱动器与控制件芯片230囊封在封装材料(优选地模塑化合物290)中。图7的仰视图展示第一垫表面201a保持不囊封。此未囊封第一表面201a包含偏离部分201c，偏离部分201c距部分201d具有深度270且具有适于附接半导体芯片的横向尺寸。
图8展示下一工艺，即传导性粘合剂(环氧树脂)层211及221的施配或丝网印刷，传导性粘合剂(环氧树脂)层211及221可被聚合(被固化)。替代方案为z轴传导性聚合物。优选层厚度为～25μm。选择粘合剂，使得材料适于产品的所有附接接头。因此，所有粘合剂层可在共同固化步骤期间同时经历经升高温度下的聚合工艺。
图2B中展示接下来工艺(FET芯片的附接)的结果。第一FET芯片210(其也称作同步或低侧FET)附接到粘合剂层211，且因此附接到第一垫表面201a的偏离部分201c上。低侧FET具有漏极向下设计且以其漏极端子附接于粘合剂层上。源极端子及栅极端子背对垫表面201a。在附接之后，FET芯片210的源极端子210a及栅极端子210b与部分201d的垫表面共面，且因此也与引线202及203共面。由于所述共面性，因此源极端子210a可附接(例如通过焊料或通过传导性粘合剂)到充当到***的输入VOUT的PC板端子。第一芯片到板的此直接附接具有以下优点：消除寄生电阻及电感，且增强在***操作期间从***直接到板的散热片中的热耗散。
接下来，第二FET芯片220(其也称作控制或高侧FET)附接到粘合剂层221，且因此附接到第一垫表面201a的偏离部分201c上。高侧FET具有源极向下设计且以其源极端子附接于粘合剂层上。漏极端子及栅极端子背对垫表面201a。在附接之后，FET芯片220的漏极端子220a及栅极端子220b与部分201d的垫表面共面，且因此也与引线202及203共面。由于所述共面性，因此漏极端子220a可附接(例如通过焊料或通过传导性粘合剂)到充当到***的输入VOUT的PC板端子。第二芯片到板的此直接附接具有以下优点：消除寄生电阻及电感，且增强在***操作期间从***直接到板的散热片中的热耗散。
装置200的构造及制作工艺流程提供以下机会：仅采用传导性(金属填充的)聚合化合物用于进行组装，且同时使所有化合物层聚合。此外，当FET的端子到电路板的直接附接也使用传导性聚合物来执行时，完全省略了使用铅(Pb)用于焊料。
实例性实施例不仅适用于场效应晶体管，而且适用于其它适合电力晶体管。
作为另一实例，通过将散热器添加到封装的顶部表面，可进一步扩展电力供应模块的高电流能力且进一步增强效率。在此配置中，所述模块是双重冷却的且可将其热量从两侧表面耗散到散热片。
所描述实例不具有夹子且使芯片嵌入封装的外部在引线框架的经预先压印凹部中。与电力供应***的常规结构及制作方法相比，实例性实施例消除了两个夹子而未放弃夹子的功能，借此节省经组装***的高度。实例性实施例进一步：消除对应夹子组装步骤；及节省组装工艺流程的时间及成本。通过将两个FET芯片并排嵌入到经部分薄化的引线框架垫中而进一步减小成品装置的高度。由于组合件FET芯片的端子与引线框架垫端子共面，因此所有端子可同时且直接附接到电路板。通过避免热电阻，到电路板中的散热片的热耗散得以显著改进，从而将转换器操作频率增强超过1MHz。
在权利要求书的范围内，在所描述实施例中可做出若干修改，且其它实施例是可能的。

Claims (10)

1.一种电力供应***，其包括：
四方扁平无引线QFN类型引线框架，其具有多个引线及垫，所述垫具有第一垫表面及第二垫表面，所述第一垫表面具有凹入部分及未凹入部分，所述凹入部分具有深度及适于附接多个半导体芯片的轮廓，所述垫能够系接到所述***的切换节点端子；
第一场效应晶体管FET芯片，其具有所述第一FET芯片的附接到所述第一垫表面的所述凹入部分的漏极端子，且进一步具有与所述第一垫表面的所述未凹入部分共面的所述第一FET芯片的源极端子及栅极端子，所述第一FET芯片的所述源极端子能够系接到作为所述***的接地输出端子的板端子；及
第二FET芯片，其具有所述第二FET芯片的附接到所述第一垫表面的所述凹入部分的源极端子，且进一步具有与所述第一垫表面的所述未凹入部分共面的所述第二FET芯片的漏极端子及栅极端子，所述第二FET芯片的所述漏极能够系接到作为所述***的输入端子的板端子。
2.根据权利要求1所述的***，其进一步包含附接到所述第二垫表面的驱动器与控制器芯片。
3.根据权利要求2所述的***，其中所述驱动器与控制器芯片具有多个端子，所述多个端子通过接合线系接到所述引线框架的相应引线。
4.根据权利要求3所述的***，其进一步包含封装，所述封装囊封所述驱动器与控制器芯片、所述线及所述垫的所述第二表面以及若干引线，但使所述第一垫表面及所述多个引线中的至少一些引线不囊封。
5.根据权利要求1所述的***，其中所述第一FET芯片包含漏极FET，所述漏极FET用作低侧晶体管。
6.根据权利要求5所述的***，其中所述第二FET芯片包含源极向下FET，所述源极向下FET用作高侧晶体管。
7.一种制作电力供应***的方法，所述方法包括：
提供引线框架，所述引线框架具有引线及垫，所述垫具有第一表面及第二表面，所述第一表面具有凹入的部分，所述凹入部分具有深度及适于附接半导体芯片的轮廓；
将驱动器与控制件芯片附接在所述垫的所述第二表面上；
使用接合线将所述驱动器与控制件芯片的端子连接到相应引线；
将所述驱动器与控制件芯片、所述接合线及所述第二垫表面囊封在封装化合物中，而使所述第一垫表面不囊封；
接着使第一场效应晶体管FET芯片以其漏极端子附接到所述第一垫表面的所述凹入部分，使得所述第一FET芯片的源极端子及栅极端子与所述第一垫表面的未凹入部分共面；及
使第二FET芯片以其源极端子附接到所述第一垫表面的所述凹入部分，使得所述第二FET芯片的漏极端子及栅极端子与所述第一垫表面的所述未凹入部分共面。
8.根据权利要求7所述的方法，其进一步包含以下工艺：将所述垫连接到所述***的切换节点端子，将所述第一FET芯片的所述源极端子连接到作为所述***的接地输出端子的板端子，及将所述第二FET芯片的所述漏极连接到作为所述***的输入端子的板端子。
9.根据权利要求7所述的方法，其中所述附接工艺采用选自包含传导性粘合剂及具有z轴导体的聚合化合物的群组的附接材料。
10.根据权利要求7所述的方法，其中所述引线框架具有四方扁平无引线QFN或小轮廓无引线SON类型的配置。
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