CN105914258A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
- Publication number
- CN105914258A CN105914258A CN201610365953.7A CN201610365953A CN105914258A CN 105914258 A CN105914258 A CN 105914258A CN 201610365953 A CN201610365953 A CN 201610365953A CN 105914258 A CN105914258 A CN 105914258A
- Authority
- CN
- China
- Prior art keywords
- semiconductor layer
- nitride semiconductor
- metal
- layer
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 322
- 238000002360 preparation method Methods 0.000 title abstract description 27
- 150000004767 nitrides Chemical class 0.000 claims abstract description 237
- 238000004544 sputter deposition Methods 0.000 claims abstract description 112
- 239000000758 substrate Substances 0.000 claims abstract description 106
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 100
- 229910021389 graphene Inorganic materials 0.000 claims abstract description 97
- 239000013078 crystal Substances 0.000 claims abstract description 91
- 238000000034 method Methods 0.000 claims abstract description 66
- 238000000151 deposition Methods 0.000 claims abstract description 56
- 230000008021 deposition Effects 0.000 claims abstract description 44
- 229910052751 metal Inorganic materials 0.000 claims description 103
- 239000002184 metal Substances 0.000 claims description 97
- 238000004062 sedimentation Methods 0.000 claims description 84
- 238000000137 annealing Methods 0.000 claims description 46
- 239000011521 glass Substances 0.000 claims description 36
- 239000000203 mixture Substances 0.000 claims description 25
- 238000010884 ion-beam technique Methods 0.000 claims description 21
- 229910002704 AlGaN Inorganic materials 0.000 claims description 14
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 14
- 229910045601 alloy Inorganic materials 0.000 claims description 13
- 239000000956 alloy Substances 0.000 claims description 13
- 229910052759 nickel Inorganic materials 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 229910052742 iron Inorganic materials 0.000 claims description 7
- 238000001659 ion-beam spectroscopy Methods 0.000 claims description 5
- 210000002615 epidermis Anatomy 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 18
- 239000010410 layer Substances 0.000 description 277
- 230000015572 biosynthetic process Effects 0.000 description 34
- 239000000463 material Substances 0.000 description 23
- 239000000126 substance Substances 0.000 description 14
- 238000002474 experimental method Methods 0.000 description 13
- 239000004020 conductor Substances 0.000 description 10
- 239000007792 gaseous phase Substances 0.000 description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 7
- 238000009826 distribution Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 230000008901 benefit Effects 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- 239000002356 single layer Substances 0.000 description 5
- 238000003786 synthesis reaction Methods 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 230000002411 adverse Effects 0.000 description 4
- 150000001336 alkenes Chemical class 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 229910017464 nitrogen compound Inorganic materials 0.000 description 4
- 150000002830 nitrogen compounds Chemical class 0.000 description 4
- 230000003197 catalytic effect Effects 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910002804 graphite Inorganic materials 0.000 description 3
- 239000010439 graphite Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000006698 induction Effects 0.000 description 3
- 238000011835 investigation Methods 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 238000001953 recrystallisation Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000002441 X-ray diffraction Methods 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 2
- 239000002178 crystalline material Substances 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 239000002689 soil Substances 0.000 description 2
- 238000005477 sputtering target Methods 0.000 description 2
- 229910000601 superalloy Inorganic materials 0.000 description 2
- 239000013077 target material Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 235000014593 oils and fats Nutrition 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 229910001404 rare earth metal oxide Inorganic materials 0.000 description 1
- 230000026267 regulation of growth Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0054—Processes for devices with an active region comprising only group IV elements
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a semiconductor structure and a preparation method thereof. Specifically, the method comprises the following steps: (1) providing a substrate; (2) arranging a graphene layer on the upper surface of the substrate; and (3) forming a first nitride semiconductor layer on the upper surface of the graphene layer through sputtering deposition to get the semiconductor structure, wherein the first nitride semiconductor layer has crystal preferred orientation. Therefore, the preparation cost is reduced, the preparation technology is simplified, and a first nitride semiconductor layer with crystal preferred orientation is obtained.
Description
Technical field
The present invention relates to semiconductor technology and field of semiconductor manufacture, specifically, the present invention relates to semiconductor structure and
The method preparing semiconductor structure.
Background technology
In technical field of semiconductors, the substrate of solaode or light emitting diode (LED) mostly is glass or metal.
Use glass as substrate, the light transmission of available glass, and with low cost therefore have a good application prospect；Use gold
Belong to as substrate, then the feature that metallic conduction performance can be utilized good improves device performance, or utilizes flexible metal film
Substrate prepares flexible semiconductor device.But, for the solaode or LED of better performances, therein partly lead
Body material typically requires that into the polycrystalline that monocrystalline or crystal orientation concordance are good, crystal the most therein has preferred orientation.At present
The method that can use epitaxial growth or sputtering sedimentation obtains semiconductive thin film at glass surface, quasiconductor prepared by these methods
Thin film or be non-crystalline material, or be the polycrystalline material not having crystal preferred orientation, it is difficult to obtain that crystal preferred orientation is good half
Conductor thin film, it is difficult to meet the requirement of high performance solar cells or light emitting diode.
Therefore, it is currently based on glass or metal substrate is prepared the semiconductor technology of nitride semi-conductor material and still had much room for improvement.
Summary of the invention
Graphene, as the two-dimensional layer material of a kind of unique properties, is widely used in such as solaode etc. half in recent years
In conductor device or semiconductor structure.Inventor finds through further investigation and great many of experiments, introduces in the semiconductor structure
Graphene layer, utilizes Graphene to have the characteristic of two-dimensional layered structure, meanwhile, by suitable sputter deposition craft, it is possible to
Induction produces the nitride semiconductor layer with crystal preferred orientation.Can prepare on glass or metal substrate and there is crystalline substance
The nitride film of body preferred orientation, such that it is able to be used for preparing the quasiconductors such as high performance solaode, light emitting diode
Device.Additionally, by the lattice paprmeter controlling element nitride crystal so that it is and have between common semiconductor crystalline material preferably
Lattice Matching degree, thereby may be ensured that the crystal that the semiconductor layer being grown on this element nitride crystal layer has had preferentially takes
To.
It is contemplated that one of technical problem solved the most to a certain extent in correlation technique.To this end, the one of the present invention
Purpose is to propose a kind of method preparing semiconductor structure, and the method uses the method for sputtering sedimentation, by introducing Graphene
Layer and the control to sputtering condition, it is possible to form the nitride semiconductor layer with crystal preferred orientation.With utilize outside solid phase
Epitaxial growth technology and metal organic chemical vapor deposition technology are compared, and sputtering sedimentation has with low cost, simple to operate etc. excellent
Point.
In one aspect of the invention, the present invention proposes a kind of method preparing semiconductor structure.The method includes: (1)
Substrate is provided；(2) surface configuration graphene layer over the substrate；And (3) pass through at the upper surface of described graphene layer
Sputtering sedimentation, forms the first nitride semiconductor layer, in order to obtain described semiconductor structure, described first nitride-based semiconductor
Layer has crystal preferred orientation.Thus, it is possible to reduction preparation cost, simplify preparation technology, and acquisition has crystal and preferentially takes
To nitride semiconductor layer.Graphene layer and suitable sputtering condition can induce the first nitride semiconductor layer to form crystalline substance
The preferred orientation of body, and, first nitride semiconductor layer with crystal preferred orientation can induced synthesis thereon its
The formation of remaining semiconductor layer, makes the lattice arrangement in the semiconductor layer of formation also have preferred orientation.Meanwhile, the first nitridation
During thing semiconductor layer can also stop that in substrate, impurity is diffused into remaining semiconductor layer, such that it is able to be effectively improved semiconductor structure
Performance.
According to embodiments of the invention, step (3) farther includes: by sputtering sedimentation at the upper surface of described graphene layer
Form nitride-based semiconductor mixture, described nitride-based semiconductor mixture is carried out the first annealing, in order to obtain described
First nitride semiconductor layer.Thus, it is possible to simplify the preparation technology of sputter deposition process further, reduce depositing device
Requirement, such that it is able to reduce production cost further.
According to embodiments of the invention, the method farther includes: (4) at described first nitride semiconductor layer away from described
The side of graphene layer forms the second nitride semiconductor layer, and described second nitride semiconductor layer has crystal preferred orientation.
Thus, it is possible to utilize the crystal preferred orientation of the first nitride semiconductor layer, improve the quality of the second nitride semiconductor layer.
According to embodiments of the invention, the method farther includes；(5) to described substrate, described graphene layer, described
Mononitride semiconductor layer and described second nitride semiconductor layer carry out the second annealing.Thus, it is possible to by second
Annealing, improves the first nitride semiconductor layer and the crystalline quality of the second nitride semiconductor layer further.
According to embodiments of the invention, described first nitride semiconductor layer contains AlN, GaN, AlGaN and InGaN
At least one.Those skilled in the art can select above-mentioned material to form the first nitride semiconductor layer according to the actual requirements,
Thus, it is possible to improve the performance of this semiconductor structure further.
According to embodiments of the invention, described second nitride semiconductor layer contains AlN, GaN, AlGaN and InGaN
At least one, described second nitride semiconductor layer composition differs with the composition of described first nitride semiconductor layer.By
This, can improve the performance of this semiconductor structure further.
According to embodiments of the invention, described substrate is formed by glass or metal.Quasiconductor according to embodiments of the present invention
Structure can use glass or metal as backing material, such that it is able to utilize glass substrate preparation to have the half of light transmission
Conductor structure, or utilize the preferable electric conductivity of metal substrate to obtain the semiconductor structure that electric property is good.
According to embodiments of the invention, described glass top surface has the coat of metal.Thus, it is possible to directly on the coat of metal
The method deposited by chemical gaseous phase forms graphene layer, thus is conducive to improving the knot between graphene layer and glass substrate
Close quality, and then the performance of this semiconductor structure can be improved.
According to embodiments of the invention, described metal includes high temperature alloy.Thus, on the one hand it is possible to prevent metal substrate rear
Continuous pyroprocess fusing, on the other hand can alleviate the diffusion in hot environment of the substrate metal element, and then be possible to prevent
Metallic element in substrate spreads and adversely affects the performance of this semiconductor structure.
According to embodiments of the invention, the upper surface of described metal or the described coat of metal contains in Ni, Co, Cu, Fe
At least one.Above-mentioned metal has preferable catalytic action to forming Graphene, and thus, beneficially raising utilizes chemical gaseous phase
It is deposited thereon the quality of the graphene layer of formation.
According to embodiments of the invention, the upper surface of described metal or the described coat of metal has texture structure.Thus, it is possible to
The crystal orientation distribution utilizing crystal grain on metal or coat of metal upper surface deviates considerably from the texture structure of random distribution, induction
The graphene layer being formed thereon also has the most orderly structure, and then can improve the quality of graphene layer, in order to obtain
There is the first nitride semiconductor layer and second nitride semiconductor layer of more preferable crystalline quality.
According to embodiments of the invention, described graphene layer contains 1～10 layer graphene monolayers.Thin and the graphite of ordered arrangement
Alkene layer can effectively induce the first nitride semiconductor layer to form the most orderly crystal preferred orientation, the number of plies of Graphene monolayer
Graphene layer within the above range can improve the regulation effect of the performance to semiconductor structure further.
According to embodiments of the invention, described sputtering sedimentation is magnetron sputtering deposition or ion beam sputter depositing.Magnetic control is utilized to spatter
Penetrate or ion beam sputtering can preferably control the crystal structure of sedimentation rate and formation of deposits, thus advantageously form tool
There is the first nitride semiconductor layer of crystal preferred orientation.
According to embodiments of the invention, described sputtering sedimentation is pulsed sputtering sedimentation or ion beam aided sputtering deposition.Thus,
Pulsed sputtering sedimentation or ion beam aided sputtering deposition can be utilized to control the speed of deposition, improve the first nitride obtained
The crystalline quality of semiconductor layer.
According to embodiments of the invention, the sputter rate of described sputtering sedimentation is less than 100nm/ hour.When sputter rate is less than upper
When stating numerical value, it is possible to significantly improve the crystalline quality of the first nitride semiconductor layer that sputtering sedimentation obtains, and then one can be entered
Step improves the performance of this semiconductor structure.
According to embodiments of the invention, during described sputtering sedimentation, underlayer temperature is not less than 300 degrees Celsius.Thus, it is possible to it is easy
Ground is by heating substrate, it is thus achieved that have the structure of crystal preferred orientation, such that it is able to reduce deposition step to equipment
Requirement, simplifies preparation technology, reduces production cost.
According to embodiments of the invention, the temperature of described first annealing and the second annealing is separately
600～1200 degrees Celsius.Thus, it is possible to improve crystalline quality further.
In another aspect of this invention, the present invention proposes a kind of semiconductor structure.According to embodiments of the invention, this is partly led
Body structure includes: substrate；Graphene layer, described graphene layer is arranged on the upper surface of described substrate；With the first nitride
Semiconductor layer, described first nitride semiconductor layer is formed at the upper surface of described graphene layer, and described first nitride
Semiconductor layer has crystal preferred orientation.Graphene layer can induce the first nitride semiconductor layer to form the preferred orientation of crystal,
Further, first nitride semiconductor layer with crystal preferred orientation can lattice in induced synthesis remaining structure thereon
Arrangement also has preferred orientation, and meanwhile, the first nitride semiconductor layer can also stop the diffusion of impurity in substrate, permissible
It is effectively improved the performance of this semiconductor structure, thus beneficially this semiconductor structure of later use constitutes solaode or luminescence
The structures such as diode.
According to embodiments of the invention, described substrate is formed by glass or metal.Quasiconductor according to embodiments of the present invention
Structure can use glass or metal as backing material, such that it is able to utilize glass substrate preparation to have the half of light transmission
Conductor structure, or utilize the preferable electric conductivity of metal substrate to obtain the semiconductor structure that electric property is good.
According to embodiments of the invention, described metal includes high temperature alloy.Thus, on the one hand it is possible to prevent metal substrate rear
Continuous pyroprocess fusing, on the other hand can alleviate the diffusion in hot environment of the substrate metal element, and then be possible to prevent
Metallic element in substrate spreads and adversely affects the performance of this semiconductor structure.
According to embodiments of the invention, described glass top surface has the coat of metal.Thus, it is possible to directly on the coat of metal
The method deposited by chemical gaseous phase forms graphene layer, thus is conducive to improving the knot between graphene layer and glass substrate
Close quality, and then the performance of this semiconductor structure can be improved.
According to embodiments of the invention, the upper surface of described metal and the described coat of metal contains in Ni, Co, Cu, Fe
At least one.Above-mentioned metal has preferable catalytic action to forming Graphene, and thus, beneficially raising utilizes chemical gaseous phase
It is deposited thereon the quality of the graphene layer of formation.
According to embodiments of the invention, the upper epidermis of described metal and the described coat of metal has texture structure.Thus, may be used
Deviate considerably from the texture structure of random distribution to utilize the crystal orientation of crystal grain on metal or coat of metal upper surface to be distributed, lure
Lead the graphene layer being formed thereon and also there is the most orderly structure, and then the quality of graphene layer can be improved, in order to obtain
Must have the first nitride semiconductor layer and second nitride semiconductor layer of more preferable crystalline quality.
According to embodiments of the invention, described first nitride semiconductor layer contains AlN, GaN, AlGaN and InGaN
At least one.Those skilled in the art can select the concrete material of the first nitride semiconductor layer according to the actual requirements, by
This, can improve the performance of this semiconductor structure further.
According to embodiments of the invention, described semiconductor structure farther includes: the second nitride semiconductor layer, and described second
Nitride semiconductor layer is formed at described first nitride semiconductor layer side away from described graphene layer, described nitride half
Conductor layer has crystal preferred orientation.Thus, it is possible to utilize the first nitride semiconductor layer induction with crystal preferred orientation
The formation of the second nitride semiconductor layer, such that it is able to improve the crystalline quality of the second nitride semiconductor layer.
According to embodiments of the invention, described second nitride semiconductor layer contains AlN, GaN, AlGaN and InGaN
At least one, described second nitride semiconductor layer composition differs with the composition of described first nitride semiconductor layer.By
This, can improve the performance of this semiconductor device further.
According to embodiments of the invention, the halfwidth of the XRD diffraction maximum of described first nitride semiconductor layer (0002) crystal face
Less than 5 degree.The halfwidth controlling XRD diffraction maximum is conducive to improving the crystalline quality of the first nitride semiconductor layer.
According to embodiments of the invention, described first nitride semiconductor layer is formed by sputtering sedimentation.Thus, it is possible to
While ensureing the first nitride semiconductor layer quality, reduce preparation cost, simplify preparation technology.
According to embodiments of the invention, described first nitride semiconductor layer is formed by sputtering sedimentation and annealing.
Thus, it is possible to simplify the preparation technology of sputter deposition process further, reduce the requirement to depositing device, such that it is able to enter one
Step reduces production cost.
According to embodiments of the invention, described second nitride semiconductor layer is formed by sputtering sedimentation.Thus, it is possible to
While ensureing the second nitride semiconductor layer quality, reduce preparation cost, simplify preparation technology.
According to embodiments of the invention, the second nitride semiconductor layer is formed by sputtering sedimentation and annealing.Thus,
The preparation technology of sputter deposition process can be simplified further, reduce the requirement to depositing device, such that it is able to reduce further
Production cost.
According to embodiments of the invention, described sputtering sedimentation is magnetron sputtering deposition or ion beam sputter depositing.Magnetic control is utilized to spatter
Penetrate or ion beam sputtering can preferably control the crystal structure of sedimentation rate and formation of deposits, thus advantageously form tool
There is the structure of crystal preferred orientation.
According to embodiments of the invention, described sputtering sedimentation is pulsed sputtering sedimentation or ion beam aided sputtering deposition.Thus,
Pulsed sputtering sedimentation or ion beam aided sputtering deposition can be utilized to control the speed of deposition, improve crystalline quality.
According to embodiments of the invention, during described sputtering sedimentation, underlayer temperature is more than 300 degrees Celsius.Thus, preparation work is simplified
Skill, reduces production cost.
According to embodiments of the invention, the sputter rate of described sputtering sedimentation is less than 100nm/ hour.When sputter rate is less than upper
When stating numerical value, it is possible to significantly improve the crystalline quality that sputtering sedimentation obtains, and then this semiconductor structure can be improved further
Performance.
Accompanying drawing explanation
Fig. 1 is the flow chart of the method preparing semiconductor structure according to an embodiment of the invention；
Fig. 2 is the flow chart of the method preparing semiconductor structure in accordance with another embodiment of the present invention；
Fig. 3 is the structural representation of semiconductor structure according to an embodiment of the invention；And
Fig. 4 is the structural representation of semiconductor structure in accordance with another embodiment of the present invention.
Description of reference numerals:
100: substrate；200: graphene layer；300: the first nitride semiconductor layers；400: the second nitride semiconductor layers.
Detailed description of the invention
Embodiments of the invention are described below in detail, and the example of described embodiment is shown in the drawings, the most identical
Or similar label represents same or similar element or has the element of same or like function.Retouch below with reference to accompanying drawing
The embodiment stated is exemplary, it is intended to is used for explaining the present invention, and is not considered as limiting the invention.
In describing the invention, it is to be understood that term " on ", the orientation of the instruction such as D score or position relationship be based on
Orientation shown in the drawings or position relationship, be for only for ease of the description present invention and simplify description rather than instruction or hint institute
The device that refers to or element must have specific orientation, with specific azimuth configuration and operation, therefore it is not intended that to this
Bright restriction.
In one aspect of the invention, the present invention proposes a kind of method preparing semiconductor structure.Generally, sputtering is used
Method is hardly formed crystal preferred orientation, general many formation polycrystalline or impalpable structure.Inventor is through furtheing investigate and big
Amount experiment finds, by being firstly introduced into graphene layer structure, and lining when reducing sputter rate, raising sputtering in substrate
The modes such as end temperature, or processed by subsequent anneal, improve the crystalline quality of the nitride-based semiconductor that sputtering is formed, permissible
Realize utilizing sputtering to obtain crystal preferred orientation.Utilize the two-dimensional structure of graphene layer during this, nitride partly can be led
The growth of body forms inducing action, and make use of nitride semiconductor crystal anisotropy of the speed of growth when epitaxial growth,
I.e. nitride semiconductor thin film is when deposition, and the deposition growth rate in some crystal orientation is significantly faster than that other crystal face, and spatters at high temperature
Penetrating nitride-based semiconductor in deposition and annealing process and have obvious crystal recrystallization, the big crystal grain with preferred orientation is continuous
Grow up so that the little crystal grain of non-preferred orientation is fewer and feweri to be even disappeared completely.In the present invention, " preferred orientation of crystal " is
Refer to that crystal has preferred orientation, a range of in the i.e. first nitride semiconductor layer and the second nitride semiconductor layer
Crystal orientation reaches unanimity, and the most also includes monocrystalline (being orientated completely the same in crystal everywhere).Specifically, according to the present invention's
Embodiment, with reference to Fig. 1, the method includes:
S100: substrate is provided
According to embodiments of the invention, in this step, it is provided that substrate is to form semiconductor structure.Specifically, substrate can
To be formed by glass or metal.Semiconductor structure according to embodiments of the present invention can use glass or metal as lining
Bottom material, such that it is able to utilize glass substrate preparation to have the semiconductor structure of light transmission, or utilizes metal substrate preferable
Electric conductivity obtain the good semiconductor structure of electric property.
Specifically, when using glass as substrate, glass top surface can have the coat of metal.Thus, it is possible to directly exist
The method deposited by chemical gaseous phase on the coat of metal forms graphene layer, thus is conducive to improving graphene layer and glass lined
Bond quality at the end, and then the performance of this semiconductor structure can be improved.According to embodiments of the invention, use metal
During as substrate, high temperature alloy can be selected to form above-mentioned substrate.Thus, on the one hand it is possible to prevent metal substrate follow-up
Pyroprocess melts, and on the other hand can alleviate the diffusion in hot environment of the substrate metal element, and then be possible to prevent substrate
In metallic element diffusion and the performance of this semiconductor structure is adversely affected.
According to embodiments of the invention, the upper surface of above-mentioned metal or the coat of metal can be containing in Ni, Co, Cu, Fe
At least one.Such as, the upper surface of metal or the coat of metal can be by the alloy formed containing one or more elements above-mentioned
Constitute.Alloy containing above-mentioned metallic element has catalytic action to forming graphene layer, thus, is conducive to improving utilization
Chemical gaseous phase is deposited thereon the quality of the graphene layer of formation.
According to embodiments of the invention, the upper surface of above-mentioned metal or the coat of metal can have texture structure.Thus, it is possible to
Polycrystal distribution of orientations on metal or coat of metal upper surface is utilized to deviate considerably from the texture structure of random distribution, induced synthesis
Graphene layer thereon also has the most orderly structure, and then can improve the quality of graphene layer, in order to obtains and has
More preferably the first nitride semiconductor layer of crystalline quality.It should be noted that the concrete grammar forming above-mentioned texture structure is not subject to
Limiting especially, those skilled in the art can select the method being familiar with, at metal substrate or the metal of glass substrate upper surface
Texture structure is formed on coating.Such as, according to embodiments of the invention, deformation texture can be passed through, i.e. plastic deformation and
The method of annealing, forms upper surface and has the metal substrate of texture structure.Specifically, can be first to the metal constituting substrate
Material carries out plastic deformation, such as, metal material is rolled into thin slice, then by recrystallization annealing, surface is formed thereon
Texture structure.Or, the coat of metal can be formed by the method for sputtering sedimentation in surface on a glass substrate, such as by from
Son bundle assisted deposition technique, by regulating the condition of sputtering sedimentation, the anisotropy of coat of metal growth when utilizing sputtering sedimentation,
By sedimentation rate slowly or to methods such as silicon, form the coat of metal with texture structure.
It will be appreciated to those of skill in the art that the quality of semiconductor structure in order to improve preparation, carry out subsequent step
Before, substrate can be carried out, in order to remove the impurity such as the oils and fats of substrate surface, dust, such that it is able to improve follow-up
The deposition effect of step.
S200: graphene layer is set
According to embodiments of the invention, in this step, the upper surface at substrate arranges graphene layer.Specifically, Graphene
The method that layer can be deposited by chemical gaseous phase, is formed directly into the upper surface of substrate；Or, it is possible to use Graphene shifts
Technology, is transferred to the graphene layer formed in other substrate material surface on the upper surface of substrate according to embodiments of the present invention.
Specifically, direct shape can be deposited at metal substrate or the glass substrate upper surface with the coat of metal by chemical gaseous phase
Become graphene layer.Now, the upper surface of preferably metal substrate or the coat of metal has texture structure.There is certain crystal take
To texture structure beneficially improve the order degree of the graphene layer being formed thereon, and then follow-up first nitridation can be improved
Thing semiconductor layer and the crystalline quality of semiconductor layer.Other embodiments according to the present invention, it is also possible to serve as a contrast at other in advance
Basal surface forms graphene layer, then utilizes transfer techniques, transfers them to substrate surface according to embodiments of the present invention.This
Time, substrate can be the glass without the coat of metal.
According to embodiments of the invention, graphene layer can have the Graphene monolayer of 1～10 layer.Thin and the graphite of ordered arrangement
Alkene layer can effectively induce the first nitride semiconductor layer to form the most orderly crystal preferred orientation, it is achieved to semiconductor structure
Performance be adjusted.It should be noted that in the present invention, term " Graphene monolayer " refers in particular to monoatomic layer Graphene,
Graphene i.e. contains only the graphite-structure of one layer of ordered arrangement, and term " graphene layer " can be Graphene monolayer, also
It can be the multi-layer graphene of multiple Graphene monoatomic layer composition.
S300: the first nitride semiconductor layer is set
According to embodiments of the invention, in this step, the upper surface at graphene layer passes through sputtering sedimentation, forms the first nitrogen
Compound semiconductor layer.Thus, it is possible to reduction preparation cost, simplify preparation technology, and acquisition has the dilute of crystal preferred orientation
Soil oxide structure.
Sputter deposition process is described in detail by the specific embodiment below according to the present invention.
According to embodiments of the invention, the first nitride semiconductor layer can contain AlN, GaN, AlGaN and InGaN
At least one.Above-mentioned nitride semi-conductor material has good physical and chemical performance, is suitable to prepare semiconductor photoelectric device.Example
As, according to embodiments of the invention, AlN can be used to form the first nitride semiconductor layer.Use the first of AlN formation
Nitride semiconductor layer, is possible not only to the broad-band gap utilizing AlN material to have, good uv transmittance and height and punctures
The performances such as field intensity, improve the performance of the semiconductor structure formed, it is also possible to as other nitride semi-conductor materials of subsequent growth
The good substrate of (the second nitride semiconductor layer), because compared with the substrate of the material such as metal, AlN and remaining nitride
Semi-conducting material has more preferable lattice matching property.
Specifically, according to embodiments of the invention, magnetron sputtering deposition or ion beam sputter depositing can be used to form the first nitrogen
Compound semiconductor layer.Inventor finds through great many of experiments, and not only graphene layer can induce the first nitride semiconductor layer shape
Becoming the preferred orientation of crystal, the crystal structure of the speed of sputtering sedimentation the first nitride semiconductor layer to being formed also has important
Impact.Sputtering sedimentation speed advantageously forms first nitride semiconductor layer with crystal preferred orientation slowly.Magnetic control is utilized to spatter
Penetrate or ion beam sputtering can preferably control sedimentation rate, such that it is able to control the crystal knot of the nitride-based semiconductor of deposition
Structure, is formed and has a crystal preferred orientation and the first nitride semiconductor layer of the polycrystalline of non-confusion arrangement.Preferably, according to this
Inventive embodiment, sputtering sedimentation can also be pulsed sputtering sedimentation or ion beam aided sputtering deposition.Pulsed sputtering is heavy
Long-pending replacing DC source to carry out sputtering sedimentation owing to have employed the pulse power, can effectively control deposition velocity, enhanced deposition is former
The migration of son, promotes the formation of crystal preferred orientation；Use ion beam aided sputtering deposition, utilize Assisted by Ion Beam bombardment heavy
Long-pending substrate (i.e. metal or glass substrate), can improve energy and the stability of deposition aggregated particle, eliminate deposition table simultaneously
The defect in face and the crystal grain of non-preferred orientation, be conducive to improving the quality of the first nitride semiconductor layer of formation of deposits, formed
There is the first nitride semiconductor layer of preferred orientation.Specifically, according to embodiments of the invention, sputtering sedimentation can be controlled
Sputter rate less than 100nm/ hour；According to other embodiments of the present invention, the sputter rate of sputtering sedimentation can be controlled
Less than 30nm/ hour.Inventor finds through great many of experiments, when sputter rate is less than above-mentioned numerical value, it is possible to form crystallization
The first nitride semiconductor layer that quality is higher, sedimentation rate is the lowest, then the preferred orientation of the crystal obtained is the best.Above-mentioned
Under the conditions of the halfwidth of the XRD diffraction maximum of the first nitride semiconductor layer (0002) crystal face that formed can be less than 5 degree.By
This, it is possible to use pulsed sputtering sedimentation or ion beam aided sputtering deposition improve the first nitride semiconductor layer of acquisition
Crystalline quality.Inventor finds through great many of experiments, for conventional magnetron sputtering, deposits the first nitride-based semiconductor
Time its sedimentation rate easily reach 1000nm/ hour the highest, now be difficult to obtain have preferred orientation first nitridation
Thing semiconductor layer, generally requires and utilizes pulsed magnetron sputtering or ion beam aided sputtering deposition technique, by big for its sedimentation rate
Amplitude reduction to less than 100nm/ hour, is then obtained in that first nitride semiconductor layer with preferred orientation.
According to embodiments of the invention, in this step, tool can be formed by substrate being heated in sputter procedure
There is the first nitride semiconductor layer of crystal preferred orientation.Inventor finds through great many of experiments, the underlayer temperature of sputtering sedimentation
The highest, then the preferred orientation of crystal is the best.Specifically, when can make sputtering sedimentation by heating, underlayer temperature is not less than 300
Degree Celsius.Inventor finds through further investigation and great many of experiments, the first nitridation formed for nitride semi-conductor material
Thing semiconductor layer, when underlayer temperature is less than 300 degrees Celsius when deposited, the first nitride semiconductor layer of formation mostly is polycrystalline
Structure.When underlayer temperature is increased to 300～500 degrees Celsius, the crystal making formation is conducive to have preferred orientation.Further,
Under above-mentioned heating-up temperature, carry out sputtering sedimentation, also metal or glass substrate will not be impacted.And the adding of said temperature
The graphene layer of substrate not only will not be impacted by heat, and it is organic to remove the part of absorption among graphene layer
Impurity, or the impalpable structure formed in chemical vapor deposition processes, such that it is able to improve having of graphene layer further
Sequence degree.Thus, it is possible to easily by substrate is heated, it is thus achieved that the first nitride semiconductor layer, such that it is able to fall
The requirement to equipment of the low deposition step, simplifies preparation technology, reduces production cost.
According to other embodiments of the present invention, in this step, it is also possible to by normal temperatures target being carried out sputtering sedimentation,
Such as, carrying out magnetron sputtering, substrate does not heats, and the upper surface formation of deposits at graphene layer has polycrystalline or non crystalline structure
Nitride mixture.It will be appreciated to those of skill in the art that foregoing " silicon ", be i.e. that substrate is carried out
Heat treated, and the graphene layer owing to being formed thereon comprises only～10 layers of single-layer graphene, and Graphene is that the good of heat is led
Body, therefore heats substrate, the most also comprises the graphene layer to being formed at substrate top surface and heats.Need explanation
, in the present invention, term " nitride mixture " refer in particular under room temperature or low temperature, target to be carried out sputtering sedimentation formation,
There is polycrystalline structure, but tend not to consistent structure without preferable preferred orientation, i.e. crystal lattice orientation.Then, dilute to formed
Soil oxide mixture carries out the first annealing so that it is be converted into the crystal structure with preferred orientation, such that it is able to improve
The crystalline quality of rare earth oxide mixture, it is thus achieved that the first nitride semiconductor layer according to embodiments of the present invention.Inventor's warp
Crossing great many of experiments to find, the time of annealing is the longest, then the crystal mass of the first nitride semiconductor layer is the best.Thus, it is possible to
Obtain the first nitride semiconductor layer by annealing easily, be conducive to reducing further the deposition step requirement to equipment, letter
Change preparation technology, reduce production cost.According to the still other embodiments of the present invention, in this step, it is also possible to by height
Under temperature, target is carried out sputtering sedimentation, such as, to silicon during magnetron sputtering, the underlayer temperature can be made to be
300-500 degrees centigrade, the upper surface formation of deposits at graphene layer has the first nitride-based semiconductor of crystal preferred orientation
Layer, carries out the first annealing to the first nitride semiconductor layer formed subsequently, such that it is able to improve the first nitridation further
The crystalline quality of thing semiconductor layer, it is thus achieved that high-quality have the most high-quality mono-crystalline structures of crystal preferred orientation.According to this
Some embodiments of invention, the temperature of the first annealing can be 600～1200 degrees Celsius.Other according to the present invention are real
Executing example, the temperature of the first annealing can also be 800～1000 degrees Celsius.Thus, it is possible to improve the first nitride further
The crystalline quality of semiconductor layer.It will be appreciated to those of skill in the art that when needing the first nitride semiconductor layer is carried out
During annealing, need to use resistant to elevated temperatures metal as substrate.
According to embodiments of the invention, in order to improve the performance of the semiconductor structure utilizing said method to prepare further, according to
Embodiments of the invention, with reference to Fig. 2, the method can further include:
S400: the second nitride semiconductor layer is set
According to embodiments of the invention, in this step, the upper surface at the first nitride semiconductor layer forms the second nitride
Semiconductor layer.In other words, nitrogenize away from the side formation second of substrate and graphene layer at the first nitride semiconductor layer
Thing semiconductor layer.Concrete, the second nitride semiconductor layer can containing AlN, GaN, AlGaN and InGaN extremely
One of few.Second nitride semiconductor layer composition differs with the composition of described first nitride semiconductor layer.Due to the first nitrogen
Compound semiconductor layer has preferable crystal preferred orientation, therefore forms the second nitride half on the first nitride semiconductor layer
During conductor layer, it is possible to the second nitride semiconductor layer is played inducing action, make in the second nitride semiconductor layer of formation
Lattice arrangement also has preferred orientation.Further, it is due to the first nitride semiconductor layer and the second nitride semiconductor layer
Nitride semi-conductor material is formed, and therefore forms the second nitride semiconductor layer on the first nitride semiconductor layer, with
Directly forming the second nitride semiconductor layer on the metallic substrate to compare, the Lattice Matching degree between double-layer structure is more preferable, by
This, can optimize the semiconductor structure that the method is formed.
It should be noted that in this step, the concrete grammar forming the second nitride semiconductor layer is not particularly limited.Example
As, sputtering sedimentation and annealing can be used to form second nitride semiconductor layer with preferred orientation, or directly by height
Temperature sputtering sedimentation is formed, it is also possible to utilize mocvd process to be formed.
In order to improve the crystal preferred orientation of each layer in this semiconductor structure further, the method may further include second and moves back
Fire.According to some embodiments of the present invention, can after formation of the second nitride semiconductor layer, to substrate, graphene layer,
First nitride semiconductor layer and the second nitride semiconductor layer carry out the second annealing.Specifically, according to the present invention's
Embodiment, the temperature of the second annealing can be 600～1200 degrees Celsius.According to other embodiments of the present invention, second
The temperature of annealing can also be 800～1000 degrees Celsius.Thus, it is possible to improve further the first nitride semiconductor layer and
The crystalline quality of the second nitride semiconductor layer, improves its crystal preferred orientation.Inventor finds through great many of experiments, time long
Between annealing can make the first nitride semiconductor layer and the second nitride semiconductor layer recrystallization, form crystal preferentially
Orientation.Therefore, above-mentioned semiconductor structure is carried out the second annealing and is conducive to improving the crystalline of nitride semi-conductor material
Amount.It will be appreciated by persons skilled in the art that the method for sputtering can also be utilized first to be formed on substrate not to be had preferentially
First nitride semiconductor layer of orientation and the second nitride semiconductor layer, recycle long second annealing and make
First nitride semiconductor layer and the second nitride semiconductor layer form the preferred orientation of crystal, and this kind of situation is also the present invention's
Among protection domain.It should be noted that in the present invention, in " long second annealing ", the second annealing
The concrete time be not particularly limited, as long as first nitride semiconductor layer and second with crystal preferred orientation can be formed
Nitride semiconductor layer, or the crystal structure quality of said structure can be improved.According to a particular embodiment of the invention,
The concrete time of the second annealing can be 1～20 hour.Annealing temperature is the highest, then annealing time can suitably shorten.
In another aspect of this invention, the present invention proposes a kind of semiconductor structure.According to embodiments of the invention, with reference to Fig. 3,
This semiconductor structure includes: substrate 100, graphene layer 200 and the first nitride semiconductor layer 300.Wherein, Graphene
Layer 200 is formed on the upper surface of substrate 100, and the first nitride semiconductor layer 300 is formed at the upper table of graphene layer 200
Face, and the first nitride semiconductor layer 300 has crystal preferred orientation.First nitride with crystal preferred orientation is partly led
Body layer is conducive to this semiconductor structure of later use to constitute the electronic device such as solaode, light emitting diode.
Specifically, substrate 100 can be formed by glass or metal.Specifically, when using glass as substrate 100,
Glass top surface can have the coat of metal.Thus, it is possible to the method shape directly deposited by chemical gaseous phase on the coat of metal
Become graphene layer 200, thus be conducive to improving the bond quality between graphene layer 200 and glass substrate, so permissible
Improve the performance of this semiconductor structure.According to embodiments of the invention, when using metal as substrate 100, height can be selected
Temperature alloy forms above-mentioned substrate.Thus, metal substrate on the one hand it is possible to prevent to melt in follow-up pyroprocess, on the other hand
Can alleviate the diffusion in hot environment of the substrate metal element, so the metallic element diffusion that is possible to prevent in substrate and to this
The performance of semiconductor structure adversely affects.According to embodiments of the invention, the upper surface of above-mentioned metal or the coat of metal can
With containing in Ni, Co, Cu, Fe at least one.Concrete, the upper surface of metal or the coat of metal can be containing Ni,
The alloy that one or more in Co, Cu, Fe are formed.Formation graphene layer is had by the alloy containing above-mentioned metallic element urges
Change effect, thus, is conducive to improving the quality of graphene layer 200 utilizing chemical gaseous phase to be deposited thereon formation.According to this
Inventive embodiment, the upper surface of above-mentioned metal or the coat of metal can have texture structure.Thus, it is possible to utilize metal or
On person's coat of metal upper surface, polycrystal distribution of orientations deviates considerably from the texture structure of random distribution, induced synthesis stone thereon
Ink alkene layer 200 also has the most orderly structure, and then can improve the quality of graphene layer 200, in order to obtains and has more
First nitride semiconductor layer 300 of good crystalline quality.The method forming above-mentioned texture structure can be with previously described preparation
The method forming texture structure in the method for semiconductor structure has identical feature and advantage, does not repeats them here.
It should be noted that graphene layer 200 can have and the graphite in the previously described method preparing semiconductor structure
Feature that alkene layer is identical and advantage, do not repeat them here.Thus, it is possible to utilize the ordered structure that graphene layer 200 has,
Induced synthesis the first nitride semiconductor layer 300 thereon forms the structure with crystal preferred orientation, such that it is able to improve
The performance of this semiconductor structure.
According to embodiments of the invention, the particular make-up of the first nitride semiconductor layer 300 can have and previously described system
The feature identical for the first nitride semiconductor layer in the method for semiconductor structure and advantage, do not repeat them here.Such as,
First nitride semiconductor layer 300 can containing AlN, GaN, AlGaN and InGaN at least one.According to this
Bright specific embodiment, can use AlN to form the first nitride semiconductor layer.First nitride semiconductor layer 300 is permissible
Formed by sputtering sedimentation.Generally, the method for sputtering is used to be hardly formed crystal preferred orientation structure, general many formation
Polycrystalline or impalpable structure.Inventor finds through further investigation and great many of experiments, by reducing sputter rate, improving and spatter
The mode such as underlayer temperature when penetrating, or processed by subsequent anneal, improve the crystalline quality of the nitride-based semiconductor that sputtering is formed,
Can realize utilizing sputtering sedimentation to obtain crystal preferred orientation structure on the metallic substrate.Thus, it is possible to ensureing nitride half
While conductor layer quality, reduce preparation cost, simplify preparation technology.Specifically, pulsed sputtering sedimentation shape can be passed through
Become the first nitride semiconductor layer 300.It is for instance possible to use magnetron sputtering deposition or ion beam sputter depositing form the first nitrogen
Compound semiconductor layer 300.Inventor finds through great many of experiments, the speed of the sputtering sedimentation nitride-based semiconductor to being formed
Crystal structure has material impact.Sputtering sedimentation speed advantageously forms the first nitride semiconductor layer 300 slowly.Utilize magnetic control
Sputtering or ion beam sputtering can preferably control sedimentation rate, such that it is able to control the crystal of the nitride-based semiconductor of deposition
Structure, forms the first nitride semiconductor layer.Specifically, according to embodiments of the invention, spattering of sputtering sedimentation can be controlled
Firing rate rate is less than 100nm/ hour；According to other embodiments of the present invention, the sputter rate that can control sputtering sedimentation is less than
30nm/ hour.Inventor finds through great many of experiments, when sputter rate is less than above-mentioned numerical value, it is possible to form crystalline quality relatively
The first high nitride semiconductor layer, sedimentation rate is the lowest, then the preferred orientation of the crystal obtained is the best.According to the present invention's
Embodiment, sputtering sedimentation can also be pulsed sputtering sedimentation or ion beam aided sputtering deposition.Pulsed sputtering sedimentation due to
Have employed the pulse power replaces DC source to carry out sputtering sedimentation, can effectively control deposition velocity, moving of enhanced deposition atom
Move, promote the formation of crystal preferred orientation；Use ion beam aided sputtering deposition, utilize Assisted by Ion Beam to bombard deposition substrate
(i.e. substrate 100), can improve the deposition energy of aggregated particle and stability, eliminates the defect of deposition surface and non-simultaneously
The crystal grain of preferred orientation, is conducive to improving the quality of the first nitride semiconductor layer 300 of formation of deposits.Thus, it is possible to it is sharp
The crystalline of the first nitride semiconductor layer 300 obtained is improved with pulsed sputtering sedimentation or ion beam aided sputtering deposition
Amount.Inventor finds through great many of experiments, and for conventional magnetron sputtering, when depositing the first nitride-based semiconductor, it sinks
Long-pending speed easily reach 1000nm/ hour the highest, be now difficult to obtain and there is the first nitride of preferred orientation partly lead
Body layer, generally requires and utilizes pulsed magnetron sputtering or ion beam aided sputtering deposition technique, its sedimentation rate significantly dropped
As little as less than 100nm/ hour, then it is obtained in that first nitride semiconductor layer with preferred orientation.
According to embodiments of the invention, when sputtering sedimentation, substrate can be heated, make the temperature of substrate 100 more than 300
Degree Celsius.Thus, it is possible to improve the crystalline quality of the first nitride semiconductor layer 300.The temperature of substrate 100 is with front herein
The temperature in the method preparing semiconductor structure that face describes heated substrate is identical, during about sputtering sedimentation enters substrate
The temperature of row heating, is previously detailed description, does not repeats them here.Or, according to other of the present invention
Embodiment, the first nitride semiconductor layer 300 can be formed by sputtering sedimentation and annealing.Specifically, Ke Yi
Complete sputter procedure under room temperature, form nitride mixture, then by the first annealing, improve nitride mixture
Crystalline quality, it is hereby achieved that the first nitride semiconductor layer 300.According to some embodiments of the present invention, the first annealing
The temperature processed can be 600～1200 degrees Celsius.According to other embodiments of the present invention, the temperature of the first annealing is also
Can be 800～1000 degrees Celsius.Thus, it is possible to improve the crystalline quality of the first nitride semiconductor layer further.
According to embodiments of the invention, the half of the XRD diffraction maximum of (0002) crystal face of the first nitride semiconductor layer 300 is high
Wide it is less than 5 degree.Thus, it is possible to ensure that the first nitride semiconductor layer 300 has preferable crystalline quality, such that it is able to fall
Defect in first nitride semiconductor layer 300 of low formation, is conducive to improving utilize this semiconductor structure to prepare all kinds of half
The use function of conductor device.
According to embodiments of the invention, with reference to Fig. 4, this semiconductor structure can further include: the second nitride-based semiconductor
Layer 400.Specifically, the second nitride semiconductor layer 400 is formed at the upper surface of the first nitride semiconductor layer 300.Also
I other words, nitrogenize away from the side formation second of substrate 100 and graphene layer 200 at the first nitride semiconductor layer 300
Thing semiconductor layer 400.According to a particular embodiment of the invention, the second nitride semiconductor layer 400 can contain AlN, GaN,
At least one AlGaN and InGaN.The composition of the second nitride semiconductor layer 400 and the first nitride semiconductor layer 300
Composition differ.Those skilled in the art can select suitable nitridation according to the concrete application demand of this semiconductor structure
Thing semi-conducting material forms the second nitride semiconductor layer 400, if the second nitride semiconductor layer composition and the first nitride
The composition of semiconductor layer differs.Owing to the first nitride semiconductor layer 300 has preferable crystal preferred orientation, because of
When this forms the second nitride semiconductor layer 400 on the first nitride semiconductor layer 300, it is possible to utilize the first nitride half
The preferred orientation of conductor layer 300 induces the formation of the second nitride semiconductor layer 400, makes the second nitride-based semiconductor of formation
Lattice arrangement in layer 400 also has preferred orientation.Additionally, compared with the substrate 100 that metal is formed, the second nitridation
Lattice Matching degree between thing semiconductor layer 400 and the first nitride semiconductor layer 300 is more preferable, therefore at the first nitride
Form the second nitride semiconductor layer on semiconductor layer 300, be conducive to improving the crystallization of the second nitride semiconductor layer 400
Quality.Thus, it is possible to obtain second nitride semiconductor layer 400 with preferred orientation.Second nitride semiconductor layer 400
Concrete forming method and the previously described method preparing semiconductor structure in form the method tool of the second nitride semiconductor layer
There are identical feature and advantage, do not repeat them here.
It should be noted that the previously described semiconductor structure of the present invention can apply to prepare electronic device.Due to this electronics
Containing previously described semiconductor structure in device, therefore this electronic device has the whole special of previously described semiconductor structure
Levy and advantage, do not repeat them here.In simple terms, this electronic device have preparation method easy, with low cost, without
The advantages such as high equipment.Further, the semiconductor structure of this electronic device has the nitride containing crystal preferred orientation half
Conductor layer, such that it is able to improve the integral device performance of this electronic device.It should be noted that in the present invention, electronics device
The concrete kind of part is not particularly limited, and those skilled in the art can select according to the particular make-up in semiconductor structure.
Such as, in the second nitride semiconductor layer containing nitride multilayer thing SQW (include GaN/InGaN/GaN,
AlGaN/InGaN/AlGaN etc.) time, both can be applied to LED structure as luminescent material can also be as light absorbing zone
It is applied to solaode.
Below by specific embodiment, the present invention will be described, it should be noted that following specific embodiment is only to use
In descriptive purpose, and limit the scope of the present invention never in any form, it addition, if no special instructions, the most specifically record
The method of condition or step is conventional method, and the reagent and the material that are used the most commercially obtain.Wherein, raw
Long equipment uses as LAB18 magnetic control sputtering device.
Embodiment 1: nickel base superalloy Grown Graphene, the first nitride-based semiconductor (AlN) layer
Employing nickel base superalloy (GH3536) is as substrate, little by annealing 2 under rolling and 1000 degrees Celsius of blanket of nitrogen
Time, form the high temperature alloy thin slice with texture.This thin slice is cleaned post-drying.
First graphene layer is prepared: put in chemical gas-phase deposition system by this high temperature alloy thin slice, be heated to 1000 degrees Celsius,
Air pressure 200Torr, methane flow 50ml/min, argon flow amount 500ml/min, cool to the most rapidly room temperature, argon during cooling
Throughput 2000ml/min, hydrogen flowing quantity 500ml/min, cooling rate 10 degrees second.At high temperature alloy sheet surface after cooling
Obtain graphene layer.
Then utilizing magnetron sputtering deposition the first nitride semiconductor layer AlN, Al is sputtering target material, carries out in a nitrogen atmosphere
Deposition.In advance substrate is carried out before deposition.
Strobe pulse magnetron sputtering, sputtering power 300W, the dutycycle of the pulse power is 0.05, vacuum 1E-7Torr, spatters
Penetrate Ar Pressure 10mtorr, underlayer temperature 450 degrees Celsius, control about speed of growth 30nm/h.Obtain nitride-based semiconductor
Layer thickness is 30nm.Subsequently, the thin film obtaining sputtering carries out making annealing treatment under blanket of nitrogen, annealing temperature 1000 degrees Celsius,
Annealing time 2 hours.
By showing the XRD analysis of the AlN obtained, the halfwidth at its (0002) peak is 1.2 degree, illustrates that AlN has
There is preferable crystal preferred orientation.
Embodiment 2: growth regulation mononitride quasiconductor (AlN) layer and the second nitride-based semiconductor (GaN) in metal substrate
Layer
The step of growing AIN the first nitride semiconductor layer with embodiment 1, except that, utilize sputtering acquisition first
After nitride semiconductor layer, continuing with pulsed magnetron sputtering technique, GaN is sputtering target material, enters in a nitrogen atmosphere
Row deposition.Sputtering power 300W, the dutycycle of the pulse power is 0.05, vacuum 1E-7Torr, Sputtering Ar Pressure 10mtorr,
Underlayer temperature 600 degrees Celsius, controls about speed of growth 30nm/h.Obtaining nitride semiconductor layer thickness is 30nm.With
After, the thin film obtaining sputtering carries out making annealing treatment under blanket of nitrogen, annealing temperature 1000 degrees Celsius, annealing time 2 hours.
By showing the XRD analysis of the GaN obtained, the halfwidth at its (0002) peak is 1.8 degree, illustrates that GaN has
There is preferable crystal preferred orientation.
In the description of this specification, reference term " embodiment ", " some embodiments ", " example ", " concrete example ",
Or specific features, structure, material or the feature bag that the description of " some examples " etc. means to combine this embodiment or example describes
It is contained at least one embodiment or the example of the present invention.In this manual, to the schematic representation of above-mentioned term necessarily
It is directed to identical embodiment or example.And, the specific features of description, structure, material or feature can be arbitrary
Individual or multiple embodiment or example combine in an appropriate manner.Additionally, in the case of the most conflicting, the skill of this area
The feature of the different embodiments described in this specification or example and different embodiment or example can be combined by art personnel
And combination.
Additionally, in the present invention, term " first ", " second " are only used for describing purpose, and it is not intended that indicate or dark
Show relative importance or the implicit quantity indicating indicated technical characteristic.Thus, " first ", " second " are defined
Feature can express or implicitly include at least one this feature.
Although above it has been shown and described that embodiments of the invention, it is to be understood that above-described embodiment is exemplary,
Being not considered as limiting the invention, those of ordinary skill in the art within the scope of the invention can be to above-described embodiment
It is changed, revises, replaces and modification.
Claims (20)
1. the method preparing semiconductor structure, it is characterised in that including:
(1) substrate is provided；
(2) surface configuration graphene layer over the substrate；And
(3) upper surface at described graphene layer passes through sputtering sedimentation, forms the first nitride semiconductor layer, in order to obtain institute
Stating semiconductor structure, described first nitride semiconductor layer has crystal preferred orientation.
Method the most according to claim 1, it is characterised in that step (3) farther includes:
Form nitride-based semiconductor mixture by sputtering sedimentation at the upper surface of described graphene layer, described nitride is partly led
Body mixture carries out the first annealing, in order to obtain described first nitride semiconductor layer.
Method the most according to claim 1 and 2, it is characterised in that farther include:
(4) the second nitride semiconductor layer is formed at described first nitride semiconductor layer away from the side of described graphene layer,
Described second nitride semiconductor layer has crystal preferred orientation.
Method the most according to claim 3, it is characterised in that farther include:
(5) described substrate, described graphene layer, described first nitride semiconductor layer and described second nitride are partly led
Body layer carries out the second annealing.
Method the most according to claim 1, it is characterised in that described first nitride semiconductor layer contain AlN, GaN,
At least one AlGaN and InGaN.
Method the most according to claim 3, it is characterised in that described second nitride semiconductor layer contain AlN, GaN,
At least one AlGaN and InGaN, described second nitride semiconductor layer composition and described first nitride semiconductor layer
Composition differ.
Method the most according to claim 1, it is characterised in that described substrate is formed by glass or metal；
Optionally, described glass top surface has the coat of metal；
Optionally, described metal includes high temperature alloy.
Method the most according to claim 7, it is characterised in that the upper surface of described metal or the described coat of metal contains
At least one in Ni, Co, Cu and Fe.
Method the most according to claim 7, it is characterised in that the upper epidermis tool of described metal and the described coat of metal
There is texture structure.
Method the most according to claim 1, it is characterised in that described graphene layer contains 1～10 layer graphene monolayers.
11. methods according to claim 1, it is characterised in that described sputtering sedimentation is magnetron sputtering deposition or ion
Beam sputter-deposition；
Optionally, described sputtering sedimentation is pulsed sputtering sedimentation or ion beam aided sputtering deposition；
Optionally, the sputter rate of described sputtering sedimentation is less than 100nm/ hour.
Optionally, during described sputtering sedimentation, underlayer temperature is not less than 300 degrees Celsius.
12. according to the method described in claim 2 or 4, it is characterised in that described first annealing and described second
Annealing temperature independently for 600～1200 degrees Celsius.
13. 1 kinds of semiconductor structures, it is characterised in that including:
Substrate；
Graphene layer, described graphene layer is arranged on the upper surface of described substrate；With
First nitride semiconductor layer, described first nitride semiconductor layer is formed at the upper surface of described graphene layer, and
Described first nitride semiconductor layer has crystal preferred orientation.
14. semiconductor structures according to claim 13, it is characterised in that described substrate is to be formed by glass or metal
's；
Optionally, described metal includes high temperature alloy；
Optionally, described glass top surface has the coat of metal；
Optionally, the upper surface of described metal and the described coat of metal contains at least one of Ni, Co, Cu, Fe；
Optionally, the upper epidermis of described metal and the described coat of metal has texture structure.
15. semiconductor structures according to claim 13, it is characterised in that described first nitride semiconductor layer contains
At least one AlN, GaN, AlGaN and InGaN.
16. semiconductor structures according to claim 13, it is characterised in that farther include:
Second nitride semiconductor layer, described second nitride semiconductor layer be formed at described first nitride semiconductor layer away from
The side of described graphene layer, described nitride semiconductor layer has crystal preferred orientation；
Optionally, described second nitride semiconductor layer contain AlN, GaN, AlGaN and InGaN at least one,
Described second nitride semiconductor layer composition differs with the composition of described first nitride semiconductor layer.
17. semiconductor structures according to claim 13, it is characterised in that described first nitride semiconductor layer (0002)
The halfwidth of the XRD diffraction maximum of crystal face is less than 5 degree.
18. semiconductor structures according to claim 13, it is characterised in that described first nitride semiconductor layer is logical
Cross what sputtering sedimentation was formed；
Optionally, described first nitride semiconductor layer is formed by sputtering sedimentation and annealing.
19. semiconductor structures according to claim 16, it is characterised in that described second nitride semiconductor layer is logical
Cross what sputtering sedimentation was formed；
Optionally, described second nitride semiconductor layer is formed by sputtering sedimentation and annealing.
20. according to the semiconductor structure described in claim 18 or 19, it is characterised in that described sputtering sedimentation is that magnetic control spatters
Penetrate deposition or ion beam sputter depositing；
Optionally, described sputtering sedimentation is pulsed sputtering sedimentation or ion beam aided sputtering deposition；
Optionally, during described sputtering sedimentation, underlayer temperature is more than 300 degrees Celsius；
Optionally, the sputter rate of described sputtering sedimentation is less than 100nm/ hour.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610365953.7A CN105914258B (en) | 2016-05-27 | 2016-05-27 | Semiconductor structure and the method for preparing semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610365953.7A CN105914258B (en) | 2016-05-27 | 2016-05-27 | Semiconductor structure and the method for preparing semiconductor structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105914258A true CN105914258A (en) | 2016-08-31 |
| CN105914258B CN105914258B (en) | 2018-06-22 |
Family
ID=56742730
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610365953.7A Active CN105914258B (en) | 2016-05-27 | 2016-05-27 | Semiconductor structure and the method for preparing semiconductor structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105914258B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110323308A (en) * | 2019-06-06 | 2019-10-11 | 北京大学 | A method of nitride vertical structure LED is prepared using graphene barrier layer |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102050442A (en) * | 2009-11-10 | 2011-05-11 | 三星电子株式会社 | Methods of fabricating graphene using alloy catalyst |
| CN104409319A (en) * | 2014-10-27 | 2015-03-11 | 苏州新纳晶光电有限公司 | Preparation method for growing high-quality GaN buffer layer on graphene substrate |
-
2016
- 2016-05-27 CN CN201610365953.7A patent/CN105914258B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102050442A (en) * | 2009-11-10 | 2011-05-11 | 三星电子株式会社 | Methods of fabricating graphene using alloy catalyst |
| CN104409319A (en) * | 2014-10-27 | 2015-03-11 | 苏州新纳晶光电有限公司 | Preparation method for growing high-quality GaN buffer layer on graphene substrate |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110323308A (en) * | 2019-06-06 | 2019-10-11 | 北京大学 | A method of nitride vertical structure LED is prepared using graphene barrier layer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105914258B (en) | 2018-06-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100352004C (en) | Substrate for growing gallium nitride, itsproducing method and method for preparing gallium nitride substrate | |
| CN104781938B (en) | Multi-layer substrate structure and the method and system for manufacturing it | |
| Choi et al. | One-step graphene coating of heteroepitaxial GaN films | |
| CN103774113A (en) | Method for preparing hexagonal boron nitride film | |
| CN101378015A (en) | Group III nitride semiconductor and a manufacturing method thereof | |
| WO2013158210A2 (en) | Heterogeneous material integration through guided lateral growth | |
| CN106661761B (en) | Aluminum oxide substrate | |
| CN109585270A (en) | Method and structure based on amorphous substrate growing nitride | |
| WO1998059099A1 (en) | SINGLE CRYSTAL SiC AND PROCESS FOR PREPARING THE SAME | |
| US8029924B2 (en) | Thin film template for fabrication of two-dimensional quantum dot structures | |
| CN105914258A (en) | Semiconductor structure and preparation method thereof | |
| CN106057641A (en) | Semiconductor structure and method for preparing semiconductor structure | |
| Meng et al. | A simple growth route towards ZnO thin films and nanorods | |
| CN106024584A (en) | Semiconductor structure and method for preparing semiconductor structure | |
| KR102106781B1 (en) | Single-crystal metal thin film and preparing method thereof | |
| CN106057642A (en) | Semiconductor structure and method for preparing semiconductor structure | |
| CN106024972B (en) | Semiconductor structure, the method and its application for preparing semiconductor structure | |
| CN105977136A (en) | Semiconductor structure and method for preparing the same | |
| Xiao et al. | Annealing effects on the formation of semiconducting Mg2Si film using magnetron sputtering deposition | |
| CN106057640A (en) | Semiconductor structure and method for preparing semiconductor structure | |
| JP4747330B2 (en) | Preparation of rutile type titanium oxide single crystal thin film | |
| KR102063746B1 (en) | Three-dimensional structured transition metal dichalcogenide wire and method for preparing the same | |
| CN106057643A (en) | Semiconductor structure and method for preparing semiconductor structure | |
| KR102170111B1 (en) | Single crystalline film by abnormal grain growth of polycrystalline metal fim and preparation method thereof | |
| Masenya et al. | The effects of the thickness of the sandwiched layer and of the annealing time on induced nanostructures during solid state dewetting of a metal-semiconductor-substrate triple layer structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |