CN105895611A - 具有可湿性侧面的无引线方形扁平半导体封装 - Google Patents

具有可湿性侧面的无引线方形扁平半导体封装 Download PDF

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CN105895611A
CN105895611A CN201410858226.5A CN201410858226A CN105895611A CN 105895611 A CN105895611 A CN 105895611A CN 201410858226 A CN201410858226 A CN 201410858226A CN 105895611 A CN105895611 A CN 105895611A
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CN105895611B (zh
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白志刚
庞兴收
许南
姚晋钟
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NXP USA Inc
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Freescale Semiconductor Inc
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Abstract

本发明涉及具有可湿性侧面的无引线方形扁平半导体封装(QFN)。无引线方形扁平半导体封装具有安装到引线框的管芯标记上的半导体管芯。具有底部和侧面的模制的壳体覆盖管芯。该封装具有导电安装脚，其中每个导电安装脚包括在壳体的底部中暴露的底部表面、被壳体覆盖的相对平行表面、以及在壳体的一侧中的暴露的端面。该暴露的端面垂直于暴露的底部表面和相对的平行表面，并位于它们之间。接合线选择性地将半导体管芯的各电极电连接到相应的脚。导电镀层涂覆安装脚的暴露的底部部分以及暴露的端面。

Description

具有可湿性侧面的无引线方形扁平半导体封装
技术领域
本发明一般涉及半导体封装，并且，特别地，涉及一种具有可湿性侧面的无引线方形扁平(QFN)封装。
背景技术
半导体集成电路的尺寸不断的减小，并且存在更小和更密集电路的相应要求。同时，期望这种电路能提供相同或更多的输入和输出。一些类型的半导体封装具有壳体，引线或引线指从该壳体突出。引线指被用于将半导体封装与外部电路互连。这种封装可具有巨大的占用面积，并且引线指增加了封装高度。
作为具有突出的引线指的封装的替代，开发了一种无引线方形扁平(QFN)封装，其中该无引线方形扁平(QFN)封装包括暴露的接触垫或端子，该接触垫或端子在由被安装到引线框的半导体管芯形成的矩形半导体封装的下面或四侧上。引线框由金属板形成，金属板包括通常被称为标记的管芯粘附垫和将标记粘附到框架的臂(系杆)。用接合线将引线框的下置引线电连接到管芯的电极。在线接合之后，半导体管芯和焊垫被包封在塑料化合物(材料)中，而仅留下引线的下侧部分被暴露。包封的半导体管芯和焊垫形成与板的部分完全的封装集成。部分完全的封装然后被从板切割(通常称为分割工艺)，以形成矩形封装，在引线的下侧部分的地方提供临近封装的四侧的接触垫。
引线框典型的包括使用类似钯的材料进行预先电镀的铜，以阻止铜的氧化。但是，当装置被分割时，引线的侧面被切割，这就移除了预先电镀的钯。这将导致引线的末端容易发生氧化。这还使得当安装该装置到印刷线路板时，焊接更加困难。使用QFN封装将是非常有利的，其能改善焊接点连接的质量。
附图说明
本发明，连同其目的和优点，通过参考下文中配合附图的优选实施例的描述，将更加容易理解，其中：
图1是依据本发明的一个实施例的组装引线框板组件的顶视图；
图2是图1中组装引线框板组件穿过2-2′的横截面侧视图；
图3是由图1的组装引线框板组件形成的组装容纳引线框板组件的下侧平面视图；
图4是图3中组装容纳引线框板组件穿过4-4′的横截面侧视图；
图5依据本发明的优选实施例，由图3的组装容纳引线框板组件形成的部分分开的板组件的下侧平面视图；
图6是依据本发明的优选实施例，图5的部分分开的板组件穿过6-6′的横截面侧视图；
图7是依据本发明的优选实施例，电镀底座阵列的安装板的顶视图。
图8是图7的安装板穿过8-8′的横截面图；
图9是依据本发明的优选实施例，将图5的部分分开的板组件安装到图7的安装板的相应电镀底座上的组合组件的侧视图；
图10是依据本发明的优选实施例的无引线方形扁平(QFN)半导体封装的侧视图；以及
图11是依据本发明的优选实施例的装配无引线方形扁平(QFN)半导体封装的方法的流程图。
具体实施方式
意图将以下结合附图给出的详细说明作为对本发明的当前优选实施例的说明，并不意味着其代表可以实施本发明的仅有形式。应该理解，通过意图包含在本发明的精神和范围内的不同实施例可以实现相同或等价的功能。在所有附图中，使用相同的标号表示相同的要素。此外，术语“包括”、“包含”或它的任何其它变体都意图涵盖非排他的包括，使得包括一系列要素或步骤的模块、电路、装置组件、结构及方法步骤不仅包括那些要素，而且还可以包括没有明确列出的或者这些模块、电路、装置组件或步骤固有的其他要素或步骤。由“包括一个...”引导的要素或步骤在没有更多约束的情况下，不排除包括该要素或步骤的额外相同要素或步骤的存在。
在一个实施例中，本发明提供包括安装到管芯标记上的半导体管芯的无引线方形扁平(QFN)半导体封装。具有覆盖半导体管芯和管芯标记的壳体。该壳体具有底部(base)和侧面，并且存在围绕管芯标记的导电安装脚(即，引线或引线指)。每个安装脚包括在壳体的底部中暴露的底部表面、被壳体覆盖的相对的平行表面、以及在壳体的一个侧面中中暴露的端面。暴露的端面垂直于暴露的底部表面和相对的平行表面，并位于它们之间。接合线选择性地将半导体管芯的各电极电连接到安装脚的相应一个，并且导电镀层涂覆暴露的端面。
在另一个实施例中，本发明提供装配QFN半导体封装的方法。该方法包括提供装配QFN半导体封装的组装容纳引线框板组件。每个封装是由引线框形成，其中引线框包括围绕管芯标记的包围框架。具有从包围框架向内延伸并支撑管芯标记的系杆。导电安装脚围绕管芯标记并从包围框架向内延伸。具有安装到管芯标记上的半导体管芯。接合线选择性地将半导体管芯的各电极电连接到安装脚的相应一个。存在具有底部和侧面的壳体。该壳体覆盖半导体管芯并部分覆盖管芯标记和安装脚，以致安装脚的每一个包括在壳体的底部中暴露的底部表面和被壳体覆盖的相对的平行表面。提供组装的容纳引线框板组件之后，该方法执行将每一个封装彼此部分分开，以提供部分分开的封装的部分分开的板组件。通过移除包围框架的多个段以暴露壳体侧面中的每个导电安装脚的端面，执行部分分开，其中暴露的端面垂直于暴露的底部表面和相对的平行表面，并位于它们之间。该方法执行将每个部分分开的封装安装到各自的电镀底座，电镀底座具有电绝缘主体，其中电绝缘主体具有被定位为沿电绝缘主体的外周边缘的导电杆。导电杆与被定位为沿外周边缘的安装脚电互连。该方法然后执行用导电镀层涂敷每个安装脚的暴露的端面。
现在参考图1，这里图解了组装引线框板组件100的顶视图。该组装的引线框架板组件100包括典型的基于铜(涂有用于焊接接头相容性的导电镀层)的导电板102，其中具有形成在板102上的引线框104阵列。一般通过切割或冲压工艺将引线框104形成在板102中，每个引线框104包括围绕相应管芯标记108(引线框标记)的包围框架106。
系杆110从每个包围框架106向内延伸，并支撑与各框架106关联的管芯标记108。每个引线框104具有从相应包围框架106朝着管芯标记108向内延伸的导电安装脚112，其中管芯标记108被该相应包围框架106封闭。并且，在每个管芯标记108上安装相应半导体管芯120，接合线122选择性将每个半导体管芯120的电极124电连接到安装脚112的相应一个。在一个实施例中，引线框架由类似铜的导电金属形成，并被用类似钯的保护材料镀敷。
参考图2，这里图解了组装引线框板组件100穿过2-2′的横截面侧视图。如所示，安装脚112的下侧表面202和每个管芯标记108的下侧表面204共平面，如平面P1所示。
参考图3，这里图解的是组装的容纳引线框板组件300的下侧平面视图，由组装的引线框板组件100形成的组装的扁平无引线半导体封装302。组装的容纳引线框板组件300包括由模制化合物形成的、用于每一个集成的扁平无引线半导体封装302的壳体304，并且每个壳体302典型地由模制包封材料形成。
图4图解了由组装引线框板组件100组成的组装容纳引线框板组件400穿过4-4′的横截面侧视图。如所示，用于每个封装302的壳体304具有底部402，并且壳体覆盖相应的半导体管芯120以及部分覆盖安装脚112，使得每一个安装脚112包括在壳体304的底部406中暴露的底部表面406(下侧表面202)和被壳体304覆盖的相对的平行表面408。管芯标记108的下侧表面204同样被暴露在壳体304的底部402中，并如上述提及的，暴露的底部表面406(下侧表面202)和下侧表面204共平面，如平面P1所示。
参考图5，图解了依据本发明的优选实施例，由组装容纳引线框板组件300形成的部分分开的板组件500的下侧平面视图。部分分开的板组件500包括通过移除包围框架106以提供间隙504(可以在壳体302中形成沟槽)而形成的部分分开的封装502。在这个实施例中，包围框架的所有段都被移除，但是在其他实施例中，框架的拐角区域仍然保留。每个这些间隙504暴露了每个导电安装脚112的端面506。这样，每个暴露的端面506垂直于相应暴露的底部表面406和相对的平行表面408，并位于它们之间。
参考图6，图解了部分分开的板组件500穿过6-6′的横截面侧视图。在这个实施例中，间隙504轻微延伸进入壳体304，以在壳体302中形成沟槽。
参考图7，图解了依据本发明的优选实施例的电镀底座702阵列的安装板700的顶平面视图。安装板700包括电绝缘主体704(典型的基于橡胶或塑料)，该电绝缘主体704具有被定位为沿每个电镀底座702的***边缘708的导电杆706。因而，导电杆706形成了***框710用于电镀底座702的相应一个。如所示，每个电镀底座702包括将电镀底座702的相应一个的各导电杆706耦接在一起的互连长条712。
每个***框架710包括封入到主体704中的凹入的拐角区域714，并且在这个平面视图中，互连长条712形成十字，其中十字的至少一个中央交叉区域716是凹入的。但是，如在实施例中描述的，所有互连长条712的全部段相对于***框架710是凹入的，且被封入到主体704中。在电镀底座702的每一个之间是具有定义***边缘708的细长表面的缝或间隙720。同样，作为主体704的一部分的互连桥722位于凹入的拐角区域714，且与临近底座702耦接在一起。
参考图8，图解了安装板700穿过8-8′的横截面侧视图，显示了凹入的拐角区域714和凹入的互连长条712中的一个。
图9显示了依据本发明的优选实施例，部分分开的板组件500(部分分开的封装502)安装到安装板700的相应电镀底座的结合组件900的侧视图。当这样安装的每个导电杆706与相应部分分开的封装502的***边缘对准时，从而每个导电杆706与沿相应***边缘708的每个安装脚112的暴露的底部表面406邻接并覆盖该暴露的底部表面406。
参考图10，图解了依据本发明的优选实施例的QFN半导体封装1000的侧视图。该QFN半导体封装1000是通过对结合的组件900执行电镀工艺，然后移除安装脚700并将独立封装502彼此完全分离而形成的。
该QFN半导体封装1000包括安装到管芯标记108上的半导体管芯120。该壳体304覆盖半导体管芯120，并且具有导电镀层1002，其覆盖每个导电安装脚112暴露的端面506。该安装脚112临近壳体3024的每一个侧面，从而封装1000是每个暴露的端面506与壳体304的侧面1004的相应一个平行的QFN封装。导电镀层100典型的是基于锡的化合物，其使得暴露的底部表面406以形成焊接点的一部分。
参考图11，图解了依据本发明的优选实施例的制造无引线方形扁平半导体封装的方法1100的流程图。该方法1100，在框1110，开始于提供装配的QFN半导体封装302的组装容纳引线框板组件300。在框1120，执行每个封装302的彼此部分分开，以提供部分分开的封装502的部分分开的板组件500。然后，该方法1100在框1130执行将每个部分分开的封装502安装到安装板700的相应电镀底座702。
在框1140，执行使用导电镀层1002涂覆每个安装脚112暴露的端面506的工艺。该涂覆是通过电镀工艺执行，其中一个涂覆电极被耦接到导电杆706，该导电杆706被电耦接到安装脚112。因而在电镀工艺期间，当有电流穿过导电杆706并到达安装脚112时，这些电连接便于暴露的端面506的涂覆。
在拆卸框1150，执行将部分分开的封装502从其相应的电镀底座702拆卸的工艺。然后，该方法1100在框1160通过壳体304的锯开或切割工艺，执行每个封装的彼此完全分开，以提供QFN半导体封装1000。
有益地，本发明为提供用于涂覆暴露的端面506，从而为安装脚112提供合适的额外焊接点表面。这从而改进了安装脚112和电路板的安装焊垫之间的焊接点连接的质量。
为了图解和描述的目的给出了对本发明的优选实施例的描述，但是该描述并不意味着是详尽的或者将本发明限制到所公开的形式。本领域的技术人员将意识到，在不偏离本发明的宽泛发明概念的情况下，可以对上述实施例进行变化。因此，应该理解，本发明不局限于所公开的具体实施例，而是覆盖如所附权利要求限定的本发明的精神和范围内的修改。

Claims (10)

1.一种无引线方形扁平QFN半导体封装，包括：
安装到引线框的管芯标记上的半导体管芯；
覆盖半导体管芯以及管芯标记的至少一部分的壳体，其中壳体具有底部和侧面；
围绕管芯标记的导电脚，其中每个脚包括在壳体的底部中暴露的底部表面、被壳体覆盖的相对的平行表面、以及在壳体的一侧中暴露的端面，该暴露的端面垂直于暴露的底部表面和相对的平行表面，并位于暴露的底部表面和相对的平行表面之间；
接合线，选择性地将半导体管芯的各电极电连接到相应的脚；以及
涂覆脚的暴露的底部表面的第一导电镀层；以及
涂覆脚的暴露端面的第二导电镀层，其中第二导电镀层不同于第一导电镀层。
2.如权利要求1所述的QFN半导体封装，其中第一导电镀层包括钯。
3.如权利要求2所述的QFN半导体封装，其中第二导电镀层包括锡。
4.如权利要求1所述的QFN半导体封装，其中暴露的底部部分与壳体的底部平行。
5.如权利要求1所述的QFN半导体封装，其中壳体由模制化合物形成。
6.如权利要求1所述的QFN半导体封装，其中脚被定位为临近壳体的每一侧。
7.一种装配无引线方形扁平QFN半导体封装的方法，该方法包括：
提供装配的QFN半导体封装的组装容纳引线框板组件，其中每个封装由包括围绕管芯标记的包围框架的引线框形成，系杆从包围框架向内延伸并支撑管芯标记，导电脚从包围框架向内延伸，并且其中半导体管芯安装到管芯标记上，接合线选择性地将半导体管芯的各电极电连接到相应的脚，壳体具有底部和侧面，壳体覆盖半导体管芯、标记并部分覆盖脚，以使得每个脚包括在壳体底部中暴露的底部表面和被壳体覆盖的相对平行表面；
将每个封装彼此部分分开，以提供部分分开的封装的部分分开的板组件，通过移除包围框架的多个段以暴露壳体侧面中的每个导电脚的端面来执行部分分开，其中暴露的端面垂直于暴露的底部表面和相对的平行表面，并位于暴露的底部表面和相对的平行表面之间；
将每个部分分开的封装安装到相应的电镀底座，电镀底座具有电绝缘主体，其中电绝缘主体具有位于沿电绝缘主体的外周边缘的导电杆，且其中导电杆与被定位为沿外周边缘的安装脚电互连；以及
使用导电镀层镀敷每个脚的暴露的端面。
8.如权利要求7所述的方法，其中镀敷包括电镀工艺，在电镀工艺中电流穿过导电杆。
9.如权利要求7所述的方法，进一步包括将每个封装彼此完全分开，以提供QFN半导体封装。
10.如权利要求7所述的方法，其中引线框包括涂覆了铜的钯，并且导电镀层材料包括锡。
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