CN104979322A - 半导体管芯封装及其组装方法 - Google Patents

半导体管芯封装及其组装方法 Download PDF

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CN104979322A
CN104979322A CN201410145465.6A CN201410145465A CN104979322A CN 104979322 A CN104979322 A CN 104979322A CN 201410145465 A CN201410145465 A CN 201410145465A CN 104979322 A CN104979322 A CN 104979322A
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external connector
lead
connector pins
semiconductor die
package according
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CN104979322B (zh
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白志刚
王志杰
姚晋钟
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NXP USA Inc
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Freescale Semiconductor Inc
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Abstract

半导体管芯封装由具有引线指的引线框架组装,该引线指具有邻近管芯标记的接合端和从所述管芯标记延伸出的伸长区域。将半导体管芯安装在管芯标记上并且用接合线将半导体管芯的电极电连接至接合端。将每个伸长区域弯曲成具有安装脚的外部连接器引线。引线指中的每一个的伸长区域从由模塑化合物形成的外壳伸出。模塑化合物从外壳延伸出以提供模制至外部连接器引线的绝缘支撑指。

Description

半导体管芯封装及其组装方法
背景技术
本发明通常涉及半导体管芯封装,并且更具体地涉及具有绝缘外引线或者支撑指的半导体管芯封装。
半导体管芯封装提供合适的外部电连接以及半导体管芯免受机械和环境应力的保护。半导体管芯尺寸的减小的持续发展和在管芯中形成的电路的增加的功能性和复杂度需要封装的尺寸减小。
半导体管芯封装的一个典型类型是四方扁平封装(QFP),其形成有安装至引线框架的半导体管芯。引线框架由具有管芯连接焊盘(常常称作标记)的金属片和将标记连接至框架的支柱组成。引线框架具有围绕标记的引线指。用接合线将管芯的电极连接至引线指的近端,以提供容易将管芯电连接至电路板等的装置。在电极与焊盘连接之后,半导体管芯和接合线被封装在模塑化合物中,仅使部分引线指暴露。为了便于至电路板的连接,将这些暴露的或者外部的引线从引线框架的框架上切下(切单)并且弯曲。
QFP封装的固有结构和尺寸导致外部引线的数量受到限制,并且因此限制了能够用于特定QFP封装尺寸的封装外部电连接的数量。然而,可以减小引线宽度和引线间距以允许增加的引线数量。这种间距的减小可能引起内引线短路并且减小的引线宽度可能导致相对细的引线变形或者弯曲。因此,减小引线间距并且同时减小内引线短路的风险将是有利的。
附图说明
通过结合附图参考以下对优选实施例的说明,可以最好地理解本发明及其目的和优点,其中:
图1是根据本发明第一实施例的引线框架片的部分平面视图;
图2是在半导体管芯填充之后,作为图1的引线框架片的一部分的引线框架组件的平面图;
图3是由图2的引线框架组件组成的线接合的引线框架组件的平面图;
图4是穿过图3的线接合的引线框架组件的4-4’的横截面侧视图;
图5是根据本发明第一实施例当夹持图3的线接合的引线框架组件时模制和成形夹具的横截面侧视图;
图6是根据本发明第一实施例的半导体管芯封装的侧视图;
图7是图6的半导体管芯封装的平面图;
图8是根据本发明第二实施例当夹持图3的线接合的引线框架组件时模制和成形夹具的横截面侧视图;
图9是根据本发明第二实施例的半导体管芯封装的侧视图;
图10是图9的半导体管芯封装的平面图;
图11是根据本发明第三实施例当夹持图3的线接合的引线框架组件时模制和成形夹具的截面侧视图;
图12是根据本发明第三实施例的半导体管芯封装的侧视图;
图13是图11的半导体管芯封装的平面图;
图14是根据本发明第四实施例的引线框架片的部分平面视图;
图15是根据本发明第五实施例的一组安装脚的端视图;
图16是根据本发明的实施例图示组装半导体管芯封装的方法的流程图。
优选实施例的详细说明
下面结合附图所阐述的详细描述旨在描述本发明的现有优选实施例,并不旨在代表本发明可被实现的唯一形式。应当理解,可以通过不同实施例实现的相同或等效的功能,这些实施例也旨在包括在本发明的精神和范围之内。在全文中相同的标号用于表示相似的元件。而且,术语“包括”或其任何其它变形旨在覆盖非排他性的包括,使得包括一系列元件或步骤的模块、电路、设备组件、结构和方法步骤并不仅包括这些元件,还可以包括未明确列出的或固有的这种模块、电路、设备组件或步骤。前加“包括一”的元件或步骤并不排除(但不作更多限制)包括所述元件或步骤的其它相同要素或步骤的存在。
在一个实施例中,本发明提供包括管芯标记和围绕该管芯标记的引线指的半导体管芯封装。引线指中的每一个具有邻近管芯标记的接合端和从管芯标记延伸出的伸长区域。半导体管芯被安装在管芯标记上并且接合导线将管芯的电极电连接至引线指中的每一个的接合端。模塑化合物形成覆盖管芯、接合导线、引线指的接合端和管芯标记的外壳。引线指中的每一个的伸长区域从外壳伸出以提供用于封装的外部连接器引线。模塑化合物从外壳延伸出以提供模制至外部连接器引线的绝缘支撑指。
在另一个实施例中,本发明提供组装半导体管芯封装的方法。本发明包括提供具有围绕管芯标记的围绕框架的引线框架。引线框架具有从围绕框架向内延伸并且支撑管芯标记的连接杆,并且有围绕管芯标记的引线指,每个引线指具有邻近管芯标记的接合端和朝外框架延伸远离管芯标记的伸长区域。外档杆桥接伸长区域的相邻自由端并且内挡杆从***绕框架支撑引线指。内挡杆为除了相邻伸长区域之间的区域之外的周边定义了外部周边封装外壳轮廓。方法还包括将半导体管芯安装在半导体管芯标记上并且用接合导线将半导体管芯的电极电连接至引线指中的每一个的接合端。还执行将每个伸长区域成形为在其自由端处具有安装脚的外部连接器引线。引线指中的每一个的伸长区域从外壳伸出以提供用于封装的外部连接器引线。在模制工序期间,模塑化合物中的一些从相邻的外部连接器引线之间的模腔流出以提供模制到外部连接器引线的绝缘支撑指。
在另一个实施例中,本发明提供在其中形成有引线框架阵列的引线框架片。引线框架中的每一个包括围绕管芯标记的围绕框架和从围绕框架向内延伸并且支撑管芯标记的连接杆。引线框架中的每一个还包括围绕管芯标记的引线指,每个引线指具有邻近管芯标记的接合端和朝外框架延伸远离管芯标记的伸长区域。外挡杆桥接伸长区域的相邻自由端并且内挡杆从***绕框架支撑引线指。内挡杆为除了相邻伸长区域之间的区域之外的周边定义了外部周边封装外壳轮廓。
现在参考图1,示出了根据本发明第一实施例的引线框架片100的部分平面图。引线框架片100通常由金属(例如铜)形成并且因此既导热又导电。引线框架片100具有阵列中的多个引线框架102并且引线框架102通常通过冲压或者切割出引线框架片100的区域来形成。引线框架102中的每一个具有围绕位于中心的管芯标记106的***绕框架104,该管芯标记106由围绕框架104支撑。
引线框架102中的每一个还包括围绕管芯标记106的引线指108,所述引线指108各自具有邻近管芯标记106的接合端110和朝***绕框架104延伸远离管芯标记106的伸长区域。各个外档杆114桥接伸长区域112的相邻自由端并且与内挡杆116结合从***绕框架104支撑引线指108。在本实施例中,内挡杆116不桥接引线指108两端并且如对本领域技术人员清楚的是还有提供附加支撑的伪引线118。
在本实施例中,有从围绕框架104向内延伸并且支撑管芯标记106的连接杆120。连接杆120各自具有角形截面122,该角形截面122被弯曲使得在管芯标记106与围绕框架104之间形成下置关系。
图2是在半导体管芯填充之后,作为引线框架片100的一部分的引线框架组件200的平面图。具有用于外部连接的电极204的半导体管芯202安装至管芯标记106。
图3是由引线框架组件200组成的线接合的引线框架组件300的平面图。线接合的引线框架组件300包括将半导体管芯202的电极204电连接至引线指108中的每一个的接合端110的接合线302。此外,虚线所示为由将在下面描述的模塑化合物形成的封装外壳轮廓304的周边。封装外壳轮廓304以内挡杆116为边界,然而,内挡杆116不桥接引线指108两端。因此,如将在下面描述的,在相邻的引线指108之间提供外壳模制出口306。
图4是穿过线接合的引线框架组件300的4-4’的横截面侧视图。在本图示中,示出了在管芯标记106与围绕框架104之间的下置关系。还示出了与***绕框架104共面的引线指108的伸长区域112。
图5是根据本发明第一实施例当夹持线接合的引线框架组件300时模制和成形夹具500的横截面侧视图。夹具500包括砧座502和互补的上部构件504A、504B,其中砧座502和上部构件504A共同形成外壳模制腔506。夹具500还具有共同作用的内档杆夹持构件508、510和由砧座502和构件504B形成的共同作用的引线指成形(再成形)表面512、514。上部构件504A、504B相对于彼此可移动,以便最初将砧座502和上部构件504A集合在一起以形成外壳模制腔506,在该外壳模制腔506中,为了稍后封装外壳轮廓304的成形,内档杆夹持构件508、510夹持内挡杆116。一旦夹持内挡杆116,上部构件504B朝砧座502移动,以便表面512、514共同作用以弯曲(形成)引线指108的伸长区域112。此外,表面512、514、外挡杆114和相邻伸长区域112之间的间隔形成可通过外壳模制出口306从外壳模制腔506到达的外部模制腔516。
在操作中,模塑化合物沉积到外壳模制腔506中以覆盖半导体管芯202、接合线302、引线指108的每个接合端110和管芯标记106。此外,在模制期间,一部分模塑化合物穿过外壳模制出口306流入外壳模制腔506中并且流到外部模制腔516中。
参照图6和7,示出了根据本发明第一实施例半导体管芯封装600的相应侧视图和平面图。半导体管芯封装600是当在模制和成形夹具500中被夹持时经历封装过程的线接合的引线框架组件300。此外,通过从引线指108除去外挡杆114和伪引线118、从管芯标记106切断连接杆120以及从引线指108切断内挡杆116,切割(切单)和修整半导体管芯封装600。
半导体管芯封装600包括形成外壳602的模塑化合物,该外壳602覆盖半导体管芯202、接合线302、引线指108的每个接合端110和管芯标记106。另外,引线指108中的每一个的伸长区域112从外壳602伸出以提供用于封装600的外部连接器引线604。流入外部模制腔516的模塑化合物从外壳602延伸以提供模制到外部连接器引线604的绝缘支撑指606。
共同作用的引线指形成(再成形)表面512、514已经弯曲外部连接器引线604的自由端以形成安装脚608。此外,在本实施例中,如图所示,绝缘支撑指606与外部连接器引线604的相应相邻区域在同一个平面。
在本实施例中,绝缘支撑指606沿着外部连接器引线604的总长度延伸。然而,在一些实施例中,绝缘支撑指606不需要延伸外部连接器引线604的总长度并且例如可以在安装脚608之前终止。
图8是根据本发明第二实施例当夹持线接合的引线框架组件300时模制和成形夹具800的横截面侧视图。夹具800类似于夹具500并且为了避免重复将仅描述区别。在本实施例中,将外部模制腔516改变为包括桥接腔802。在操作中,在弯曲引线指108的伸长区域112之后,模塑化合物沉积到外壳模制腔506中以覆盖半导体管芯202、接合线302、引线指108的每个接合端110和管芯标记106。在模制期间,模塑化合物中的一些穿过外壳模制出口306流入外壳模制腔506中并且到外部模制腔516和桥接腔802中。
图9和10图示了根据本发明第二实施例半导体管芯封装900的相应侧视图和平面图。半导体管芯封装900是当在模制和成形夹具800中被夹持时经历封装过程的线接合的引线框架组件300。此外,通过从引线指108除去外挡杆114和伪引线118、从管芯标记106切断连接杆120以及还从引线指108切断内挡杆116,切割(切单)和修整半导体管芯封装900。
半导体管芯封装900包括形成外壳902的模塑化合物,该外壳902覆盖半导体管芯202、接合线302、引线指108的每个接合端110和管芯标记106。另外,引线指108中的每一个的伸长区域112从外壳902伸出以提供用于封装900的外部连接器引线904。流入外部模制腔516的模塑化合物从外壳602延伸以提供模制到外部连接器引线904的绝缘支撑指906。此外,流入桥接腔802的模塑化合物形成相应的绝缘横向构件908,该绝缘横向构件908与一组外部连接器引线604相关联并且被模制至该组外部连接器引线604。此外,每个相应的横向构件908垂直于该组外部连接器引线604的纵轴并且每个横向构件908与一组绝缘支撑指906集成为一体。
在本实施例中,绝缘支撑指906沿着外部连接器引线904的总长度延伸。然而,在一些实施例中,绝缘支撑指906不需要延伸外部连接器引线904的总长度并且例如可以在到达外部连接器引线904的安装脚918之前终止。
参照图11,示出了根据本发明的第三实施例当夹持线接合的引线框架组件300时模制和成形夹具1100的横截面侧视图。夹具1100类似于夹具500并且为了避免重复将仅描述区别。在本实施例中,改变夹具1100以增大外部模制腔516的尺寸,该外部模制腔516包括桥接腔1102。
在操作中,在弯曲引线指108的伸长区域112之后,模塑化合物沉积到外壳模制腔506中以覆盖半导体管芯202、接合线302、引线指108的每个接合端110和管芯标记106。在模制期间,一部分模塑化合物穿过外壳模制出口306流入外壳模制腔506中并且到外部模制腔516和桥接腔1102中。
参照图12和13,示出了根据本发明第三实施例半导体管芯封装1200的相应侧视图和平面图。半导体管芯封装1200是当在模制和成形夹具1100中被夹持时经历封装过程的线接合的引线框架组件300。此外,通过从引线指108除去外挡杆114和伪引线118、从管芯标记106切断连接杆120以及从引线指108切断内挡杆116,切割(切单)和修整半导体管芯封装1200。
半导体管芯封装1200包括形成外壳1202的模塑化合物,该外壳1202覆盖半导体管芯202、接合线302、引线指108的每个接合端110和管芯标记106。另外,引线指108中的每一个的伸长区域112从外壳1202伸出以提供用于封装1200的外部连接器引线1204。流入外部模制腔516的模塑化合物从外壳602延伸以提供模制到外部连接器引线904的绝缘支撑指1206。绝缘支撑指1206比外部连接器引线1204粗并且覆盖外部连接器引线1204的顶部和对立的下部表面的区域。
此外,流入桥接腔1102的模塑化合物形成相应的绝缘横向构件1208,该绝缘横向构件1208与一组外部连接器引线604相关联并且被模制到该组外部连接器引线604。此外,每个相应的横向构件1208垂直于该组外部连接器引线604的纵轴并且每个横向构件1208与一组绝缘支撑指1206集成为一体。
在本实施例中,绝缘支撑指1206沿着外部连接器引线1204的总长度延伸。然而,在一些实施例中,绝缘支撑指1206不需要延伸外部连接器引线1204的总长度并且例如可以在到达外部连接器引线1204的安装脚1218之前终止。
参照图14,示出了根据本发明第四实施例的引线框架片1400的部分平面视图。除去除了伪引线118以外,引线框架片1400基本上与引线框架片100相同。引线框架片1400可以由半导体管芯202填充并且形成为如上面实施例中的任何一个描述的半导体封装。
图15是根据本发明第五实施例的一组安装脚608的端视图。安装脚608各自具有底座1502和对应的对立上表面1504,并且如图所示每个底座1502具有比对应的对立上表面1504的宽度W2窄的宽度W1。
参照图16,示出了根据本发明实施例组装半导体管芯封装的方法1600的流程图。方法1600包括,在块1610处,提供引线框架,例如引线框架片100或者1400的引线框架102中的一个。在块1620处,方法1600执行将半导体管芯(例如管芯202)安装在管芯标记106上并且在块1630处,执行将半导体管芯202的电极204选择性地线接合至引线指108中的每一个的接合端110的过程。结果,形成了线接合的引线框架组件300并且将该组件放置在模制和成形夹具(例如夹具500、800或者1100中的一个)中。在块1640处,将夹具砧座和互补上部构件集合在一起以由此形成外壳模制腔并且因此将每个伸长区域112成形(弯曲)在外部连接器引线中,安装脚在引线的自由端处。
块1650处的方法1600包括执行模制工序以通过模塑化合物沉积形成外壳。模制工序将模塑化合物注入或者压到外壳模制腔506中以便模塑化合物覆盖半导体管芯202、接合线302、每个接合端110和管芯标记106。在模制工序期间,内挡杆116为外壳(例如,外壳602、902、1202)形成模制腔的部分外部周边。另外,引线指108中的每一个的伸长区域从外壳伸出以提供用于封装的外部连接器引线,并且在模制工序期间,部分模塑化合物从相邻外部连接器引线之间的模制腔506流出以提供模制到外部连接器引线的绝缘支撑指。此外,在模制工序期间,相邻外部连接器引线之间的模塑化合物的流动由外挡杆114保持。最后,在块1660执行切割(切单)过程以切断外挡杆和内挡杆114、116和连接杆120之后完成方法1600,该方法产生完整的封装,例如半导体管芯封装600、900或者1200。
有利地,本发明提供了通过利用绝缘支撑指加强半导体管芯封装的外部引线,所述绝缘支撑指可以由绝缘横向构件进一步加强。因此,本发明至少减轻了由外部引线间距的减小和减小的引线宽度引起的内引线短路。绝缘支撑指和绝缘横向构件还可以减轻外部引线的变形或者不期望的弯曲。另外,由于安装脚的底座具有比对应的对立上表面的宽度窄的宽度,因此该特性还可以减少当半导体封装安装到电路板上时焊接短路的可能性。
为了说明和描述的目的给出了本发明优选实施例的描述,但是并不旨在将穷举本发明或将本发明限制于所公开的形式。本领域的技术人员应当理解,在不偏离本发明主要的发明构思的情况下,可以对上述实施例进行改变。因此,应当理解,本发明不限于所公开的具体实施例,而是覆盖了如所附权利要求中限定的本发明的精神和范围内的修改。

Claims (20)

1.一种半导体管芯封装,包括:
管芯标记;
围绕所述管芯标记的引线指,每个引线指具有邻近所述管芯标记的接合端和延伸远离所述管芯标记的伸长区域;
安装在所述管芯标记上的半导体管芯;
将所述半导体管芯的电极电连接至所述引线指中的每一个的所述接合端的接合线;以及
形成外壳的模塑化合物,所述模塑化合物覆盖所述半导体管芯、所述接合线、每个接合端和所述管芯标记,
其中所述引线指中的每一个的所述伸长区域从所述外壳伸出以提供用于所述封装的外部连接器引线,并且所述模塑化合物从所述外壳延伸以提供模制到所述外部连接器引线的绝缘支撑指。
2.根据权利要求1所述的半导体管芯封装,其中所述绝缘支撑指延伸所述外部连接器引线的总长度。
3.根据权利要求1所述的半导体管芯封装,其中所述外部连接器引线的自由端被弯曲以形成安装脚。
4.根据权利要求1所述的半导体管芯封装,其中所述绝缘支撑指与所述外部连接器引线的相应的相邻区域共面。
5.根据权利要求1所述的半导体管芯封装,其中所述模塑化合物进一步形成垂直于一组外部连接器引线的纵轴的绝缘横向构件。
6.根据权利要求5所述的半导体管芯封装,其中所述绝缘横向构件被模制至所述外部连接器引线组。
7.根据权利要求6所述的半导体管芯封装,其中所述绝缘横向构件与一组绝缘支撑指集成为一体。
8.根据权利要求1所述的半导体管芯封装,其中所述安装脚各自具有底座和对应的对立上表面,并且其中每个底座具有比对应的对立上表面的宽度窄的宽度。
9.一种组装半导体管芯封装的方法,所述方法包括:
提供引线框架,所述引线框架具有(i)围绕管芯标记的围绕框架、(ii)从所述围绕框架向内延伸并且支撑所述管芯标记的连接杆、(iii)围绕所述管芯标记的引线指,每个引线指具有邻近所述管芯标记的接合端和朝所述外框架延伸远离所述管芯标记的伸长区域、(iv)桥接所述伸长区域的相邻自由端的外挡杆,和(v)从所述***绕框架支撑所述引线指的内挡杆,其中所述内挡杆为除了相邻伸长区域之间的区域之外的周边定义了外部周边封装外壳轮廓;
将半导体管芯安装在所述管芯标记上;
用接合线将所述半导体管芯的电极电连接至所述引线指中的每一个的所述接合端;
将每个伸长区域形成为外部连接器引线,安装脚位于其自由端处;以及
执行模制工序以用模塑化合物形成外壳,所述外壳覆盖所述半导体管芯、所述接合线以及每个接合端和所述管芯标记,其中在所述模制工序期间,所述内挡杆为所述外壳形成模制腔的部分外部周边,以及
其中所述引线指中的每一个的所述伸长区域从所述外壳伸出以提供用于所述封装的所述外部连接器引线,并且在模制工序期间,所述模塑化合物中的一部分从相邻外部连接器引线之间的所述模制腔流出以提供模制至所述外部连接器引线的绝缘支撑指。
10.根据权利要求9所述的组装半导体管芯封装的方法,其中相邻外部连接器引线之间的所述模塑化合物的所述流动由所述外挡杆保持。
11.根据权利要求9所述的组装半导体管芯封装的方法,其中所述绝缘支撑指延伸所述外部连接器引线的总长度。
12.根据权利要求9所述的组装半导体管芯封装的方法,其中所述外部连接器引线被弯曲以形成安装脚。
13.根据权利要求9所述的组装半导体管芯封装的方法,其中所述绝缘支撑指与所述外部连接器引线的相应的相邻区域共面。
14.根据权利要求9所述的组装半导体管芯封装的方法,其中所述模塑化合物进一步形成垂直于一组所述外部连接器引线的纵轴的绝缘横向构件。
15.根据权利要求14所述的组装半导体管芯封装的方法,其中所述绝缘横向构件被模制至所述外部连接器引线组。
16.根据权利要求15所述的组装半导体管芯封装的方法,其中所述绝缘横向构件与一组绝缘支撑指集成为一体。
17.根据权利要求9所述的组装半导体管芯封装的方法,其中所述安装脚各自具有底座和对应的对立上表面,并且其中每个底座具有比对应的对立上表面的宽度窄的宽度。
18.根据权利要求9所述的组装半导体管芯封装的方法,其中用模制和成形夹具执行所述每个伸长区域形成为外部连接器引线和所述模制工序的所述执行。
19.一种在其中形成有引线框架阵列的引线框架片,所述引线框架中的每一个包括:
围绕管芯标记的围绕框架;
从所述围绕框架向内延伸并且支撑所述管芯标记的连接杆;
围绕所述管芯标记的引线指,所述引线指中的每一个具有邻近所述管芯标记的接合端和朝所述外框架延伸远离所述管芯标记的伸长区域;
桥接所述伸长区域的相邻自由端的外挡杆;以及
从所述***绕框架支撑所述引线指的内挡杆,
其中所述内挡杆为除了相邻伸长区域之间的区域之外的周边定义了外部周边封装外壳轮廓。
20.根据权利要求19所述的引线框架片,其中邻近所述外档杆的每个所述伸长区域的自由端具有底座和对应的对立上表面,并且其中所述底座具有比所述对应的对立上表面窄的宽度。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107978576A (zh) * 2016-10-21 2018-05-01 恩智浦美国有限公司 封装半导体器件的衬底互连结构
CN114252820A (zh) * 2020-09-24 2022-03-29 迈来芯电子科技有限公司 磁传感器部件和组件

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108735701B (zh) * 2017-04-13 2021-12-24 恩智浦美国有限公司 具有用于包封期间的毛刺缓解的虚设引线的引线框架

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4897602A (en) * 1988-01-04 1990-01-30 Motorola, Inc. Electronic device package with peripheral carrier structure of low-cost plastic
US5412157A (en) * 1992-07-17 1995-05-02 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US5473199A (en) * 1992-03-02 1995-12-05 Fujitsu Limited Semiconductor device having a body with a carrier ring connected thereto
US6025640A (en) * 1997-07-16 2000-02-15 Dai Nippon Insatsu Kabushiki Kaisha Resin-sealed semiconductor device, circuit member for use therein and method of manufacturing resin-sealed semiconductor device
US20030073265A1 (en) * 2001-10-12 2003-04-17 Tom Hu Semiconductor package with singulation crease

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4801561A (en) * 1984-07-05 1989-01-31 National Semiconductor Corporation Method for making a pre-testable semiconductor die package
US6608366B1 (en) * 2002-04-15 2003-08-19 Harry J. Fogelson Lead frame with plated end leads

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4897602A (en) * 1988-01-04 1990-01-30 Motorola, Inc. Electronic device package with peripheral carrier structure of low-cost plastic
US5473199A (en) * 1992-03-02 1995-12-05 Fujitsu Limited Semiconductor device having a body with a carrier ring connected thereto
US5412157A (en) * 1992-07-17 1995-05-02 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6025640A (en) * 1997-07-16 2000-02-15 Dai Nippon Insatsu Kabushiki Kaisha Resin-sealed semiconductor device, circuit member for use therein and method of manufacturing resin-sealed semiconductor device
US20030073265A1 (en) * 2001-10-12 2003-04-17 Tom Hu Semiconductor package with singulation crease

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107978576A (zh) * 2016-10-21 2018-05-01 恩智浦美国有限公司 封装半导体器件的衬底互连结构
CN107978576B (zh) * 2016-10-21 2023-07-28 恩智浦美国有限公司 封装半导体器件的衬底互连结构
CN114252820A (zh) * 2020-09-24 2022-03-29 迈来芯电子科技有限公司 磁传感器部件和组件

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