CN105894079B - Clock scrambling circuit - Google Patents
Clock scrambling circuit Download PDFInfo
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- CN105894079B CN105894079B CN201610255899.0A CN201610255899A CN105894079B CN 105894079 B CN105894079 B CN 105894079B CN 201610255899 A CN201610255899 A CN 201610255899A CN 105894079 B CN105894079 B CN 105894079B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
- G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
- G06K19/07363—Means for preventing undesired reading or writing from or onto record carriers by preventing analysis of the circuit, e.g. dynamic or static power analysis or current analysis
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Abstract
A kind of clock scrambling circuit, comprising: controller and clock signal scrambling circuit, in which: the controller is coupled with the clock signal scrambling circuit, suitable for generating control signal and being input to the clock signal scrambling circuit；The clock signal scrambling circuit is suitable for receiving the control signal, carries out random scrambling processing to the clock signal of input.Using the clock scrambling circuit, the attack tolerant energy of safety chip can be improved.
Description
Technical field
The present invention relates to information security field more particularly to a kind of clock scrambling circuits.
Background technique
In recent years, smart card techniques develop rapidly, and have been widely used in a variety of fields such as Bank Danamon card, social security card
It closes.With the development of smart card techniques, the security performance of smart card is increasingly taken seriously.It is right in smart card detection standard
Security test proposes very high requirement, not only needs faster response speed, it is also necessary to various attacks are resisted, it is especially other
(also referred to as side-channel attack) and fault injection attacks are attacked in road.
In the calculating process for carrying out cryptographic algorithm, the current curve of safety chip consumption can wrap the safety chip of smart card
Containing key information in certain piece.Advanced attack technology can analyze key by a plurality of current curve and crack safety
Chip.
There are certain hidden danger for the safety of existing safety chip.
Summary of the invention
Present invention solves the technical problem that being how to improve the attack tolerant energy of safety chip in smart card.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of clock scrambling circuit, comprising: controller is with timely
Clock signal scrambling circuit, in which: the controller is coupled with the clock signal scrambling circuit, is suitable for generating control signal simultaneously
It is input to the clock signal scrambling circuit；The clock signal scrambling circuit is suitable for receiving the control signal, to input
Clock signal carries out random scrambling processing.
Optionally, the clock signal scrambling circuit be suitable for in the phase or frequency of the clock signal of the input extremely
A kind of few random scrambling processing of progress.
Optionally, the clock signal scrambling circuit comprises at least one of the following: delay unit, divides phase offset unit
Frequency unit, in which: the delay unit is coupled with the controller, the first control letter generated suitable for receiving the controller
Number, random delay operation is carried out to the clock signal of the input；The phase offset unit is coupled with the controller, is fitted
In the second control signal for receiving the controller generation, multi-channel time-delay is carried out to the clock signal of the input and is therefrom selected
Time delayed signal is as output all the way；The frequency unit is coupled with the controller, suitable for receive that the controller generates the
Three control signals carry out random scaling down processing to the clock signal of the input.
Optionally, the phase offset unit includes: N grades of delay buffers and phase offset selecting unit, in which: institute
N grades of delay buffers are stated, are coupled with the phase offset selecting unit, including N number of delay buffer, suitable for by the input
Clock signal carries out delay process, generates the different signal of the road N delay duration and is input to the phase offset selection list
Member, N > 1；The phase offset selecting unit is coupled with the controller, the second control generated suitable for receiving the controller
Signal processed is randomly choosed in the signal different from the road N delay duration and is exported all the way.
Optionally, the clock signal scrambling circuit includes in delay unit, phase offset unit and frequency unit
Any two unit, any two unit series connection, and one of unit inputs the clock signal, another unit is defeated
Out by the clock signal of random scrambling processing.
Optionally, the clock signal scrambling circuit includes: the delay unit of series connection, the phase offset list
The first and described frequency unit.
Optionally, the controller includes: mask register, and the mask controller is suitable for generating n bit
Mask, and position and operation are carried out with the random number of identical digit, obtained position and result are n bit；Institute's rheme and knot
Fruit is the control signal, is comprised at least one of the following: the first control signal, the second control signal and described the
Three control signals.
Optionally, the control signal includes the first control signal, the second control signal and the third
Control signal, in which: the first control signal is 0~n1Bit, in which: 0~m1Bit is control
The delay duration information of the delay unit, m1+ 1~n1Bit is the update cycle information of the delay duration；Institute
Stating second control signal is n-th1+ 1~n2Bit, in which: n-th1+ 1~m2Bit is that the control phase is inclined
Move the signal identification information of selecting unit selection, m2+ 1~n2Bit is the update week of the selected signal identification
Phase information；The third control signal is n-th2+ 1~n bit, in which: n-th2+ 1~m3Bit is control institute
State the frequency division value of frequency unit, m3+ 1~n bit is the update cycle information of the frequency division value；Wherein, 0 < m1<n1<
m2< n2<m3< n.
Optionally, the controller further include: limitation value register is suitable for 0~m1Bit, m1+ 1~
n1Bit, n-th1+ 1~m2Bit, m2+ 1~n2Bit, n-th2+ 1~m3Bit and
M3The numerical value of+1~n bit is limited.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that
Clock signal scrambling circuit receives controller and generates control signal, at the progress of input clock signal at random scrambling
Reason.Random scrambling treated clock signal is in random variation, so that the current curve inside safety chip is no longer rule
Then change but change at random, so as to promote attack difficulty, improves the attack tolerant energy of safety chip.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of one of embodiment of the present invention clock scrambling circuit；
Fig. 2 is the structural schematic diagram of another clock scrambling circuit in the embodiment of the present invention.
Specific embodiment
Safety chip in smart card is in the calculating process for carrying out cryptographic algorithm, the current curve meeting of safety chip consumption
Include key information in certain piece.Advanced attack technology can analyze key by a plurality of current curve, to crack
Safety chip.
In embodiments of the present invention, clock signal scrambling circuit receives controller and generates control signal, believes input clock
Number progress at random scrambling handle.Random scrambling treated clock signal is in random variation, so that inside safety chip
Current curve be no longer rule variation but random variation, so as to promote attack difficulty, improve the anti-of safety chip and attack
Hit performance.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, with reference to the accompanying drawing to this
The specific embodiment of invention is described in detail.
Referring to Fig.1, the embodiment of the invention provides a kind of clock scrambling circuits, comprising: controller 11 adds with clock signal
Disturb circuit 12, in which:
Controller 11 is coupled with the clock signal scrambling circuit 12, suitable for generating control signal and being input to clock letter
Number scrambling circuit 12, to realize the control to clock signal scrambling circuit 12；
Clock signal scrambling circuit 12 is coupled with the controller 11, the control sent suitable for receiving the controller 11
Signal, and random scrambling processing is carried out according to clock signal clk IN of the control signal to input, it obtains by scrambling at random
The output clock signal clk OUT of processing；Wherein, it carries out random scrambling processing to the clock signal clk IN of input to refer to: to defeated
At least one of phase or frequency of the clock signal clk IN entered carry out random scrambling processing, namely: it can be only to input
The phase of clock signal clk IN carry out random scrambling processing, can also only the frequency to the clock signal clk IN of input carry out
Random scrambling processing the phase to the clock signal clk IN of input and frequency can also carry out random scrambling processing simultaneously.
In specific implementation, the controller 11 can be processor of single chip computer, or digital signal processor
Controllers such as (Digital Signal Processor, DSP).
After the phase to the clock signal of input carries out random scrambling processing, the phase of obtained clock signal is random
Variation；Correspondingly, after the frequency to the clock signal of input carries out random scrambling processing, the frequency of obtained clock signal
And change at random.In this way, the current curve inside safety chip is no longer just regular variation, but random variation, therefore
Attack difficulty can be promoted, the attack tolerant energy of safety chip is improved.
In embodiments of the present invention, clock signal scrambling circuit may include delay unit, phase offset unit and divide
At least one of frequency unit.It in practical applications, can be according to actual application scenarios, such as board area, production cost
And security consideration, one or more composition clock letters are selected from delay unit, phase offset unit and frequency unit
Number scrambling circuit.
For example, it is contemplated that it is limited to board area, phase offset unit can be only included in clock signal scrambling circuit.Again
Such as, it is contemplated that the demand of high security, can include simultaneously in clock signal scrambling circuit delay unit, phase offset unit with
And frequency unit, at this point, delay unit, phase offset unit and frequency unit three series connection.
In embodiments of the present invention, delay unit can be only included in clock signal scrambling circuit.At this point, controller with prolong
Shi Danyuan coupling, clock signal input to delay unit.Controller generates first control signal, and is input to delay unit, with
Random scrambling control is carried out to delay unit.It include the delay duration information for controlling delay unit in first control signal
And the update cycle information of delay duration, delay duration information and corresponding update cycle information are set at random.
Delay unit is after receiving first control signal, according to the delay duration information in first control signal, selection
Corresponding delay duration, and delay operation is carried out to the clock signal of input.Delay unit is after receiving first control signal
Start timing, is fed back when timing duration reaches the update cycle of delay duration to controller, so that controller reconfigures
The update cycle information of delay duration information and delay duration.
In practical applications, delay unit may include multiple delay gears, when the delay for including in first control signal
Long message is delay gear information.Each corresponding delay duration of delay gear is different, and be delayed the corresponding delay of gear 1
Duration can be 20ns, and the delay corresponding delay duration of gear 2 can be 40ns, and the delay corresponding delay duration of gear 3 can be with
For 60ns etc..
The corresponding delay gear 1 of the delay gear information that includes in first control signal, be delayed 1 corresponding delay of gear when
A length of 20ns, the update cycle information of delay duration are 5s.Then delay unit is after receiving first control signal, by input
Clock signal carries out the delay of 20ns, and after 5s, has reached to the update cycle of controller delay of feedback duration, at this point,
Controller can distribute the update cycle information of delay duration information and delay duration again for delay unit.
It should be noted that controller is randomly the update of delay unit distribution delay duration information and delay duration
Cycle information.That is, previous first control signal generated of controller and the latter first control signal generated can
It is completely uncorrelated therebetween to be different.
In embodiments of the present invention, phase offset unit can be only included in clock signal scrambling circuit.At this point, controller
It is coupled with phase offset unit, clock signal input to phase offset unit.Controller generates second control signal, and is input to
Phase offset unit, to carry out random scrambling control to phase offset unit.
Phase offset unit includes N grades of delay buffers and phase offset selecting unit coupled thereto.It is delayed at N grades
In buffer, the delay duration including N number of delay buffer being cascaded, each delay buffer can be all the same,
It can also be different.N grades of delay buffers carry out at delay the clock signal of input in the clock signal for receiving input
Reason generates the different signal of the road N delay duration and is input to phase offset selecting unit, wherein N > 1.
The value of N can also be set according to practical application scene, for example, setting N=7, i.e. phase offset unit include 7
The delay buffer being cascaded.
In second control signal, include control phase offset selecting unit selection output signal identification information and
The update cycle information of signal identification, signal identification information and its corresponding update cycle information are set at random.
Phase offset selecting unit is believed after receiving second control signal according to the signal identification in second control signal
Breath selects corresponding signal all the way as output from the road the N signal that the N grade delay buffer received exports.Phase offset
Selecting unit starts timing after receiving second control signal, when timing duration reaches the update cycle of signal identification to control
Device feedback processed, so that controller reconfigures the update cycle information of signal identification information and signal identification.
For example, in second control signal, the signal identification information for including is 2, namely selects from N grades of delay buffers the
2 road signals are as output.
It should be noted that controller is randomly phase offset unit distribution signal identification information and signal identification
Update cycle information.That is, previous second control signal generated of controller and the second control generated for latter time are believed
It number is different, it is completely uncorrelated therebetween.
In embodiments of the present invention, frequency unit can be only included in clock signal scrambling circuit.At this point, controller with point
The coupling of frequency unit, clock signal input to frequency unit.Controller generates third and controls signal, and is input to frequency unit, with
Random scrambling control is carried out to frequency unit.It include to control the frequency division value of frequency unit and divide in third control signal
The update cycle information of frequency value, frequency division value and corresponding update cycle information are set at random.
Frequency unit receive third control signal after, according to third control signal in frequency division value, to input when
Clock signal carries out divide operation corresponding with frequency division value.Frequency unit starts timing after receiving third control signal, works as meter
It is constantly long to be fed back to controller when reaching frequency division value corresponding update cycle so that controller reconfigure frequency division value and point
The update cycle information of frequency value.
For example, the frequency division value for including is 2 in third control signal.Frequency unit receive third control signal after,
Divide-by-two operations are carried out to the clock signal of input.
Similar, controller is the update cycle information of frequency unit distribution frequency division value and frequency division value at random.Also
To say, the previous time third control signal generated of controller and the third generated for latter time control signal and are different, the two it
Between completely it is uncorrelated.
In embodiments of the present invention, also may include in clock signal scrambling circuit delay unit, phase offset unit with
And any two unit in frequency unit, two unit series connection, and one of unit input clock signal, another unit
Clock signal of the output by random scrambling processing.
For example, including delay unit and phase offset unit in clock signal scrambling circuit, clock signal input is to prolonging
Shi Danyuan.Delay unit carries out and first the clock signal of input after the first control signal for receiving controller transmission
Control the corresponding delay operation of signal.Clock signal input after delay process is to phase offset unit, phase offset
Unit is handled by the clock signal after delay process again, clock signal of the output by random scrambling processing.
Phase offset unit includes 7 grades of delay buffers and phase offset selecting unit, and 7 grades of delay buffers use 7
A concatenated delay buffer.7 grades of delay buffers are delayed to by the clock signal after delay process, generate 7 tunnels
The different clock signal of delay duration, and it is input to phase offset selecting unit.
Phase offset selecting unit is after the second control signal for receiving controller transmission, according to second control signal,
It is selected in the clock signal different from 7 tunnel delay durations all the way as output.
It is understood that when only including delay unit and phase offset unit in clock signal scrambling circuit, when
Clock signal can also first be input to phase offset unit.Phase offset unit is delayed after receiving second control signal from 7 grades
It selects in 7 road signals of buffer output all the way as output, and is input to delay unit.Delay unit is receiving the first control
After signal processed, the output signal of phase offset unit is subjected to corresponding delay operation.
It is similar, can also only include delay unit and frequency unit in clock signal scrambling circuit, delay unit with
Frequency unit series connection.The clock signal input Jing Guo delay process can extremely be divided first by clock signal input to delay unit
Frequency unit, to carry out scaling down processing；Scaling down processing can also be carried out, then will pass through first by clock signal input to frequency unit
The clock signal input of frequency dividing to delay unit carries out delay operation.
Can also only include phase offset unit and frequency unit in clock signal scrambling circuit, phase offset unit with
Frequency unit series connection.Correspondingly, clock signal can also first be input to phase offset unit, and the output of phase offset unit is made
For the input of frequency unit；It can also be inclined as phase using the output of frequency unit first by clock signal input to frequency unit
Move the input of unit.
It can also simultaneously include delay unit, phase offset unit and frequency unit in clock signal scrambling circuit.
Referring to Fig. 2, the structure chart of another clock scrambling circuit in the embodiment of the present invention is given.
Controller 11 is coupled with delay unit 121, phase offset unit 122 and frequency unit 123 respectively.Controller 11
The control signal of generation includes: first control signal, second control signal and third control signal, in which: the first control letter
Number for controlling delay unit 121, second control signal is for controlling phase offset unit 122, third control
Signal processed is for controlling frequency unit 123.
Clock signal clk IN is input to delay unit 121.When delay unit 121 receives first control signal, according to
Delay gear information in first control signal, selection delay duration corresponding with delay gear information, and to the clock of input
Signal CLKIN carries out corresponding delay process.Clock signal input by delay process is to phase offset unit 122.
Phase offset unit 122 includes 7 grades of delay buffers 1221 and phase offset selecting unit 1222.7 grades of delays
Buffer includes 7 delay buffers, is followed successively by D1~D7, the clock signal Jing Guo delay process is handled, 7 tunnels are generated
The different signal of delay duration is simultaneously input to phase offset selecting unit 1222.Phase offset selecting unit 1222 is according to connecing
The second control signal received selects signal all the way from 7 road signals and is input to frequency unit 123.
Frequency unit 123 controls signal according to the third received, defeated to the phase offset selecting unit 1222 received
Signal out carries out the divide operation of corresponding frequency division value, and finally obtained fractional frequency signal is the clock by random scrambling processing
Signal CLKOUT.
It is understood that between delay unit, phase offset unit and frequency unit three, there may also be a variety of
The connection relationship of other forms is not limited in the connection schematic diagram provided in Fig. 2 of the embodiment of the present invention.
For example, clock signal is first input to frequency unit first carries out divide operation, the clock signal input after frequency dividing is extremely
Delay unit, the clock signal by delay are input to phase offset unit again and are selected, signal, that is, conduct of final choice
The clock signal of output, namely by random scrambled clock signal.
In specific implementation, controller can generate control signal by the way of software, can also use the side of hardware
Formula generates control signal.To realize more quick control effect, in an embodiment of the present invention, controller uses the side of hardware
Formula generates control signal.
The process for being generated control signal by the way of hardware to controller below is illustrated.
It is provided with mask register in the controller.The mask of n bit, and and n can be generated in mask register
The binary random number in position carries out position and operation, and the position of obtained n bit and result can be used as controller generation
Controlling the control signal that signal namely controller generate is n bit.
When it includes a variety of for controlling signal, the position of n bit and result can be divided into mutually independent data
Block, different data block correspond to different control signals.For example, n=32, control signal includes first control signal, the second control
Signal processed and third control signal, then 32 bits are divided into 3 data blocks, and the first data block is 32 binary systems
Several the 0th~7, corresponds to first control signal；Second data block is the 8th~15 of 32 bits, corresponds to the
Two control signals；Third data block is the 16th~31 of 32 bits, corresponds to third control signal.
The random number of n bit can be generated using the randomizer of peripheral hardware, can also be using in controller
The randomizer in portion generates.
The size of n can be related to unit number included in clock signal scrambling circuit.In clock signal scrambling circuit
The control signal that unit number is more namely controller to be generated number it is more, n can be bigger；Correspondingly, clock signal
Unit number in scrambling circuit is smaller namely the controller number for controlling signal to be generated is smaller, and n can be smaller.
For example, controller only needs to generate the second control when only including phase offset unit in clock signal scrambling circuit
Signal, at this time n=8.It for another example, simultaneously include delay unit and phase offset unit in clock signal scrambling circuit, at this point, control
Device processed needs to generate first control signal and second control signal, and n=16 can be set.For another example, clock signal scrambling circuit
In simultaneously include delay unit, phase offset unit and when frequency unit, controller needs to generate first control signal, second
It controls signal and third controls signal, then n=32 can be set.
It is understood that the size of n can also be unrelated with unit number included in clock signal scrambling circuit, n is
Fixed value, namely no matter include how many a units in clock signal scrambling circuit, the value of n is constant.For example, setting n=32, when
When only including phase offset unit in clock signal scrambling circuit, n=32；When in clock signal scrambling circuit while including delay
When unit, phase offset unit and frequency unit, n remains as 32.
When n is fixed value, if the unit for including in clock signal scrambling circuit is less, therein one can be only chosen
Part is as control signal, remaining digit zero setting.
For example, can only choose the therein 0th~7 when only including phase offset unit in clock signal scrambling circuit
Position is used as second control signal, remaining digit whole zero setting.
In embodiments of the present invention, in the position and result of n bit, each corresponding data block of control signal is also
Two parts can be divided into.For example, the corresponding data block of first control signal is divided into two parts, the number of first part
According to delay duration information is expressed as, the data of second part are expressed as the update cycle information of delay duration.
It, can be with when simultaneously including delay unit, phase offset unit and when frequency unit in clock signal scrambling circuit
Three data blocks are divided into two parts, in which:
First control signal is 0~n1Bit, in which: 0~m1Bit is control delay unit
Delay duration information, m1+ 1~n1Position binary code is the update cycle information of delay duration；
Second control signal is n-th1+ 1~n2Bit, in which: n-th1+ 1~m2Bit is control phase
Deviate the signal identification information of selecting unit selection, m2+ 1~n2Bit is the update cycle of the signal identification of selection
Information；
It is n that third, which controls signal,2+ 1~n bit, in which: n-th2+ 1~m3Bit is described point of control
The frequency division value of frequency unit, m3+ 1~n bit is the update cycle information of the frequency division value；n1、n2, n meet n1< n2
< n.
In an embodiment of the present invention, n=32, in which:
0th~7 bit corresponds to first control signal, in which: the 0th~3 bit is first control signal
In delay duration information, the 4th~7 bit is expressed as the corresponding update cycle information of delay duration information；
8th~15 bit corresponds to second control signal, in which: the 8th~11 bit is the second control letter
Signal identification information in number, the 12nd~15 bit are the corresponding update cycle information of signal identification；
16th~31 bit corresponds to third control signal, in which: the 15th~23 bit is third control
Frequency division value in signal, the 24th~31 bit are the corresponding update cycle information of frequency division value.
In embodiments of the present invention, since the mask of n bit and n binary system random numbers carry out position and operation,
Therefore in the position and result obtained, the numerical value in each data block is random.Namely first control signal, the second control
Signal and the corresponding binary number of third control signal may be random.
It, can be for each control signal to avoid some value in above-mentioned three kinds of control signal bigger than normal or less than normal
Corresponding limits value is arranged in corresponding binary number, to limit the value range of each corresponding binary number of control signal.
For example, in 0~n1Bit, for 0~m1Bit, its value range of limit value are decimal number 1
~6,0~m in position and result1When the corresponding decimal number of bit is 0, then automatically by the in position and result
0~m1Bit is set to 001；0~m in position and result1When the corresponding decimal number of bit is 7, then certainly
Dynamic 0~m by position and result1Bit is set to 110.
Correspondingly, m1+ 1~n1Bit, n-th1+ 1~m2Bit, m2+ 1~n2Bit,
N-th2+ 1~m3Bit and m3+ 1~n bit may exist one-to-one limits value therewith, these
Limits value can be preset according to the actual needs.
In embodiments of the present invention, it can be provided with limitation value register in the controller, by preset limits value
It is stored in advance in limitation value register.
In conjunction with Fig. 2, in the position and result of n bit, n can be divided into 3 data blocks, each data block
Respectively correspond a control signal.The adjustable mask register of controller n binary code generated, to determine whether to control
It makes some unit and executes random Scrambling Operation.
For example, in n binary masks, n-th1+ 1~n2Bit is all set to 0, then with n random numbers into
After line position and operation, n-th in the position and operation of obtained n bit1+ 1~n2Bit is all 0.At this point, control
Device processed does not control phase offset unit and carries out STOCHASTIC CONTROL operation to clock signal, and phase offset unit can choose fixed
Signal identification is as output.
Analogously, in n binary masks, as 0~n1When bit is all set to 0, delay unit
The fixed delay gear of selection is delayed to input clock signal；When n-th2When+1~n bit is all set to 0,
The frequency division value of frequency unit is also a fixed value.
That is, when simultaneously including that delay unit, phase offset unit and frequency dividing are single in clock signal scrambling circuit
It, can be random to select one or more to carry out the clock signal of input by the setting to control signal when first
Scrambling processing.
It is understood that in other embodiments of the present invention, the value of above-mentioned n, the position of n bit and result
Division etc. is not repeated herein there may also be other forms.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (7)
1. a kind of clock scrambling circuit characterized by comprising controller and clock signal scrambling circuit, in which:
The controller is coupled with the clock signal scrambling circuit, suitable for generating control signal and being input to the clock letter
Number scrambling circuit；
The clock signal scrambling circuit is suitable for receiving the control signal, in the phase or frequency of the clock signal of input
At least one carry out random scrambling processing；
The clock signal scrambling circuit comprises at least one of the following: delay unit, phase offset unit, frequency unit, in which:
The delay unit is coupled with the controller, the first control signal generated suitable for receiving the controller, to the input
Clock signal carry out random delay operation, and carry out random delay operation duration reach the update cycle of delay duration when
It is fed back to the controller, so that the controller reconfigures the first control signal；The phase offset unit, with
The controller coupling, the second control signal generated suitable for receiving the controller carry out the clock signal of the input
Multi-channel time-delay and therefrom select all the way time delayed signal and reach signal post in the duration for receiving second control signal as output
It is fed back when the update cycle of knowledge to the controller, so that the controller reconfigures the second control signal；It is described
Frequency unit is coupled with the controller, controls signal suitable for receiving the third that the controller generates, to the input when
Clock signal carries out random scaling down processing, when the duration for receiving the third control signal reaches the frequency division value corresponding update cycle
When fed back to the controller so that the controller reconfigures third control signal；
The first control signal includes controlling the update of the delay duration information and the delay duration of the delay unit
Cycle information；The second control signal includes controlling signal identification information and the institute of the phase offset Unit selection output
State the update cycle information of signal identification information；Third control signal include control the frequency unit frequency division value and
The update cycle information of the frequency division value.
2. clock scrambling circuit as described in claim 1, which is characterized in that the phase offset unit includes: that N grades of delays are slow
Rush device and phase offset selecting unit, in which:
The N grades of delay buffer is coupled with the phase offset selecting unit, including N number of delay buffer, and being suitable for will be described
The clock signal of input carries out delay process, generates the different signal of the road N delay duration and is input to the phase offset
Selecting unit, N > 1；
The phase offset selecting unit is coupled with the controller, the second control letter generated suitable for receiving the controller
Number, it randomly chooses in the signal different from the road N delay duration and exports all the way.
3. clock scrambling circuit as described in claim 1, which is characterized in that the clock signal scrambling circuit includes that delay is single
Any two unit in member, phase offset unit and frequency unit, any two unit series connection, and it is one of single
Member inputs the clock signal, clock signal of another unit output by random scrambling processing.
4. clock scrambling circuit as described in claim 1, which is characterized in that the clock signal scrambling circuit includes: series connection
The delay unit, the phase offset unit and the frequency unit of connection.
5. clock scrambling circuit as described in claim 1, which is characterized in that the controller includes: mask register, described
Mask register is suitable for generating the mask of n bit, and carries out position and operation, obtained position with the random number of identical digit
It is n bit with result；Institute's rheme and result are the control signal, are comprised at least one of the following: first control
Signal, the second control signal and the third control signal.
6. clock scrambling circuit as claimed in claim 5, which is characterized in that the control signal includes the first control letter
Number, the second control signal and the third control signal, in which:
The first control signal is 0~n1Bit, in which: 0~m1Bit is to control the delay list
The delay duration information of member, m1+ 1~n1Bit is the update cycle information of the delay duration；
The second control signal is n-th1+ 1~n2Bit, in which: n-th1+ 1~m2Bit is described in control
The signal identification information of phase offset Unit selection, m2+ 1~n2Bit is the update of the selected signal identification
Cycle information；
The third control signal is n-th2+ 1~n bit, in which: n-th2+ 1~m3Bit is described in control
The frequency division value of frequency unit, m3+ 1~n bit is the update cycle information of the frequency division value；
Wherein, 0 < m1<n1<m2< n2<m3< n.
7. clock scrambling circuit as claimed in claim 6, which is characterized in that the controller further include: limitation value register,
Suitable for 0~m1Bit, m1+ 1~n1Bit, n-th1+ 1~m2Bit, m2+ 1~n2Position
Binary number, n-th2+ 1~m3Bit and m3The numerical value of+1~n bit is limited.
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