CN105894079A - Clock scrambling circuit - Google Patents
Clock scrambling circuit Download PDFInfo
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- CN105894079A CN105894079A CN201610255899.0A CN201610255899A CN105894079A CN 105894079 A CN105894079 A CN 105894079A CN 201610255899 A CN201610255899 A CN 201610255899A CN 105894079 A CN105894079 A CN 105894079A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
- G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
- G06K19/07363—Means for preventing undesired reading or writing from or onto record carriers by preventing analysis of the circuit, e.g. dynamic or static power analysis or current analysis
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Abstract
The invention provides a clock scrambling circuit. The clock scrambling circuit includes a controller and a clock signal scrambling circuit, wherein the controller is coupled with the clock signal scrambling circuit, thus being suitable for generating a control signal and inputting the control signal to the clock signal scrambling circuit; and the clock signal scrambling circuit is suitable for receiving the control signal, and performing random scrambling processing on the input clock signal. The clock scrambling circuit can improve the anti-attack performance of a security chip.
Description
Technical field
The present invention relates to information security field, particularly relate to a kind of clock scrambling circuit.
Background technology
In recent years, smart card techniques develops rapidly, and has been widely used in Bank Danamon card, social security card
Etc. multiple occasion.Along with the development of smart card techniques, the security performance of smart card increasingly comes into one's own.
In smart card detection standard, security test is proposed the highest requirement, not only need to ring faster
Answer speed, in addition it is also necessary to resist various attack, especially bypass attack (also referred to as side-channel attack) and fault
Injection attacks.
The safety chip of smart card in the calculating process carrying out cryptographic algorithm, safety chip consume electric current
Curve can comprise key information in certain sheet.Advanced attack technology can be divided by a plurality of current curve
Separate out key and then crack safety chip.
There is certain hidden danger in the security of existing safety chip.
Summary of the invention
Present invention solves the technical problem that the attack resistance performance being how to improve safety chip in smart card.
For solving above-mentioned technical problem, the embodiment of the present invention provides a kind of clock scrambling circuit, including: control
Device processed and clock signal scrambling circuit, wherein: described controller, with described clock signal scrambling circuit
Couple, be suitable to generate control signal and input to described clock signal scrambling circuit；Described clock signal adds
Disturb circuit, be suitable to receive described control signal, the clock signal of input is carried out random scrambling process.
Optionally, described clock signal scrambling circuit is suitable to phase place or the frequency of the clock signal to described input
At least one in rate carries out random scrambling process.
Optionally, described clock signal scrambling circuit include following at least one: delay unit, phase place are inclined
Move unit, frequency unit, wherein: described delay unit, couple with described controller, be suitable to receive institute
State the first control signal that controller generates, the clock signal of described input is carried out random delay operation；
Described phase offset unit, couples with described controller, is suitable to receive the second control that described controller generates
Signal processed, carries out multi-channel time-delay to the clock signal of described input and therefrom selects a road time delayed signal conduct
Output；Described frequency unit, couples with described controller, is suitable to receive the 3rd that described controller generates
Control signal, carries out random scaling down processing to the clock signal of described input.
Optionally, described phase offset unit includes: N level time delay buffer and phase offset select single
Unit, wherein: described N level time delay buffer, selects unit to couple, including N number of with described phase offset
Time delay buffer, is suitable to carry out the clock signal of described input delay process, generates N road delay duration
Different signal also inputs to described phase offset selection unit, N ＞ 1；Described phase offset selects
Unit, couples with described controller, is suitable to receive the second control signal that described controller generates, from institute
State and the signal that N road delay duration is different randomly chooses a road output.
Optionally, described clock signal scrambling circuit includes delay unit, phase offset unit and frequency dividing
Any two unit in unit, described any two unit is connected, and the input of one of them unit is described
Clock signal, another unit exports the clock signal processed through random scrambling.
Optionally, described clock signal scrambling circuit includes: the described delay unit that is connected in series, described
Phase offset unit and described frequency unit.
Optionally, described controller includes: mask register, and described mask controller is suitable to generate n position
The mask of binary number, and carry out position and operation with the random number of identical figure place, the position obtained and result are n
Bit；Institute's rheme and result are described control signal, including following at least one: described first
Control signal, described second control signal and described 3rd control signal.
Optionally, described control signal include described first control signal, described second control signal and
Described 3rd control signal, wherein: described first control signal is the 0th～n1Bit, wherein:
0th～m1Bit is the delay duration information controlling described delay unit, m1+ 1～n1Position two is entered
Number processed is the update cycle information of described delay duration；Described second control signal is n-th1+ 1～n2Position two
System number, wherein: n-th1+ 1～m2Bit is to control described phase offset to select Unit selection
Signal identification information, m2+ 1～n2Bit is the update cycle letter of the signal identification of described selection
Breath；Described 3rd control signal is n-th2+ 1～n bit, wherein: n-th2+ 1～m3Position binary system
Number is for controlling the frequency division value of described frequency unit, m3+ 1～n bit is the renewal of described frequency division value
Cycle information；Wherein, 0 < m1<n1<m2＜ n2<m3＜ n.
Optionally, described controller also includes: limits value register, is suitable to the 0th～m1Bit,
M1+ 1～n1Bit, n-th1+ 1～m2Bit, m2+ 1～n2Bit,
n2+ 1～m3Bit and m3The numerical value of+1～n bit limits.
Compared with prior art, the technical scheme of the embodiment of the present invention has the advantages that
Clock signal scrambling circuit receive controller generate control signal, input clock signal is carried out with
Machine scrambling processes.Clock signal after random scrambling processes is change at random, so that in safety chip
The current curve in portion is no longer rule change but change at random, attacks difficulty such that it is able to promote, and improves
The attack resistance performance of safety chip.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of clock scrambling circuit in the embodiment of the present invention；
Fig. 2 is the structural representation of the another kind of clock scrambling circuit in the embodiment of the present invention.
Detailed description of the invention
Safety chip in smart card in the calculating process carrying out cryptographic algorithm, safety chip consume electricity
Flow curve can comprise key information in certain sheet.Advanced attack technology can pass through a plurality of current curve
Analyze key, thus crack safety chip.
In embodiments of the present invention, clock signal scrambling circuit receives controller and generates control signal, to defeated
Enter clock signal carries out random scrambling process.Clock signal after random scrambling processes is change at random,
So that the current curve within safety chip is no longer rule change but change at random, such that it is able to
Promote and attack difficulty, improve the attack resistance performance of safety chip.
Understandable for enabling the above-mentioned purpose of the present invention, feature and beneficial effect to become apparent from, below in conjunction with
The specific embodiment of the present invention is described in detail by accompanying drawing.
With reference to Fig. 1, embodiments provide a kind of clock scrambling circuit, including: controller 11 with
Clock signal scrambling circuit 12, wherein:
Controller 11, couples with described clock signal scrambling circuit 12, is suitable to generate control signal and input
To clock signal scrambling circuit 12, thus realize the control to clock signal scrambling circuit 12；
Clock signal scrambling circuit 12, couples with described controller 11, is suitable to receive described controller 11
The control signal sent, and according to described control signal, the clock signal clk IN of input is added at random
Disturb process, obtain the output clock signal clk OUT processed through random scrambling；Wherein, to input
Clock signal clk IN carries out random scrambling process and refers to: the phase place to the clock signal clk IN of input
Or at least one in frequency carries out random scrambling process, namely: can be only to the clock signal inputted
The phase place of CLKIN carries out random scrambling process, it is also possible to the only frequency to the clock signal clk IN inputted
Carry out random scrambling process, it is also possible to phase place and frequency to the clock signal clk IN inputted are entered simultaneously
The random scrambling of row processes.
In being embodied as, described controller 11 can be processor of single chip computer, it is also possible to for data signal
The controllers such as processor (Digital Signal Processor, DSP).
After the phase place of the clock signal to input carries out random scrambling process, the phase of the clock signal obtained
Position is change at random；Accordingly, after the frequency of the clock signal to input carries out random scrambling process,
The frequency of the clock signal obtained also is change at random.So, the current curve within safety chip is just
It is no longer rule change, but change at random, therefore can promote attack difficulty, improve safety chip
Attack resistance performance.
In embodiments of the present invention, clock signal scrambling circuit can include delay unit, phase offset list
At least one in unit and frequency unit.In actual applications, can according to actual application scenarios,
Such as board area, production cost and security consideration, from delay unit, phase offset unit and
Frequency unit selects one or more composition clock signal scrambling circuit.
For example, it is contemplated that limited to board area, clock signal scrambling circuit can only include phase place inclined
Move unit.And for example, it is contemplated that the demand of high security, clock signal scrambling circuit can include simultaneously
Delay unit, phase offset unit and frequency unit, now, delay unit, phase offset unit with
And frequency unit three series connection.
In embodiments of the present invention, clock signal scrambling circuit can only include delay unit.Now,
Controller couples with delay unit, and clock signal inputs to delay unit.Controller produces the first control letter
Number, and input to delay unit, delay unit to be scrambled at random control.In the first control signal
In, include delay duration information and the update cycle information of delay duration controlling delay unit, prolong
Time duration information and the update cycle information of correspondence be random setting.
Delay unit, after receiving the first control signal, is believed according to the delay duration in the first control signal
Breath, selects corresponding delay duration, and the clock signal of input is carried out delay operation.Delay unit exists
Receive and start timing after the first control signal, when timing duration reaches the update cycle of delay duration to
Controller feeds back, so that controller reconfigures the update cycle of delay duration information and delay duration
Information.
In actual applications, delay unit can include multiple time delay gear, comprises in the first control signal
Delay duration information be time delay gear information.The delay duration that each time delay gear is corresponding is different,
The delay duration of time delay gear 1 correspondence can be 20ns, and the delay duration of time delay gear 2 correspondence can be
40ns, the delay duration of time delay gear 3 correspondence can be 60ns etc..
The time delay gear information correspondence time delay gear 1 comprised in the first control signal, time delay gear 1 is corresponding
Delay duration be 20ns, the update cycle information of delay duration is 5s.Then delay unit is receiving
After one control signal, the clock signal of input is carried out the time delay of 20ns, and after 5s, anti-to controller
The update cycle of feedback delay duration has reached, and now, controller can prolong for delay unit distribution again
Time duration information and the update cycle information of delay duration.
When it should be noted that controller randomly for delay unit distribution delay duration information and time delay
Long update cycle information.It is to say, previous time the first control signal generated of controller with after once
The first control signal generated can be different, the most uncorrelated.
In embodiments of the present invention, clock signal scrambling circuit can only include phase offset unit.This
Time, controller couples with phase offset unit, and clock signal inputs to phase offset unit.Controller produces
Raw second control signal, and input to phase offset unit, so that phase offset unit is scrambled at random
Control.
Phase offset unit includes that N level time delay buffer and phase offset coupled thereto select unit.
In N level time delay buffer, including N number of time delay buffer being cascaded, each time delay buffers
The delay duration of device can be the most identical, it is also possible to all different.N level time delay buffer is receiving input
During clock signal, the clock signal of input is carried out delay process, generates N road delay duration different
Signal and input to phase offset select unit, wherein, N ＞ 1.
The value of N can also set according to actual application scenarios, such as, sets N=7, i.e. phase offset
Unit includes 7 time delay buffers being cascaded.
In the second control signal, include and control the signal identification that phase offset selects Unit selection to export
The update cycle information of information and signal identification, the update cycle information of signal identification information and correspondence thereof
It is random setting.
Phase offset selection unit is after receiving the second control signal, according to the letter in the second control signal
Number identification information, selects a road of correspondence from the N road signal of the N level time delay buffer output received
Signal is as output.Phase offset selects unit to start timing after receiving the second control signal, works as meter
Feed back to controller, so that controller reconfigures letter during the update cycle that length reaches signal identification constantly
Number identification information and the update cycle information of signal identification.
Such as, in the second control signal, the signal identification information comprised is 2, namely delays from N level time delay
Rush and device selects the 2nd road signal as output.
It should be noted that controller is randomly for phase offset unit distribution signal identification information and letter
Number mark update cycle information.It is to say, previous time the second control signal generated of controller with after
The second control signal once generated is different, the most uncorrelated.
In embodiments of the present invention, clock signal scrambling circuit can only include frequency unit.Now,
Controller couples with frequency unit, and clock signal inputs to frequency unit.Controller produces the 3rd control letter
Number, and input to frequency unit, frequency unit to be scrambled at random control.In the 3rd control signal
In, include the frequency division value of frequency unit and the update cycle information of frequency division value of controlling, frequency division value and
Corresponding update cycle information is random setting.
Frequency unit is after receiving the 3rd control signal, according to the frequency division value in the 3rd control signal, right
The clock signal of input carries out the divide operation corresponding with frequency division value.Frequency unit is receiving the 3rd control
Start timing after signal, feed back to controller when timing duration reaches update cycle corresponding to frequency division value,
So that controller reconfigures the update cycle information of frequency division value and frequency division value.
Such as, in the 3rd control signal, the frequency division value comprised is 2.Frequency unit is receiving the 3rd control
After signal processed, the clock signal of input is carried out divide-by-two operations.
Similar, controller is at random for the update cycle letter of frequency unit distribution frequency division value and frequency division value
Breath.It is to say, previous time the 3rd control signal generated of controller with after the 3rd control that once generates
Signal is different, the most uncorrelated.
In embodiments of the present invention, clock signal scrambling circuit can also including, delay unit, phase place are inclined
Move any two unit in unit and frequency unit, two unit series connection, and one of them unit is defeated
Entering clock signal, another unit exports the clock signal processed through random scrambling.
Such as, clock signal scrambling circuit includes delay unit and phase offset unit, clock signal
Input is to delay unit.Delay unit is after receiving the first control signal that controller sends, to input
Clock signal carry out the delay operation corresponding with the first control signal.Clock after delay process
Signal inputs to phase offset unit, and phase offset unit is again to the clock signal after delay process
Process, the clock signal that output processes through random scrambling.
Phase offset unit includes that 7 grades of time delay buffers and phase offset select unit, 7 grades of time delay bufferings
Device uses the time delay buffer of 7 series connection.Clock after delay process is believed by 7 grades of time delay buffers
Number carry out time delay, generate the clock signal that 7 tunnel delay duration are different, and input to phase offset and select
Select unit.
Phase offset selects unit after receiving the second control signal that controller sends, and controls according to second
Signal processed, selects a road as output from the clock signal that 7 tunnel delay duration are different.
It is understood that when clock signal scrambling circuit only includes delay unit and phase offset list
During unit, clock signal can also first input to phase offset unit.Phase offset unit is receiving second
After control signal, select a road as output and defeated from 7 road signals of 7 grades of time delay buffer outputs
Enter to delay unit.Delay unit is after receiving the first control signal, by the output of phase offset unit
Signal carries out the delay operation of correspondence.
Similar, clock signal scrambling circuit can also only include delay unit and frequency unit, prolong
Shi Danyuan connects with frequency unit.First clock signal can be inputted to delay unit, will be at time delay
The clock signal of reason inputs to frequency unit, to carry out scaling down processing；First clock signal can also be inputted
To frequency unit, carry out scaling down processing, then the clock signal input through frequency dividing is carried out to delay unit
Delay operation.
Can also only include phase offset unit and frequency unit in clock signal scrambling circuit, phase place is inclined
Move unit to connect with frequency unit.Correspondingly, clock signal can also first input to phase offset unit,
Using the output of phase offset unit as the input of frequency unit；First clock signal input extremely can also be divided
Frequently unit, using the output of frequency unit as the input of phase offset unit.
Clock signal scrambling circuit can also include delay unit, phase offset unit and frequency dividing simultaneously
Unit.
With reference to Fig. 2, give the structure chart of another kind of clock scrambling circuit in the embodiment of the present invention.
Controller 11 respectively with delay unit 121, phase offset unit 122 and frequency unit 123 coupling
Connect.The control signal that controller 11 generates includes: the first control signal, the second control signal and the 3rd
Control signal, wherein: the first control signal is for being controlled delay unit 121, and second controls letter
Number for being controlled phase offset unit 122, the 3rd control signal is for entering frequency unit 123
Row controls.
Clock signal clk IN inputs to delay unit 121.When delay unit 121 receives the first control
During signal, according to the time delay gear information in the first control signal, select corresponding with time delay gear information
Delay duration, and the clock signal clk IN of input is carried out corresponding delay process.Through delay process
Clock signal input to phase offset unit 122.
Phase offset unit 122 includes that 7 grades of time delay buffers 1221 and phase offset select unit 1222.
7 grades of time delay buffers include 7 time delay buffers, are followed successively by D1～D7, by the clock through delay process
Signal processes, and generates the different signal of 7 tunnel delay duration and inputs to phase offset selection single
Unit 1222.Phase offset selection unit 1222 is according to the second control signal received, from 7 road signals
Select a road signal and input to frequency unit 123.
The phase offset received, according to the 3rd control signal received, is selected single by frequency unit 123
The signals of unit 1222 output carry out the divide operation of corresponding frequency division value, the fractional frequency signal finally given be through
Cross the clock signal clk OUT that random scrambling processes.
It is understood that it is all right between delay unit, phase offset unit and frequency unit three
There is the annexation of other forms multiple, the company provided is provided in Fig. 2 of the embodiment of the present invention
Connect schematic diagram.
Such as, clock signal is first inputted to frequency unit and first carry out divide operation, the clock letter after frequency dividing
Number input is to delay unit, and the clock signal through time delay inputs to phase offset unit again and selects,
The final signal selected is i.e. as the clock signal of output, namely the clock signal through random scrambling.
In being embodied as, controller can generate control signal in the way of using software, it would however also be possible to employ
The mode of hardware generates control signal.For realizing more quickly controlling effect, in one embodiment of the invention
In, controller uses the mode of hardware to generate control signal.
The flow process using the mode of hardware to generate control signal controller below illustrates.
It is provided with mask register in the controller.Mask register can generate covering of n bit
Code, and random number binary with n position carry out position and operation, the position of the n bit obtained and knot
Fruit can be used as the control signal that controller generates, namely the control signal that controller generates is that n position two is entered
Number processed.
When control signal includes multiple, the position of n bit and result can be divided into the most solely
Vertical data block, different pieces of information block is corresponding to different control signals.Such as, n=32, control signal bag
Include the first control signal, the second control signal and the 3rd control signal, then 32 bits are divided
Becoming 3 data blocks, the first data block is the 0th～7 of 32 bits, corresponds to the first control letter
Number；Second data block is the 8th～15 of 32 bits, corresponds to the second control signal；3rd
Data block is the 16th～31 of 32 bits, corresponds to the 3rd control signal.
The random number of n bit can use the randomizer of peripheral hardware to generate, it would however also be possible to employ control
Randomizer within device processed generates.
The size of n can be relevant to the unit number included in clock signal scrambling circuit.Clock signal scrambles
Unit number in circuit is the most, namely the number of controller control signal to be generated is the most, and n can get over
Greatly；Correspondingly, the unit number in clock signal scrambling circuit is the least, namely the control that controller is to be generated
The number of signal processed is the least, and n can be the least.
Such as, when only including phase offset unit in clock signal scrambling circuit, controller has only to generate
Second control signal, now n=8.And for example, clock signal scrambling circuit includes simultaneously delay unit and
Phase offset unit, now, controller needs to generate the first control signal and the second control signal, can
To arrange n=16.And for example, clock signal scrambling circuit includes delay unit, phase offset unit simultaneously
And during frequency unit, controller needs to generate the first control signal, the second control signal and the 3rd control
Signal processed, then can arrange n=32.
It is understood that the size of n can also with clock signal scrambling circuit included in unit number without
Closing, n is fixed value, namely no matter clock signal scrambling circuit includes how many unit, and the value of n is not
Become.Such as, n=32, when only including phase offset unit in clock signal scrambling circuit, n=32 are set；
When clock signal scrambling circuit includes delay unit, phase offset unit and frequency unit simultaneously, n
Remain as 32.
When n is fixed value, if the unit comprised in clock signal scrambling circuit is less, then can only choosing
Take a part therein as control signal, remaining figure place zero setting.
Such as, when clock signal scrambling circuit only includes phase offset unit, can only choose wherein
The the 0th～7 as the second control signal, the whole zero setting of remaining figure place.
In embodiments of the present invention, the position of n bit is with result, and each control signal is corresponding
Data block can also be divided into two parts.Such as, data block corresponding for the first control signal is divided into
Two parts, the tables of data of Part I is shown as delay duration information, and the tables of data of Part II is shown as prolongs
The update cycle information of Shi Shichang.
When clock signal scrambling circuit includes delay unit, phase offset unit and frequency unit simultaneously
Time, three data blocks all can be divided into two parts, wherein:
First control signal is the 0th～n1Bit, wherein: the 0th～m1Bit is that control is prolonged
The delay duration information of Shi Danyuan, m1+ 1～n1Position binary code is the update cycle information of delay duration；
Second control signal is n-th1+ 1～n2Bit, wherein: n-th1+ 1～m2Bit is
Control phase offset and select the signal identification information of Unit selection, m2+ 1～n2Bit is for selecting
The update cycle information of signal identification；
3rd control signal is n2+ 1～n bit, wherein: n-th2+ 1～m3Bit is control
Make the frequency division value of described frequency unit, m3+ 1～n bit is the update cycle letter of described frequency division value
Breath；n1、n2, n meet n1＜ n2＜ n.
In an embodiment of the present invention, n=32, wherein:
Corresponding first control signal of 0th～7 bits, wherein: the 0th～3 bits are first
Delay duration information in control signal, it is corresponding that the 4th～7 bits are expressed as delay duration information
Update cycle information；
8th～15 corresponding second control signals of bits, wherein: the 8th～11 bits are the
Signal identification information in two control signals, the 12nd～15 bits are the renewal that signal identification is corresponding
Cycle information；
Corresponding 3rd control signal of 16th～31 bits, wherein: the 15th～23 bits are
Frequency division value in 3rd control signal, the 24th～31 bits are the update cycle letter that frequency division value is corresponding
Breath.
In embodiments of the present invention, carry out with n position binary system random number due to the mask of n bit
Position and operation, the position therefore obtained is with result, and the numerical value in each data block is random.Also
Binary number corresponding to the i.e. first control signal, the second control signal and the 3rd control signal is all probably
Random.
For avoiding some value in above-mentioned three kinds of control signals bigger than normal or less than normal, can be for each
Binary number corresponding to control signal arranges the limits value of correspondence, limits each control signal corresponding
The span of binary number.
Such as, the 0th～n1Bit, for 0～m1Bit, its span of limit value is
Decimal number 1～6, the 0th～m in position with result1When the decimal number that bit is corresponding is 0,
Then automatically by position and the 0th～m in result1Bit is set to 001；In position with result the 0th～m1
When the decimal number that bit is corresponding is 7, then automatically by position and the 0th～m in result1Position binary system
Number is set to 110.
Correspondingly, m1+ 1～n1Bit, n-th1+ 1～m2Bit, m2+ 1～n2
Bit, n-th2+ 1～m3Bit and m3+ 1～n bit all can exist with
Limits value one to one, these limits values can preset according to the actual needs.
In embodiments of the present invention, limits value register can be provided with in the controller, will preset
Limits value be stored in advance in limits value register.
In conjunction with Fig. 2, in the position of n bit with result, n can be divided into 3 data blocks,
The most corresponding control signal of each data block.Controller can adjust the n that mask register is generated
Position binary code, determines whether that controlling certain unit performs random Scrambling Operation.
Such as, in the binary mask of n position, n-th1+ 1～n2Bit is all set to 0, then with
After n position random number carries out position and operates, the position of the n bit obtained and n-th in operation1+ 1～n2
Bit is all 0.Now, controller does not control phase offset unit and carries out clock signal at random
Controlling operation, phase offset unit can select the signal identification fixed as output.
Analogously, in the binary mask of n position, when the 0th～n1When bit is all set to 0,
Delay unit selects fixing time delay gear that input clock signal is carried out time delay；When n-th2+ 1～n position two is entered
When number processed is all set to 0, the frequency division value of frequency unit is also a fixed value.
It is to say, when clock signal scrambling circuit includes simultaneously delay unit, phase offset unit with
And during frequency unit, one or more can be selected defeated by the setting to control signal
The clock signal entered carries out random scrambling process.
It is understood that in other embodiments of the present invention, the value of above-mentioned n, n bit
Position can not repeat there is other form with the division etc. of result.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (9)
1. a clock scrambling circuit, it is characterised in that including: controller and clock signal scrambling circuit,
Wherein:
Described controller, couples with described clock signal scrambling circuit, is suitable to generate control signal and input to institute
State clock signal scrambling circuit；
Described clock signal scrambling circuit, is suitable to receive described control signal, to input clock signal carry out with
Machine scrambling processes.
2. clock scrambling circuit as claimed in claim 1, it is characterised in that described clock signal scrambling circuit
At least one be suitable in the phase place of the clock signal to described input or frequency carries out random scrambling process.
3. clock scrambling circuit as claimed in claim 2, it is characterised in that described clock signal scrambling circuit
Including following at least one: delay unit, phase offset unit, frequency unit, wherein:
Described delay unit, couples with described controller, is suitable to receive the first control letter that described controller generates
Number, the clock signal of described input is carried out random delay operation；
Described phase offset unit, couples with described controller, is suitable to receive the second control that described controller generates
Signal processed, carries out multi-channel time-delay to the clock signal of described input and therefrom selects a road time delayed signal conduct
Output；
Described frequency unit, couples with described controller, is suitable to receive the 3rd control letter that described controller generates
Number, the clock signal of described input is carried out random scaling down processing.
4. clock scrambling circuit as claimed in claim 3, it is characterised in that described phase offset unit includes:
N level time delay buffer and phase offset select unit, wherein:
Described N level time delay buffer, selects unit to couple with described phase offset, including N number of time delay buffer,
Be suitable to carry out the clock signal of described input delay process, generate the letter that N road delay duration is different
Number and input to described phase offset select unit, N ＞ 1；
Described phase offset selects unit, couples with described controller, is suitable to receive that described controller generates the
Two control signals, randomly choose a road output from the signal that described N road delay duration is different.
5. clock scrambling circuit as claimed in claim 3, it is characterised in that described clock signal scrambling circuit
Including any two unit in delay unit, phase offset unit and frequency unit, described any two
Individual unit is connected, and one of them unit inputs described clock signal, and the output of another unit is through random
The clock signal that scrambling processes.
6. clock scrambling circuit as claimed in claim 3, it is characterised in that described clock signal scrambling circuit
Including: the described delay unit being connected in series, described phase offset unit and described frequency unit.
7. clock scrambling circuit as claimed in claim 3, it is characterised in that described controller includes: mask
Register, described mask controller be suitable to generate n bit mask, and with identical figure place with
Machine number carries out position and operation, and the position obtained and result are n bit；Institute's rheme and result are described
Control signal, including following at least one: described first control signal, described second control signal and
Described 3rd control signal.
8. clock scrambling circuit as claimed in claim 7, it is characterised in that described control signal includes described
First control signal, described second control signal and described 3rd control signal, wherein:
Described first control signal is the 0th～n1Bit, wherein: the 0th～m1Bit is for controlling institute
State the delay duration information of delay unit, m1+ 1～n1Bit is the renewal of described delay duration
Cycle information；
Described second control signal is n-th1+ 1～n2Bit, wherein: n-th1+ 1～m2Bit is
Control described phase offset and select the signal identification information of Unit selection, m2+ 1～n2Bit is
The update cycle information of the signal identification of described selection；
Described 3rd control signal is n-th2+ 1～n bit, wherein: n-th2+ 1～m3Bit is
Control the frequency division value of described frequency unit, m3+ 1～n bit is the update cycle of described frequency division value
Information；
Wherein, 0 < m1<n1<m2＜ n2<m3＜ n.
9. clock scrambling circuit as claimed in claim 8, it is characterised in that described controller also includes: limit
Value register processed, is suitable to the 0th～m1Bit, m1+ 1～n1Bit, n-th1+ 1～m2
Bit, m2+ 1～n2Bit, n-th2+ 1～m3Bit and m3+ 1～n
The numerical value of bit limits.
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