CN108390648A - A kind of Gaussian white noise generator based on FPGA - Google Patents
A kind of Gaussian white noise generator based on FPGA Download PDFInfo
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- CN108390648A CN108390648A CN201810037910.5A CN201810037910A CN108390648A CN 108390648 A CN108390648 A CN 108390648A CN 201810037910 A CN201810037910 A CN 201810037910A CN 108390648 A CN108390648 A CN 108390648A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B29/00—Generation of noise currents and voltages
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Abstract
The present invention relates to a kind of Gaussian white noise generators based on FPGA, including communicate uniform random number generator module, address generating module, Gauss number RAM module, orthogonal conversion module and the quadratic sum correcting module of connection successively.The present invention is based on WALLACE algorithms, contribute to the white Gaussian noise that output speed is high, noise effects are good, and meet and realized in FPGA environment.
Description
Technical field
The present invention relates to signal processing technology field technical field, more particularly to a kind of white Gaussian noise hair based on FPGA
Raw device.
Background technology
Communicate and control system in, white Gaussian noise is very common noise signal, it is therefore desirable to utilize Gauss white noise
Acoustical signal source is tested and the interference free performance of checking system.Meanwhile in radio communication channel, it is often necessary to which white Gaussian noise is believed
Number source.So simple in structure, dependable performance a white Gaussian noise signal source is realized in design, have to system detectio very necessary
Meaning.Existing Gassian noise generator usually has physical noise generator and digital two class of composite noise generator.Although
Physical noise generator precision is relatively high, but realizes that circuit is complex, so more selecting digital make an uproar in engineering
Acoustic generator.Currently, many white Gaussian noise sources microprocessor and etc. realize in systems because they are by using letter
Number library can easily calculate sinusoidal and exponential function.But simulation velocity can be increased substantially using hardware emulator.
Invention content
The object of the present invention is in view of the shortcomings of the prior art, a kind of Gaussian white noise generator based on FPGA of design, base
In WALLACE algorithms, the white Gaussian noise that output speed is high, noise effects are good, and meets and realized in FPGA environment.
The invention is realized by the following technical scheme：
A kind of Gaussian white noise generator based on FPGA, which is characterized in that structure includes communicate connection successively uniform
Randomizer module, address generating module, Gauss number RAM module, orthogonal conversion module and quadratic sum correcting module；
The uniform random number generator module uses the integration algorithm of cellular automaton, utilizes the origin polynomial f of rank
(x)=x29+x2+ 1, the rule number for calculating the cellular automaton corresponding to origin multinomial is (0,100 1,000 1,001 0111
1100 1,000 1,001 0), and initial value is (0,001 0,010 1,101 1,010 0,101 11010)；The uniformly random number sequence generated
Arrange selection addresses of the UNIFORM as Gauss number RAM；The effect of random number be exactly upset 1024 Gauss numbers just
Initial value so that end value and the relevance of initial value are desalinated；
According to Wallace algorithms, orthogonal transformation needs four variables every time, therefore address generating module is in each clock week
It is interim to generate independent four addresses, it is denoted as p, q, r and s, address size 10bit respectively；Purpose is obtained in order to make
New Gauss number and the relevance of initial Gaussian random number reduce；This four addresses are simultaneously the input variable of orthogonal transformation
Gauss number RAM is provided, address and orthogonal transformation input new variables offer write address are provided；
Specific algorithm is as follows:Three 10bit variable start, stride and mask are defined, are calculated as follows:Start=
uniform[28:19]；
Stride={ uniform [18:10],1'b1}；
Mask=uniform [9:0]；
Four addresses are obtained by following formula:
The Gauss number RAM module is designed using twoport, is had two data with write-in and is read, RAM sizes 24*
1024；Initial value Gauss number be the obedience standard that is obtained with box-muller algorithms using the randn orders of matlab just
The random number of state distribution, and make its quadratic sum be 1 by normalization, quantify random number using the complement of two's two's complement of 24 bits, deposits
It stores up in the ROM that a size is 24*1024, when initialization, ROM values is written by RAM by counter, random selection address p,
Q, address is read in and read to two in r, s as Gauss number；Randomly choose orthogonal transformation output new variables or
Value of the Gaussian noise as write-in RAM is initialized in ROM；
The orthogonal conversion module carries out orthogonal transformation by two orthogonal matrixes to initial Gaussian random number, for just
Hand over matrix selection can there are many kinds of, in order to achieve the effect that preferably to generate Gauss number, the design selection below two
Kind orthogonal matrix:
Above two matrix uses in turn, in conversion every 1024 variables, uses A in turn0And A1；Due to turning
It changes in matrix and is only formed by 1 and -1, so actually only adding to initial Gaussian random number during conversion
The either operation of displacement；Such as a, b, c, d are four initial Gaussian random numbers for needing to carry out orthogonal conversion, are passing through A0
And A1Orthogonal conversion after, new a', b', c', d' is obtained, then can be denoted as:
A'=a-t, b'=t-b, c'=t-c, d'=t-d
A'=t-a, b'=b-t, c'=c-t, d'=d-t
Quadratic sum correcting module carries out quadratic sum amendment to the normalization gaussian variable that orthogonal transformation generates, and is needed
White Gaussian noise variable；Theoretically, if random number xi obeys standardized normal distribution N (0,1), G=A+Bx is definedi(A, B are normal
Number), then the quadratic sum of G obeys x2Distribution.In this module, the N number of new variables obtained for " wheel " only uses an amendment
Value G, the value by this " one wheel " first output valve x1It is calculated；The normalization variable that epicycle generates is multiplied by this correction value G,
The random sequence of an approximate Normal Distribution, as white Gaussian noise are just obtained；
According to Wallace algorithms, definitionThe initial value of G isHere N=
1024。
The present invention provides a kind of Gaussian white noise generators based on FPGA, and compared with prior art, the present invention is significantly
The complexity for reducing Gaussian white noise generator, obtained white Gaussian noise variance is approximately 1, is more suitable in FPGA real
It is existing.
Description of the drawings
Fig. 1 is that the present invention is based on the realization block diagrams of the Gaussian white noise generator of FPGA.
Specific implementation mode
The present invention is described further refering to attached drawing 1.
The present invention relates to a kind of Gaussian white noise generators based on FPGA, which is characterized in that structure includes communicating successively
The uniform random number generator module of connection, address generating module, Gauss number RAM module, orthogonal conversion module and square
And correcting module；
The uniform random number generator module uses the integration algorithm of cellular automaton, utilizes the origin polynomial f of rank
(x)=x29+x2+ 1, the rule number for calculating the cellular automaton corresponding to origin multinomial is (0,100 1,000 1,001 0111
1100 1,000 1,001 0), and initial value is (0,001 0,010 1,101 1,010 0,101 1,101 0)；The uniform random number of generation
Selection addresses of the sequence UNIFORM as Gauss number RAM；The effect of random number is exactly to upset 1024 Gauss numbers
Initial value so that end value and the relevance of initial value are desalinated；
According to Wallace algorithms, orthogonal transformation needs four variables every time, therefore address generating module is in each clock week
It is interim to generate independent four addresses, it is denoted as p, q, r and s, address size 10bit respectively；Purpose is obtained in order to make
New Gauss number and the relevance of initial Gaussian random number reduce；This four addresses are simultaneously the input variable of orthogonal transformation
Gauss number RAM is provided, address and orthogonal transformation input new variables offer write address are provided；
Specific algorithm is as follows:Three 10bit variable start, stride and mask are defined, are calculated as follows:Start=
uniform[28:19]；
Stride={ uniform [18:10],1'b1}；
Mask=uniform [9:0]；
Four addresses are obtained by following formula:
The Gauss number RAM module is designed using twoport, is had two data with write-in and is read, RAM sizes 24*
1024；Initial value Gauss number be the obedience standard that is obtained with box-muller algorithms using the randn orders of matlab just
The random number of state distribution, and make its quadratic sum be 1 by normalization, quantify random number using the complement of two's two's complement of 24 bits, deposits
It stores up in the ROM that a size is 24*1024, when initialization, ROM is normalized by the write-in of gaussian variable initial value by counter
Two in RAM, random selection address p, q, r, s are used as Gauss number to be read in and read address；It randomly chooses orthogonal
Value of the Gaussian noise as write-in RAM is initialized in transformation output new variables or ROM；
The orthogonal conversion module carries out orthogonal transformation by two orthogonal matrixes to initial Gaussian random number, for just
Hand over matrix selection can there are many kinds of, in order to achieve the effect that preferably to generate Gauss number, the design selection below two
Kind orthogonal matrix:
Above two matrix uses in turn, in conversion every 1024 variables, uses A in turn0And A1；Due to turning
It changes in matrix and is only formed by 1 and -1, so actually only adding to initial Gaussian random number during conversion
The either operation of displacement；Such as a, b, c, d are four initial Gaussian random numbers for needing to carry out orthogonal conversion, are passing through A0
And A1Orthogonal conversion after, new a', b', c', d' is obtained, then can be denoted as:
A'=a-t, b'=t-b, c'=t-c, d'=t-d
A'=t-a, b'=b-t, c'=c-t, d'=d-t
Quadratic sum correcting module carries out quadratic sum amendment to the normalization gaussian variable that orthogonal transformation generates, and is needed
White Gaussian noise variable；Theoretically, if random number xi obeys standardized normal distribution N (0,1), G=A+Bx is definedi(A, B are normal
Number), then the quadratic sum of G obeys x2Distribution.In this module, the N number of new variables obtained for " wheel " only uses an amendment
Value G, the value by this " one wheel " first output valve x1It is calculated；The normalization variable that epicycle generates is multiplied by this correction value G,
The random sequence of an approximate Normal Distribution, as white Gaussian noise are just obtained；
According to Wallace algorithms, definitionThe initial value of G isHere N=
1024。
The present invention in specific use,
Compared with prior art, the beneficial effects of the present invention are the complexity for substantially reducing device, obtained Gauss
White noise variance is approximately 1, is more suitable for realizing in FPGA.
As described above, you can the present invention is applied.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
Any one skilled in the art in the technical scope disclosed by the present invention, according to the technique and scheme of the present invention and its
Inventive concept is subject to equivalent substitution or change, should be covered by the protection scope of the present invention.
Claims (4)
1. a kind of Gaussian white noise generator based on FPGA, which is characterized in that structure include communicate successively connection it is uniform with
Machine number generator module, address generating module, Gauss number RAM module, orthogonal conversion module and quadratic sum correcting module；
The uniform random number generator module use cellular automaton integration algorithm, using rank origin polynomial f (x)=
x29+x2+ 1, the rule number for calculating the cellular automaton corresponding to origin multinomial is (0,100 1,000 1,001 0,111 1100
1000 1,001 0), and initial value is (0,001 0,010 1,101 1,010 0,101 1,101 0)；The uniformly random Number Sequence generated
Selection addresses of the UNIFORM as Gauss number RAM；The effect of random number is exactly upset 1024 Gauss numbers initial
Value so that end value and the relevance of initial value are desalinated；
Described address generation module generates independent four addresses in each clock cycle, is denoted as p, q, r and s, address respectively
Length is 10bit；Four addresses that address generating module generates provide Gauss number for the input variable of orthogonal transformation simultaneously
RAM reads address and orthogonal transformation input new variables provides write address；
The Gauss number RAM module is designed using twoport, is had two data with write-in and is read, RAM sizes 24*
1024；Initial value Gauss number be the obedience standard that is obtained with box-muller algorithms using the randn orders of matlab just
The random number of state distribution, and make its quadratic sum be 1 by normalization, quantify random number using the complement of two's two's complement of 24 bits, deposits
It stores up in the ROM that a size is 24*1024, when initialization, ROM values is written by RAM by counter, random selection address p,
Q, address is read in and read to two in r, s as Gauss number；Randomly choose orthogonal transformation output new variables or
Value of the Gaussian noise as write-in RAM is initialized in ROM；
The orthogonal conversion module carries out orthogonal transformation by two orthogonal matrixes to initial Gaussian random number；
The quadratic sum correcting module is used to carry out quadratic sum amendment to the normalization gaussian variable that orthogonal transformation generates, and is needed
The white Gaussian noise variable wanted.
2. a kind of Gaussian white noise generator implementation method based on FPGA, which is characterized in that include the following steps：
Uniformly random sequence, the uniformly random Number Sequence UNIFORM conducts of generation are generated by uniform random number generator module
Gauss number RAM module selects address；
Independent four addresses are generated in each clock cycle by address generating module, are denoted as p, q, r and s, address respectively
Length is 10bit, and for providing four variables for orthogonal conversion module, four addresses carry for the input variable of orthogonal transformation simultaneously
Address is read for Gauss number RAM and orthogonal transformation input new variables provides write address；
The write-in and reading of gaussian random sequence are carried out by Gauss number RAM module；
Orthogonal transformation is carried out to initial Gaussian random number by orthogonal conversion module；
Quadratic sum amendment is carried out to the normalization gaussian variable that orthogonal transformation generates by quadratic sum correcting module, is needed
White Gaussian noise variable.
3. the Gaussian white noise generator implementation method based on FPGA as claimed in claim 2, which is characterized in that
Described address generation module when generating independent four addresses in each clock cycle used method be：Define three
A 10bit variables start, stride and mask, are calculated as follows:
Start=uniform [28:19]；
Stride={ uniform [18:10],1'b1}；
Mask=uniform [9:0]；
Four addresses are obtained by following formula：
4. the Gaussian white noise generator implementation method based on FPGA as claimed in claim 2, which is characterized in that by orthogonal
When conversion module carries out orthogonal transformation to initial Gaussian random number, using two kinds of orthogonal matrixes of following feature：
Two kinds of matrixes use in turn, in conversion every 1024 variables, use A in turn0And A1。
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110855246A (en) * | 2019-11-08 | 2020-02-28 | 成都天奥测控技术有限公司 | Method for generating Gaussian white noise with arbitrary variance |
| RU2723271C1 (en) * | 2019-10-01 | 2020-06-09 | Акционерное общество "Концерн "Созвездие" | Method for generation of digital white gaussian noise using the wallace method |
| RU2723272C1 (en) * | 2019-10-01 | 2020-06-09 | Акционерное общество "Концерн "Созвездие" | Digital white gaussian noise generator by wallace method |
| CN112241253A (en) * | 2019-07-17 | 2021-01-19 | 富士通株式会社 | Random number generation device and random number generation method |
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| CN112241253A (en) * | 2019-07-17 | 2021-01-19 | 富士通株式会社 | Random number generation device and random number generation method |
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