CN116054827A

CN116054827A - Broadband digital array system synchronization method and device

Info

Publication number: CN116054827A
Application number: CN202310032810.4A
Authority: CN
Inventors: 梅勇; 陈航; 郑皓天; 何向霄; 陈羲聪
Original assignee: China South Industries Group Automation Research Institute
Current assignee: China South Industries Group Automation Research Institute
Priority date: 2023-01-10
Filing date: 2023-01-10
Publication date: 2023-05-02

Abstract

The invention discloses a synchronization method and a synchronization device of a broadband digital array system, wherein the method comprises the steps of obtaining the fluctuation value of multiple phase deviations of a target ADC chip; the target ADC chip is any ADC chip in the broadband digital array system; the phase deviation is generated by carrying out multiple power supply period tests on the target ADC chip by the upper computer; and after the fluctuation value is determined to exceed the set fluctuation threshold, judging whether the fluctuation value is regular or not. The self-synchronous test and self-synchronous debugging of the high-speed ADC chip can be realized quickly, and an external expensive instrument is not needed. And by using the TDC chip, under the condition of starting a calibration mode, the measurement accuracy can reach more than 45 ps. The testing precision is improved, the system adopts internal testing, and the lap joint of the testing cable is avoided. The measuring circuit has low power consumption, small volume, easy integration and small influence on the original system. The whole system synchronous test and the synchronous exception repair can be automatically completed.

Description

Broadband digital array system synchronization method and device

Technical Field

The invention relates to the technical field of system synchronization, in particular to a broadband digital array system synchronization method and device capable of realizing automatic synchronization test and automatic synchronization of a digital acquisition card and a system.

Background

In the broadband digital array system, with the increase of bandwidth and the application of radio frequency direct acquisition technology, a high-speed analog-digital converter (ADC: ana l og to Digita l Converter) based on JESD204B standard is applied to the digital array system, so that synchronization of multichannel signals in the digital array system is required to be realized based on JESD204B standard. However, due to environmental factor variations, assembly wiring, and the like in engineering applications, a large number of uncertain variations may be introduced, resulting in difficulty in implementing the system synchronization verification engineering.

In the prior art, the synchronous verification of the system needs to be manually completed, and the channel with synchronous abnormality needs to be manually checked, and a design engineer needs to manually adjust the time sequence phase according to the influence of the field environment after checking and determining the abnormal channel so as to eliminate the abnormality.

Meanwhile, when the unsynchronized channels are checked, other channels of the system are required to stop working or the system is required to be synchronized again, so that the normal use of the system is affected.

In addition, when the deterministic delay of the JESD204B subclass 1 of the multiple ADC chips is realized, as the ADC sampling rate and the JESD204B line rate are gradually increased, the design margin is reduced, and the deterministic delay test is more sensitive to the influences of a power supply period, temperature change and mechanical stress, so that the deterministic delay test is not easy to realize.

Therefore, how to provide a method for automatic synchronization of a system meeting the requirements of self-test, self-monitoring and automatic synchronization is an urgent need for technical solutions by those skilled in the art.

Disclosure of Invention

In view of the above, the present invention provides a broadband digital array system synchronization method and apparatus for overcoming or at least partially solving the above problems. Deterministic delays for the multi-chip ADC chip JESD204B subclass 1 can be achieved and are affected by power cycles, temperature variations, and mechanical stress within a controllable range. In a synchronous acquisition system formed by digital acquisition cards, the digital acquisition cards with abnormal work are ensured not to influence the system synchronization.

The invention provides the following scheme:

a broadband digital array system synchronization method, comprising:

acquiring a fluctuation value of multiple phase deviations of a target ADC chip; the target ADC chip is any ADC chip in the broadband digital array system; the phase deviation is generated by carrying out multiple power supply period tests on the target ADC chip by the upper computer;

after the fluctuation value is determined to exceed a set fluctuation threshold, judging whether the fluctuation value is regular or not;

determining whether the target ADC chip needs to be reworked or not by carrying out deterministic delay test on the target ADC chip to obtain a test result according to the determined irregularity;

and acquiring the deviation relation between the phase deviation and the sampling point after the regularity is determined, so that corresponding debugging is carried out according to the deviation relation to synchronize a target acquisition board with the broadband digital array system.

Preferably: and carrying out deterministic delay test on the target ADC chip by using a target test unit to obtain a test result.

Preferably: the target test unit is accessed into the broadband digital array system and is electrically connected with the target ADC chip.

Preferably: the target test unit comprises a flight time measurement chip and a combiner, the target ADC chip is connected with an FPGA chip, and the combiner and the FPGA chip are electrically connected with the flight time measurement chip; the target ADC chip is electrically connected with the combiner and the FPGA chip; the FPGA chip is used for controlling the flight time measuring chip to generate a first pulse and a second pulse, and the first pulse and the second pulse are used for measuring excitation serving as excitation power.

Preferably: and the transmission path of the first pulse is identical to the sum of the transmission path of the second pulse and the highest-order signal path of the FPGA chip through the design of wiring equal length.

Preferably: the time-of-flight measurement chip is a TDC-GP22 chip.

Preferably: the deterministic delay testing method comprises the following steps:

the FPGA chip outputs a starting pulse to the TDC chip;

the FPGA chip controls the TDC chip to generate the first pulse and the second pulse through an SP I serial bus;

the TDC chip measures time differences T1 and T2 between pulse signals input to a START pin and pulse signals input to STOP1 and STOP2 pins;

and the FPGA chip reads back the T1 and the T2 through the SPI bus, so that the FPGA chip obtains the value of the excitation power by calculating the T2-T1.

Preferably: acquiring the deviation relation between the phase deviation and the sampling point according to the determined regularity so as to carry out corresponding debugging according to the deviation relation to synchronize the target acquisition board with the broadband digital array system; comprising the following steps:

determining that the deviation between the phase deviation and the sampling point is +/-1, and adjusting SYSREF signal delay;

if the deviation between the phase deviation and the sampling point is confirmed to be +/-128, the RX Buffer Adjust 0x030 of the FPGA chip is regulated to be reduced from 32 to 1;

and if the deviation between the phase deviation and the sampling point is confirmed to be +/-8, the Sync signal delay of the FPGA chip is regulated.

Preferably: the method also comprises the step of determining that a new ADC chip is connected into the broadband digital array system;

providing a target synchronization window for the new ADC chip through a synchronization pulse selection switching circuit; the time of the target synchronization window is more than 2N times of the system synchronization pulse period, wherein N=1, 2 and 3 …; the system synchronization pulse is a continuous square wave signal with fixed frequency.

A broadband digital array system synchronization apparatus, comprising:

the fluctuation value acquisition unit is used for acquiring the fluctuation value of the multiple phase deviations of the target ADC chip; the target ADC chip is any ADC chip in the broadband digital array system; the phase deviation is generated by carrying out multiple power supply period tests on the target ADC chip by the upper computer;

the rule judging unit is used for judging whether the fluctuation value is regular or not after the fluctuation value exceeds a set fluctuation threshold value;

the irregular processing unit is used for determining that the target ADC chip is irregular and carrying out deterministic delay test on the target ADC chip to obtain a test result so as to determine whether the target ADC chip needs to be repaired or not according to the test result;

and the regular processing unit is used for determining that the phase deviation and sampling point deviation relation is obtained regularly, so that corresponding debugging is carried out according to the deviation relation to synchronize the target acquisition board with the broadband digital array system.

According to the specific embodiment provided by the invention, the invention discloses the following technical effects:

the method and the device for synchronizing the broadband digital array system can rapidly realize self-synchronizing test and self-synchronizing debugging of the high-speed ADC chip, and do not need external expensive instruments. And by using the TDC chip, under the condition of starting a calibration mode, the measurement accuracy can reach more than 45 ps. The testing precision is improved, the system adopts internal testing, and the lap joint of the testing cable is avoided. The measuring circuit has low power consumption, small volume, easy integration and small influence on the original system. The whole system synchronous test and the synchronous exception repair can be automatically completed.

In some preferred embodiments, the failure acquisition card is replaced without stopping the system from synchronizing acquisition. The synchronous self-checking test of the multichannel synchronous acquisition system is realized by using lower cost, and the fault test coverage rate of the system is improved.

Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments will be briefly described below. It is evident that the drawings in the following description are only some embodiments of the present invention and that other drawings may be obtained from these drawings by those of ordinary skill in the art without inventive effort.

FIG. 1 is a flow chart of a method for synchronizing a broadband digital array system according to an embodiment of the present invention;

FIG. 2 is a flow chart of an automated synchronous test method provided by an embodiment of the present invention;

FIG. 3 is a schematic diagram of a deterministic delay test performed by a target test unit according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a synchronization device of a broadband digital array system according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which are derived by a person skilled in the art based on the embodiments of the invention, fall within the scope of protection of the invention.

Referring to fig. 1, a method for synchronizing a broadband digital array system according to an embodiment of the present invention, as shown in fig. 1, may include:

According to the broadband digital array system synchronization method provided by the embodiment of the application, the remote upper computer can perform multiple power supply period tests on the target ADC chip through controlling the program-controlled switch, the fluctuation value of multiple phase differences is statistically analyzed, and if the fluctuation value of the phase difference exceeds a set threshold value, the phenomenon that the target ADC chip is out of synchronization with the system can be determined. And then judging whether the fluctuation of the fluctuation value is regular or not, and performing corresponding treatment according to whether the fluctuation value is regular or not by adopting a corresponding method, so that the problem of asynchronous target ADC chips is finally solved. For the irregular fluctuation condition, whether the factory return treatment needs to be dismantled or not can be judged through a deterministic delay test. If the target ADC chip cannot pass the deterministic test, the target ADC chip is determined to be detached for rollover maintenance. For the condition of the fluctuation rule, the hardware structure of the target ADC chip can be determined to be free of problems, and corresponding debugging can be carried out through the phase deviation and the deviation value of the sampling point, so that the target ADC chip is finally synchronous with the system. Through the mode, users can be effectively liberated, and self-test, self-monitoring and automatic synchronization can be realized without manual intervention.

In practical application, when the deterministic delay test is performed after the irregular fluctuation is determined, various modes may be adopted, for example, in one implementation manner, the embodiment of the application may further provide that the target test unit is used to perform the deterministic delay test on the target ADC chip to obtain a test result.

The target test unit provided by the embodiment of the application can be used as an independent unit, can be manufactured into an independent device, and can be accessed into a broadband digital array system when a deterministic delay test is required. The target test unit can also be connected into the broadband digital array system through a corresponding control component, and specifically, the target test unit is connected into the broadband digital array system and is electrically connected with the target ADC chip. The target test unit can be used as a part of a broadband digital array system, can be in a dormant state when the target test unit is not required to work, and can be awakened when the target test unit is required to work.

Specifically, the target test unit comprises a flight time measurement chip and a combiner, the target ADC chip is connected with an FPGA chip, and the combiner and the FPGA chip are electrically connected with the flight time measurement chip; the target ADC chip is electrically connected with the combiner and the FPGA chip; the FPGA chip is used for controlling the flight time measuring chip to generate a first pulse and a second pulse, and the first pulse and the second pulse are used for measuring excitation serving as excitation power. And the transmission path of the first pulse is identical to the sum of the transmission path of the second pulse and the highest-order signal path of the FPGA chip through the design of wiring equal length. The time-of-flight measurement chip is a TDC-GP22 chip.

The deterministic delay testing method comprises the following steps:

the FPGA chip outputs a starting pulse to the TDC chip;

and the FPGA chip reads back the T1 and the T2 through the SP I bus, so that the FPGA chip obtains the value of the excitation power by calculating the T2-T1.

The JESD204B standard defines deterministic Delay (DL) as the difference between the time that a frame-based sample arrives at the serial transmitter and the time that the frame-based sample is output from the serial receiver. The delay is measured in the frame clock domain and must be incrementally programmable at least for periods as low as the frame clock. According to the target test unit and the corresponding test method, the target ADC chip can be automatically subjected to deterministic delay test under the condition of no regularity, whether hardware damage exists on the target ADC chip can be determined through the deterministic delay test, and whether factory return maintenance is needed is further determined.

Aiming at the situation that the fluctuation value of the target ADC chip is regular, the condition that the target ADC chip is free from hardware damage can be determined, and automatic synchronous debugging can be performed on the target ADC chip, specifically, the determining regularly obtains the deviation relation between the phase deviation and the sampling point, so that corresponding debugging is performed according to the deviation relation, and the target acquisition board is synchronized with the broadband digital array system; comprising the following steps:

In practical application, the system synchronization debugging is needed to be performed on the newly accessed ADC chip after the newly accessed ADC chip in the broadband digital array system, and the traditional method is to uniformly adjust all the ADC chips after the system is powered off and then the power is supplied again, so that the normal operation of the system is influenced by time and labor. To address this issue, embodiments of the present application may provide for determining that a new ADC chip is connected to the broadband digital array system.

The embodiment of the application can adopt a mode of providing a target synchronization window of a form for the new ADC chip to enable the newly accessed ADC chip to carry out independent automatic synchronization. The new ADC chip may be an ADC chip that is repaired after the repair disassembly for factory return is determined. The synchronization window is a time window for the digital acquisition card to respond to an external synchronization signal, and the synchronization window can be closed after more than two times of synchronization events are automatically captured by the synchronization window.

The broadband digital array system synchronization method provided by the embodiment of the application realizes the deterministic delay of JESD204B subclass 1 of multiple ADC chips, and the deterministic delay is influenced by the power supply period, temperature change and mechanical stress in a controllable range. In the synchronous acquisition system, the re-accessed digital acquisition card can be ensured to automatically complete the synchronization with the system without affecting the continuous work of the original digital acquisition card. In a synchronous acquisition system formed by digital acquisition cards, the digital acquisition cards with abnormal work are ensured not to influence the system synchronization.

When the broadband digital array system synchronization method provided by the embodiment of the application is specifically implemented, automatic synchronization test is performed first.

The method comprises the steps that firstly, a remote upper computer performs multiple power supply period tests on test equipment through controlling a program control switch, the fluctuation value of multiple phase differences is statistically analyzed, and if the fluctuation value of the phase differences exceeds a set threshold and is irregular, the automatic deterministic delay test is independently performed on the acquisition board card for eliminating abnormal channels.

And secondly, correspondingly, the phase fluctuation value exceeds the threshold value and is regular, and the software performs classification processing according to the specific situation of the rule, as shown in fig. 2.

And thirdly, after the debugging in the steps is completed, synchronous function verification is carried out until all channels are normal.

And carrying out automatic deterministic delay test on irregular conditions determined in the automatic synchronous test.

As shown in fig. 3, the TDC-GP22 is a time-of-flight measurement chip, which generates two excitation pulses for DL measurement excitation, pulse 1 (first pulse) is connected to the ADC input through a combiner to complete the quantized acquisition of pulse 1, and then the quantized data is transmitted to the FPGA through the JESD204B bus, and the FPGA uses the highest bit (MSB) of the acquired quantized code value as the output pulse signal to transmit to the STOP2 pin of the TDC-GP22 chip. Pulse 2 (the second pulse) is routed back through the printed board to the TDC chip STOP1 pin, where the pulse 1 path = pulse signal 2 path plus MSB signal path is routed through a wire equal length design.

The testing process comprises the following steps: the FPGA outputs a starting pulse to the TDC chip- > the FPGA controls the TDC chip to generate a pulse 1 and a pulse 2- > the TDC chip through the SPI serial bus to measure the time difference T1 and T2- > between the pulse signal input to the START pin and the pulse signals input to the STOP1 and STOP2 pins, the FPGA reads back the T1 and the T2 through the SPI bus, and the FPGA can obtain a DL value- > waiting for the next test by calculating the T2-T1.

When the target ADC chip is accessed to the system again or other ADC chips are accessed to the system for the first time after the maintenance of the target ADC chip is finished, the system synchronization pulse design is adopted, and the system is automatically synchronized on the premise that the normal working state of other components is not influenced.

1. The system synchronization pulses are designed as continuous square wave signals of fixed frequency.

2. The acquisition card is provided with a synchronous pulse selection switching circuit which can be switched according to own synchronous requirements, so that a synchronous window is obtained to complete self-synchronization, and the whole system operation is not affected.

3. The "synchronization window" time is more than 2N times (n=1, 2,3 …) the synchronization pulse period.

Therefore, the synchronization method of the broadband digital array system provided by the embodiment of the application can ensure that the phase alignment of the device_cIk (sampling clock) is realized on each ADC chip inside the board. An appropriate signal delay adjustment mechanism is used to ensure that the setup and hold times (relative to device_clks) for capturing the SYSREF signal are met on each ADC chip and on the FPGA. The release point (E l ast ic Buffer Re l ease Poi nts) of the appropriate RBD (receive delay buffer) is designed in the JESD204B receiver to ensure deterministic delay between the JESD204B transmitter and receiver. The clock distribution chip of the digital acquisition card is designed with a proper 'synchronous window' to ensure that each set of digital acquisition card enters a synchronous network and can automatically complete synchronous action through synchronous pulse. The proper Sync signal pulse width and period are designed, and a 'synchronization window' which is used for ensuring that any digital acquisition card in the system is synchronously arranged can capture more than 2 'synchronization events' to complete synchronization with the system. The hardware design ensures that the state of abnormal failure of the digital acquisition card is a safe failure state. The safety failure refers to that when the digital acquisition card works abnormally, all interfaces interconnected with the outside cannot influence other equipment outside. Self-test and self-synchronization of the system are realized.

In summary, the wideband digital array system synchronization method provided in the embodiments of the present application does not require external expensive instruments. And by using the TDC chip, under the condition of starting a calibration mode, the measurement accuracy can reach more than 45 ps. The measuring circuit has low power consumption, small volume, easy integration and small influence on the original system. The whole system synchronous test and the synchronous exception repair are automatically completed. And the fault acquisition card is replaced without stopping the synchronous acquisition work of the system.

Referring to fig. 4, an embodiment of the present application may further provide a broadband digital array system synchronization apparatus, as shown in fig. 4, which may include:

a fluctuation value acquisition unit 401, configured to acquire a fluctuation value of a plurality of phase deviations of a target ADC chip; the target ADC chip is any ADC chip in the broadband digital array system; the phase deviation is generated by carrying out multiple power supply period tests on the target ADC chip by the upper computer;

a rule judging unit 402, configured to determine whether the fluctuation value exceeds a set fluctuation threshold value, and then judge whether the fluctuation value is regular;

an irregular processing unit 403, configured to determine that the target ADC chip is irregular, and perform a deterministic delay test on the target ADC chip to obtain a test result, so as to determine whether the target ADC chip needs to be reworked according to the test result;

and the regular processing unit 404 is configured to determine that the phase deviation and the sampling point deviation relationship are obtained regularly, so that corresponding debugging is performed according to the deviation relationship to synchronize the target acquisition board with the broadband digital array system.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

From the description of the embodiments above, it will be apparent to those skilled in the art that the present application may be implemented in software plus the necessary general hardware platform. Based on such understanding, the technical solutions of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a storage medium, such as a ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform the methods described in the embodiments or some parts of the embodiments of the present application.

In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for a system or system embodiment, since it is substantially similar to a method embodiment, the description is relatively simple, with reference to the description of the method embodiment being made in part. The systems and system embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.

The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A method for synchronizing a broadband digital array system, comprising:

2. The method for synchronizing a broadband digital array system according to claim 1, wherein a target test unit is used to perform deterministic delay testing on the target ADC chip to obtain a test result.

3. The method of claim 2, wherein the target test unit is connected to the broadband digital array system and electrically connected to the target ADC chip.

4. The method for synchronizing a broadband digital array system according to claim 2, wherein the target test unit comprises a time-of-flight measurement chip and a combiner, the target ADC chip is connected with an FPGA chip, and the combiner and the FPGA chip are electrically connected with the time-of-flight measurement chip; the target ADC chip is electrically connected with the combiner and the FPGA chip; the FPGA chip is used for controlling the flight time measuring chip to generate a first pulse and a second pulse, and the first pulse and the second pulse are used for measuring excitation serving as excitation power.

5. The method according to claim 4, wherein the transmission path of the first pulse is identical to the sum of the transmission path of the second pulse and the highest-order signal path of the FPGA chip by a wire equal-length design.

6. The method of claim 5, wherein the time-of-flight measurement chip is a TDC-GP22 chip.

7. The broadband digital array system synchronization method according to claim 6, wherein the deterministic delay testing method comprises:

the FPGA chip outputs a starting pulse to the TDC chip;

the FPGA chip controls the TDC chip to generate the first pulse and the second pulse through an SPI serial bus;

8. The method for synchronizing a broadband digital array system according to claim 4, wherein the determining regularly obtains a deviation relation between the phase deviation and the sampling point, so as to synchronize the target acquisition board with the broadband digital array system by performing corresponding debugging according to the deviation relation; comprising the following steps:

9. The method of claim 1, further comprising determining that a new ADC chip is connected to the broadband digital array system;

10. A broadband digital array system synchronization apparatus, comprising: