CN114564067B - Low-dropout linear voltage regulator with high power supply rejection ratio - Google Patents
Low-dropout linear voltage regulator with high power supply rejection ratio Download PDFInfo
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Abstract
The invention relates to a low-dropout linear voltage regulator with a high power supply rejection ratio, which comprises a first-stage error amplifier, a second-stage common-source amplifier, a current mirror, a feedback loop and an output load, wherein the grid electrode of the second-stage common-source amplifier is connected with the first-stage error amplifier, the drain electrode of the second-stage common-source amplifier is connected with the current mirror, and the source electrode of the second-stage common-source amplifier is grounded; the feedback loop and the output load are connected in parallel and then connected with the current mirror, and a compensation capacitor is arranged in the first-stage error amplifier. The invention can improve the power supply inhibition characteristic, reduce the number of devices and reduce the complexity of the structure.
Description
Technical Field
The invention relates to the technical field of low-dropout linear voltage regulators, in particular to a low-dropout linear voltage regulator with a high power supply rejection ratio.
Background
The low dropout linear regulator (Low Dropout regulator, LDO) is used as one of the power management chips, and has the advantages of small area, few peripheral devices, simple structure, no ripple, low noise and the like. The LDO is usually used as a power supply terminal of a chip, and the power obtained from the DC terminal is converted by the LDO to power other modules, so that the power supply rejection ratio (Power Supply Rejection, PSR) is required to be high.
The existing linear voltage stabilizer is generally composed of an error amplifier, a driving buffer, a power tube and an off-chip capacitor. The error amplifier provides high DC gain, the driving buffer provides driving force for the grid electrode of the power tube, the power tube provides enough current according to the output load, and the off-chip capacitor stabilizes the output voltage. While a large open-loop gain is required for the LDO to obtain a good power supply rejection characteristic at low frequencies, the power supply rejection characteristic is still drastically degraded even with a large open-loop gain as the frequency increases. Common methods for improving the power supply rejection characteristics are: the ripple wave or noise of a certain frequency band of the sampling power supply is added to the output end of the error amplifier, and the ripple wave or noise is overlapped with the output voltage of the error amplifier to jointly control the switch of the adjusting tube. However, this approach requires additional summing circuitry, which increases the chip area and complexity of the loop stabilization design.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a low-dropout linear voltage regulator with a high power supply rejection ratio, which can reduce the number of devices and reduce the structural complexity on the basis of ensuring the high power supply rejection ratio.
The invention provides a low-dropout linear voltage regulator with a high power supply rejection ratio, which comprises a first-stage error amplifier, a second-stage common-source amplifier, a current mirror, a feedback loop and an output load, wherein the grid electrode of the second-stage common-source amplifier is connected with the first-stage error amplifier, the drain electrode of the second-stage common-source amplifier is connected with the current mirror, and the source electrode of the second-stage common-source amplifier is grounded; the feedback loop and the output load are connected in parallel and then connected with the current mirror, and a compensation capacitor is arranged in the first-stage error amplifier.
Further, the first-stage error amplifier comprises a first transistor and a second transistor which provide tail current sources, wherein the grid electrode of the first transistor inputs first bias voltage, the drain electrode of the first transistor is connected with the source electrode of the second transistor, and the source electrode of the first transistor is grounded; the gate of the second transistor inputs a second bias voltage.
Further, the first-stage error amplifier further comprises a first input tube, a second input tube, a third input tube and a fourth input tube, wherein the grid electrode of the first input tube inputs reference voltage, the drain electrode of the first input tube is connected with the source electrode of the third input tube, and the source electrode of the first input tube is connected with the drain electrode of the second transistor; the grid electrode of the second input tube inputs feedback voltage, the drain electrode of the second input tube is connected with the source electrode of the fourth input tube, and the source electrode of the second input tube is connected with the drain electrode of the second transistor; the grid electrode of the third input tube inputs a third bias voltage, and the source electrode of the third input tube is connected with the drain electrode of the first input tube; and the grid electrode of the fourth input tube is input with a third bias voltage, and the source electrode of the fourth input tube is connected with the drain electrode of the second input tube.
Further, the first-stage error amplifier further comprises a first current mirror load, a second current mirror load, a third current mirror load and a fourth current mirror load, wherein the grid electrode of the first current mirror load is connected with the grid electrode of the second current mirror load, and the source electrode of the first current mirror load is connected with the drain electrode of the third current mirror load; the grid electrode of the second current mirror load is connected with the grid electrode of the first current mirror load, and the source electrode of the second current mirror load is connected with the drain electrode of the fourth current mirror load; the grid electrode of the third current mirror load is connected with the grid electrode of the fourth current mirror load, the drain electrode of the third current mirror load is respectively connected with the source electrode of the first current mirror load and the drain electrode of the third input tube, and the source electrode of the third current mirror load is connected with the power supply end; the grid electrode of the fourth current mirror load is connected with the grid electrode of the third current mirror load, the drain electrode of the fourth current mirror load is respectively connected with the source electrode of the second current mirror load and the drain electrode of the fourth input tube, and the source electrode of the fourth current mirror load is connected with the power supply end; the gates of the first and second current mirror loads input a fourth bias voltage, and the gates of the third and fourth current mirror loads input a fifth bias voltage.
Further, one end of the compensation capacitor is connected with the power supply end, and the other end of the compensation capacitor is connected with the drain electrode of the first current mirror load.
Further, the first-stage error amplifier further comprises a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube, wherein the grid electrode of the first MOS tube is respectively connected with the grid electrode of the second MOS tube and the drain electrode of the third MOS tube, the drain electrode is connected with the source electrode of the third MOS tube, and the source electrode is grounded; the grid electrode of the second MOS tube is connected with the grid electrode of the first MOS tube, the drain electrode of the second MOS tube is connected with the source electrode of the fourth MOS tube, and the source electrode is grounded; the grid electrode of the third MOS tube is connected with the grid electrode of the fourth MOS tube, the drain electrode of the third MOS tube is respectively connected with the drain electrode of the first current mirror load and the grid electrode of the first MOS tube, and the source electrode of the third MOS tube is connected with the drain electrode of the first MOS tube; the grid electrode of the fourth MOS tube is connected with the grid electrode of the third MOS tube, the drain electrode of the fourth MOS tube is connected with the drain electrode of the second current mirror load, and the source electrode of the fourth MOS tube is connected with the drain electrode of the second MOS tube; and a sixth bias voltage is input to the grid electrode of the third MOS tube and the grid electrode of the fourth MOS tube.
Further, the drain electrode of the second current mirror load and the drain electrode of the fourth MOS tube are connected with the output end of the first-stage error amplifier, and the output end of the first-stage error amplifier is connected with the grid electrode of the second-stage common source amplifier.
Further, the current mirror M1 includes a third transistor and a power transistor, where a gate of the third transistor is connected to a gate of the power transistor and a drain of the second stage common source amplifier, a drain is connected to a drain of the second stage common source amplifier, and a source is connected to a power supply terminal of the first stage error amplifier; and the grid electrode of the power tube is connected with the grid electrode of the third transistor, the source electrode of the power tube is connected with the power end of the first-stage error amplifier, and the drain electrode of the power tube is connected with the feedback loop and the output load. And, the drain electrode of the power tube MPFET is connected to the output terminal VOUT of the whole low dropout linear regulator.
Further, the feedback loop comprises a first feedback resistor and a second feedback resistor which are connected in series, and the common end of the first feedback resistor and the feedback resistor outputs the feedback voltage.
Further, the output load comprises a load capacitor and a load resistor, and the load capacitor and the load resistor are arranged in parallel.
According to the invention, the compensation capacitor is connected between the power end of the error amplifier and the current mirror load, when the power voltage is changed, the current change direction of the compensation capacitor passage is different from the current change direction generated by the output end of the second-stage common source amplifier, and the current is superposed at the output end to reduce the change amount of the total output voltage, so that the power suppression characteristic of the LDO is improved. Meanwhile, the second-stage common source amplifier adopts an N-type common source amplifier structure, and adopts a diode connection method of a MOS transistor as a load, so that the second-stage common source amplifier has good power supply inhibition characteristic. In addition, the invention reduces the number of devices and reduces the complexity of the structure.
Drawings
Fig. 1 is a schematic diagram of a low dropout linear regulator having a high power supply rejection ratio according to the present invention.
Fig. 2 is a graph of current Δiout1 as a function of frequency in fig. 1.
Fig. 3 is a graph of current Δiout2 as a function of frequency in fig. 1.
Fig. 4 is a graph of closed loop output impedance Zout of the low dropout linear regulator of fig. 1 as a function of frequency.
Fig. 5 is a graph showing a comparison of the simulation results of the compensated capacitor CP and the uncompensated capacitor CP.
Detailed Description
Preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
As shown in fig. 1, the low dropout linear regulator with high power supply rejection ratio according to the present invention includes a first stage error amplifier EA, a second stage common source amplifier MN11, a current mirror M1, a feedback loop, and an output load, wherein a gate of the second stage common source amplifier MN11 is connected to an output terminal of the first stage error amplifier EA, a drain is connected to the current mirror M1, and a source is grounded; the feedback loop and the output load are connected in parallel and then connected with a current mirror M1, and a compensation capacitor CP is arranged in the first-stage error amplifier EA.
The first stage error amplifier EA includes a first transistor MN1 and a second transistor MN2 that provide tail current sources. The gate of the first transistor MN1 inputs a first bias voltage Vbias6, the drain is connected to the source of the second transistor MN2, and the source is grounded; the gate of the second transistor MN2 inputs the second bias voltage Vbias5.
The first stage error amplifier EA further includes a first input pipe MN3, a second input pipe MN4, a third input pipe MN5, and a fourth input pipe MN6. The gate of the first input transistor MN3 is a forward input terminal, and is used for inputting the reference voltage VREF, the drain thereof is connected to the source of the third input transistor MN5, and the source thereof is connected to the drain of the second transistor MN 2. The gate of the second input transistor MN4 is an inverting input terminal for inputting the feedback voltage VFB, the drain thereof is connected to the source of the fourth input transistor MN6, and the source thereof is connected to the drain of the second transistor MN 2. The gate of the third input tube MN5 is configured to input the third bias voltage vbias_in, and the source is connected to the drain of the first input tube MN 3. The gate of the fourth input tube MN6 also inputs the third bias voltage vbias_in, and the source is connected to the drain of the second input tube MN 4.
The first stage error amplifier EA further includes a first current mirror load MP1, a second current mirror load MP2, a third current mirror load MP3, and a fourth current mirror load MP4. The gate of the first current mirror load MP1 is connected to the gate of the second current mirror load MP2, and the source is connected to the drain of the third current mirror load MP 3. The grid electrode of the second current mirror load MP2 is connected with the grid electrode of the first current mirror load MP1, and the source electrode is connected with the drain electrode of the fourth current mirror load MP4. The grid electrode of the third current mirror load MP3 is connected with the grid electrode of the fourth current mirror load MP4, the drain electrode is respectively connected with the source electrode of the first current mirror load MP1 and the drain electrode of the third input tube MN5, and the source electrode is connected with the power supply end VDD. The grid electrode of the fourth current mirror load MP4 is connected with the grid electrode of the third current mirror load MP3, the drain electrode is respectively connected with the source electrode of the second current mirror load MP2 and the drain electrode of the fourth input tube MN6, and the source electrode is connected with the power supply end VDD. The gates of the first and second current mirror loads MP1 and MP2 input a fourth bias voltage Vbias2, and the gates of the third and fourth current mirror loads MP3 and MP4 input a fifth bias voltage Vbias3. And, one end of the compensation capacitor CP is connected to the power supply terminal VDD, and the other end is connected to the drain of the first current mirror load MP 1.
The first-stage error amplifier EA further comprises a first MOS tube MN7, a second MOS tube MN8, a third MOS tube MN9 and a fourth MOS tube MN10. The gate of the first MOS transistor MN7 is connected to the gate of the second MOS transistor MN8 and the drain of the third MOS transistor MN9, respectively, and the drain is connected to the source of the third MOS transistor MN9, where the source is grounded. The grid electrode of the second MOS tube MN8 is connected with the grid electrode of the first MOS tube MN7, the drain electrode is connected with the source electrode of the fourth MOS tube MN10, and the source electrode is grounded. The grid electrode of the third MOS tube MN9 is connected with the grid electrode of the fourth MOS tube MN10, the drain electrode is respectively connected with the drain electrode of the first current mirror load MP1 and the grid electrode of the first MOS tube MN7, and the source electrode is connected with the drain electrode of the first MOS tube MN 7. The grid electrode of the fourth MOS tube MN10 is connected with the grid electrode of the third MOS tube MN9, the drain electrode is connected with the drain electrode of the second current mirror load MP2, and the source electrode is connected with the drain electrode of the second MOS tube MN 8. Therefore, one end of the compensation capacitor CP connected to the drain of the first current mirror load MP1 is further connected to the gate of the first MOS transistor MN7, the gate of the second MOS transistor MN8, and the drain of the third MOS transistor MN 9. In addition, the gate of the third MOS transistor MN9 and the gate of the fourth MOS transistor MN10 input the sixth bias voltage Vbias1.
The drain electrode of the second current mirror load MP2 and the drain electrode of the fourth MOS transistor MN10 are both connected to the output terminal ea_out of the first stage error amplifier EA, and the output terminal ea_out of the first stage error amplifier EA is connected to the gate electrode of the second stage common source amplifier MN 11.
Because the transistor can amplify the signal only when working in the saturation state, the amplifier can work normally, so that the first stage error amplifier EA is set with proper bias voltage, each transistor works in the saturation region to generate stable current, and the current is converted into stable voltage through the equivalent resistance of the diode connected transistor.
The current mirror M1 includes a third transistor MP5 and a power transistor MPFET. The gate of the third transistor MP5 is connected to the gate of the power transistor MPFET and the drain of the second-stage common-source amplifier MN11, respectively, the drain is also connected to the drain of the second-stage common-source amplifier MN11, and the source is connected to the power supply terminal VDD of the first-stage error amplifier EA, thereby forming a MOS diode structure. The gate of the power transistor MPFET is connected to the gate of the third transistor MP5, the source is connected to the power supply terminal VDD of the first stage error amplifier EA, the drain is connected to the feedback loop and the output load in parallel, and the drain is grounded through the feedback loop and the output load in parallel. Therefore, the drain of the power tube MPFET is connected to the output terminal VOUT of the whole low dropout linear regulator. The gate and the drain of the third transistor MP5 are connected to each other and commonly connected to the drain of the second stage common source amplifier MN11, and the diode connection method of the MOS transistor is configured to make the output impedance of the second stage common source amplifier MN11 smaller, which is advantageous for improving the power supply rejection characteristic.
The feedback loop includes a first feedback resistor RF1 and a second feedback resistor RF2 connected in series, wherein a common terminal of the first feedback resistor RF1 and the second feedback resistor RF2 outputs a feedback voltage VFB (i.e., a feedback voltage VFB input to the gate of the second input tube MN 4), and the feedback voltage VFB is generated by dividing an output voltage of the low dropout linear regulator by the first feedback resistor RF1 and the second feedback resistor RF 2.
The output load includes a load capacitor CL and a load resistor Rload, which are arranged in parallel.
The output voltage of the first stage error amplifier EA is determined by comparing the reference voltage VREF input to the first input tube MN3 and the feedback voltage VFB input to the second input tube MN4 in the first stage error amplifier EA: when the reference voltage VREF is greater than the feedback voltage VFB, the output voltage of the first-stage error amplifier EA becomes large; when the reference voltage VREF is smaller than the feedback voltage VFB, the output voltage of the error amplifier becomes smaller; when the reference voltage VREF is equal to the feedback voltage VFB, the output voltage of the first stage error amplifier EA remains unchanged. The output voltage of the first-stage error amplifier EA is input to the second-stage common source amplifier MN11, and the output voltage amplified by the second-stage common source amplifier MN11 is input to the current mirror M1 to control the gate voltage of the power transistor MPFET, thereby controlling the conduction of the power transistor MPFET.
The electric signal generated when the low dropout linear voltage regulator of the present invention works has two paths.
Path 1 is: the electric signal generated by the power supply end VDD of the first-stage error amplifier EA reaches the drain electrode of the third MOS transistor MN9 through the compensation capacitor CP, then reaches the gate electrode of the second MOS transistor MN8 through the drain electrode of the third MOS transistor MN9, and is converted from the gate electrode of the second MOS transistor MN8 to the drain electrode of the fourth MOS transistor MN10, that is, reaches the output end ea_out of the first-stage error amplifier. Then, the output terminal ea_out of the first stage error amplifier flows to the second stage common source amplifier MN11, passes through the second stage common source amplifier MN11, reaches the drain of the third transistor MP5, then reaches the gate of the power transistor MPFET through the diode connection of the third transistor MP5, and finally reaches the drain of the power transistor MPFET, i.e. the output terminal VOUT of the low dropout linear regulator.
Path 2 is: the electric signal generated by the power supply terminal VDD of the first stage error amplifier EA passes through the third transistor MP5 to reach the drain of the second stage common source amplifier MN11, from the drain of the second stage common source amplifier MN11 to reach the gate of the power transistor MPFET, and then to reach the drain of the power transistor MPFET, i.e., the output terminal VOUT of the low dropout linear regulator. In the path 2, the load from the drain of the second-stage common-source amplifier MN11 to the power supply terminal VDD is a diode-connected transistor, the equivalent resistance is small, and the source-to-ground impedance of the second-stage common-source amplifier MN11 is the source-drain resistance of the second-stage common-source amplifier MN11 operating in the saturation region, and the resistance value is large. Therefore, when the power supply is changed, the grid electrode of the power tube MPFET can better follow the change of the power supply voltage, so that the smaller change of the grid source voltage of the power tube is caused, and the power supply inhibition characteristic is improved.
The invention converts the change of the power supply VDD into the current change and superimposes the current change on the drain electrode of the power tube MPFET through the path 1 by adding the compensation capacitor CP. At the same time, the current change converted by the change of the power supply VDD through the path 2 is also superimposed to the drain of the power tube MPFET (i.e., the output terminal of the low dropout linear regulator). In one section of frequency, the output current directions generated by the same power supply change passing through the path 1 and the path 2 are different, so that after the output ends of the linear voltage regulators are overlapped, smaller total output voltage change quantity is generated, and the power supply inhibition characteristic is improved.
The amounts of current change generated in the paths 1 and 2 are analyzed in detail below.
Let the power supply variation of the power supply terminal VDD be Δvd, the current variation of Δvd generated in the path 1 be Δiout1, and the current variation of Δvd generated in the path 2 be Δiout2. Wherein Δiout1 is the difference Δiea_out between the current variation Δi2 above the output end of the first stage error amplifier EA and the current variation Δi1 below the same.
If Δvd is changed in the forward direction, in the path 1, the current change amount of Δvd converted by MP4 and MP2 is Δi2, the current change amount Δi2 is changed in the forward direction from the power supply terminal VDD of the first stage error amplifier EA to the output terminal ea_out of the first stage error amplifier EA, and is changed in the forward direction from the output terminal ea_out to the output terminal VOUT of the linear regulator after passing through the second stage common source amplifier MN11 and the current mirror M1. In the optimized frequency band, Δvdd reaches the output terminal ea_out through the current variation Δi1 generated by MP3, MP1, MN9, MN7, MN10, MN8 to change in the positive direction, and reaches the output terminal VOUT of the linear voltage regulator through the second-stage common-source amplifier MN11 and the current mirror M1 from the output terminal ea_out to change in the negative direction.
If Δvd changes in the forward direction, in the path 2, Δvd passes through the third transistor MP5 and the drain of the second stage common source amplifier MN11, and reaches the gate of the power transistor MPFET in the forward direction, and the amount of change is smaller than Δvd. The source of power tube MPFET is connected to power supply terminal VDD, and the gate-source voltage of power tube MPFET increases, resulting in a forward change of the output current.
The expression of the current Δiout1 as a function of the power supply is:
ΔIEA_out＝ΔI2-ΔI1
where Zout1 is the equivalent output impedance of the first stage error amplifier EA, gmn2 is the transconductance of the second stage common source amplifier MN11, For the impedance of the third transistor MP5, cg is the gate capacitance of the power transistor MPFET, K is the width to length ratio of the power transistor MPFET to the third transistor MP5 in the current mirror M1, cc is the compensation capacitance of the output end of the first stage error amplifier EA, rc is the equivalent series resistance of Cc, CP is the compensation capacitance, gmp2 is the transconductance of MP2, gmbp is the back gate transconductance of MP2, rop2 is the source-drain resistance of MP2, rop4 is the source-drain resistance of MP4, gmn10 is the transconductance of MN10, gmbn is the back gate transconductance of MN10, ron10 is the source-drain resistance of MN10, ron8 is the source-drain resistance of MN8,/>Is the equivalent impedance between the drain electrode of the first current mirror load MP1 and the source electrode of the third current mirror load MP3 or the equivalent impedance between the drain electrode of the second current mirror load MP2 and the source electrode of the fourth current mirror load MP4,/>The Cx is the total capacitance to ground of the gate of the second MOS transistor MN8, which is the equivalent impedance between the source of the first MOS transistor MN7 and the drain of the third MOS transistor MN 9.
The expression of the current Δiout2 as a function of the power supply is:
Where s=jw=j2pi f, f is the frequency, cg is the gate capacitance of the power transistor MPFET, The impedance of the third transistor MP5 is rdsn, which is the equivalent output impedance of the second stage common source amplifier MN11, and K is the width-to-length ratio of the power transistor MPFET to the third transistor MP5 in the current mirror M1.
The formula of the power supply rejection ratio PSR of the whole low dropout linear voltage regulator is as follows:
Zout＝(RF1+RF2)//Rload//(1/SCL)
Where Δvout is an output voltage variation generated by a power supply variation, Δiout is an output current variation generated by a power supply variation, Δiout=Δiout1+Δiout2, zout is a closed loop output impedance of the LDO, RF1 is a resistance value of the first feedback resistor, RF2 is a resistance value of the second feedback resistor, rload is a resistance value of the load resistor, and 1/SCL is an impedance of the load capacitor.
Fig. 2 is a graph of the current Δiout1 as a function of frequency. The abscissa in the figure is the angular frequency and the ordinate is the transconductance Gm. When the frequency is low, gmn is greater than SCx; when the frequency is high, gmn is less than SCx. As can be seen, the transconductance of Δi2 is gx when the frequency is low, becomes larger when the frequency is larger than gx/Cp, and has a slope SCp, and becomes lower in a curve when the frequency is larger than gmn/Cx.
Fig. 3 is a graph of the current Δiout2 as a function of frequency. The abscissa in the figure is the angular frequency and the ordinate is the transconductance Gm. As can be seen from the equation, the transconductance of ΔIout2 is gx at low frequencies and varies at a slope SCg/gmp5 at high frequencies.
Fig. 4 is a graph showing the output impedance Zout of the low dropout linear regulator with frequency. Wc in the figure is the dominant pole of the linear voltage regulator and Wo is the bandwidth of the linear voltage regulator.
Fig. 5 is a graph comparing the simulation results of the compensated capacitor CP and the uncompensated capacitor CP. As can be seen from the graph, in the frequency range of 100 to 100K, the power supply rejection characteristic with the compensation capacitor is obviously better than that without the compensation capacitor, and the power supply rejection characteristic can be reduced by 20db at most in a certain frequency range.
On the basis of keeping the architecture functions of all parts of the existing low-dropout linear voltage regulator, the invention adds a capacitor connected with VDD at the internal node of the error amplifier, adopts NMOS input and PMOS connected with a diode as common source stages of loads to replace a common driving buffer, greatly reduces the number of devices on the basis of ensuring high power supply rejection ratio, and reduces the complexity of the structure.
According to the invention, the compensation capacitor is connected between the power end of the error amplifier and the current mirror load, when the power voltage is changed, the current change direction of the compensation capacitor passage is different from the current change direction generated by the output end of the second-stage common source amplifier, and the current is superposed at the output end to reduce the change amount of the total output voltage, so that the power suppression characteristic of the LDO is improved. Meanwhile, the second-stage common source amplifier adopts an N-type common source amplifier structure, and adopts a diode connection method of a MOS transistor as a load, so that the second-stage common source amplifier has good power supply inhibition characteristic.
The foregoing description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and various modifications can be made to the above-described embodiment of the present invention. All simple, equivalent changes and modifications made in accordance with the claims and the specification of this application fall within the scope of the patent claims. The present invention is not described in detail in the conventional art.
Claims (4)
1. The low-dropout linear voltage regulator with the high power supply rejection ratio is characterized by comprising a first-stage error amplifier, a second-stage common-source amplifier, a current mirror, a feedback loop and an output load, wherein the grid electrode of the second-stage common-source amplifier is connected with the first-stage error amplifier, the drain electrode of the second-stage common-source amplifier is connected with the current mirror, and the source electrode of the second-stage common-source amplifier is grounded; the feedback loop and the output load are connected in parallel and then connected with the current mirror, and a compensation capacitor is arranged in the first-stage error amplifier;
The first-stage error amplifier comprises a first transistor and a second transistor which provide tail current sources, wherein the grid electrode of the first transistor inputs first bias voltage, the drain electrode of the first transistor is connected with the source electrode of the second transistor, and the source electrode of the first transistor is grounded; a gate of the second transistor inputs a second bias voltage;
The first-stage error amplifier further comprises a first input tube, a second input tube, a third input tube and a fourth input tube, wherein the grid electrode of the first input tube inputs reference voltage, the drain electrode of the first input tube is connected with the source electrode of the third input tube, and the source electrode of the first input tube is connected with the drain electrode of the second transistor; the grid electrode of the second input tube inputs feedback voltage, the drain electrode of the second input tube is connected with the source electrode of the fourth input tube, and the source electrode of the second input tube is connected with the drain electrode of the second transistor; the grid electrode of the third input tube inputs a third bias voltage, and the source electrode of the third input tube is connected with the drain electrode of the first input tube; the grid electrode of the fourth input tube inputs a third bias voltage, and the source electrode of the fourth input tube is connected with the drain electrode of the second input tube;
The first-stage error amplifier further comprises a first current mirror load, a second current mirror load, a third current mirror load and a fourth current mirror load, wherein the grid electrode of the first current mirror load is connected with the grid electrode of the second current mirror load, and the source electrode of the first current mirror load is connected with the drain electrode of the third current mirror load; the grid electrode of the second current mirror load is connected with the grid electrode of the first current mirror load, and the source electrode of the second current mirror load is connected with the drain electrode of the fourth current mirror load; the grid electrode of the third current mirror load is connected with the grid electrode of the fourth current mirror load, the drain electrode of the third current mirror load is respectively connected with the source electrode of the first current mirror load and the drain electrode of the third input tube, and the source electrode of the third current mirror load is connected with the power supply end; the grid electrode of the fourth current mirror load is connected with the grid electrode of the third current mirror load, the drain electrode of the fourth current mirror load is respectively connected with the source electrode of the second current mirror load and the drain electrode of the fourth input tube, and the source electrode of the fourth current mirror load is connected with the power supply end; the grid electrode of the first current mirror load and the grid electrode of the second current mirror load input a fourth bias voltage, and the grid electrode of the third current mirror load and the grid electrode of the fourth current mirror load input a fifth bias voltage;
one end of the compensation capacitor is connected with the power supply end, and the other end of the compensation capacitor is connected with the drain electrode of the first current mirror load;
The first-stage error amplifier further comprises a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube, wherein the grid electrode of the first MOS tube is respectively connected with the grid electrode of the second MOS tube and the drain electrode of the third MOS tube, the drain electrode is connected with the source electrode of the third MOS tube, and the source electrode is grounded; the grid electrode of the second MOS tube is connected with the grid electrode of the first MOS tube, the drain electrode of the second MOS tube is connected with the source electrode of the fourth MOS tube, and the source electrode is grounded; the grid electrode of the third MOS tube is connected with the grid electrode of the fourth MOS tube, the drain electrode of the third MOS tube is respectively connected with the drain electrode of the first current mirror load and the grid electrode of the first MOS tube, and the source electrode of the third MOS tube is connected with the drain electrode of the first MOS tube; the grid electrode of the fourth MOS tube is connected with the grid electrode of the third MOS tube, the drain electrode of the fourth MOS tube is connected with the drain electrode of the second current mirror load, and the source electrode of the fourth MOS tube is connected with the drain electrode of the second MOS tube; a grid electrode of the third MOS tube and a grid electrode of the fourth MOS tube are input with a sixth bias voltage;
The drain electrode of the second current mirror load and the drain electrode of the fourth MOS tube are connected with the output end of the first-stage error amplifier, and the output end of the first-stage error amplifier is connected with the grid electrode of the second-stage common source amplifier.
2. The low dropout linear regulator with high supply rejection ratio according to claim 1, wherein the current mirror M1 comprises a third transistor and a power transistor, a gate of the third transistor being connected to a gate of the power transistor and a drain of the second stage common source amplifier, respectively, a drain being connected to a drain of the second stage common source amplifier, and a source being connected to a supply terminal of the first stage error amplifier; the grid electrode of the power tube is connected with the grid electrode of the third transistor, the source electrode of the power tube is connected with the power end of the first-stage error amplifier, the drain electrode of the power tube is connected with the feedback loop and the output load, and the drain electrode of the power tube MPFET is connected with the output end VOUT of the whole low-dropout linear voltage regulator.
3. The low dropout linear regulator having a high power supply rejection ratio according to claim 1, wherein said feedback loop comprises a first feedback resistor and a second feedback resistor in series, a common terminal of said first feedback resistor and said feedback resistor outputting said feedback voltage.
4. The low dropout linear regulator having a high power supply rejection ratio according to claim 1, wherein said output load comprises a load capacitor and a load resistor, said load capacitor and said load resistor being arranged in parallel.
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| CN115454186B (en) * | 2022-09-15 | 2023-05-05 | 芯洲科技(北京)股份有限公司 | Linear voltage regulator for power supply system and power supply system |
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