CN105634508A - Realization method of low complexity performance limit approximate Turbo decoder - Google Patents

Abstract

The invention discloses a realization method of a low complexity performance limit approximate Turbo decoder, mainly solves the problems that a traditional Turbo decoder based on a searching table is high in complexity and a decoder based on a Max-Log-MAP algorithm is poor in performance. The method comprises following steps: demultiplexing input soft information streams; storing in an RAM; selecting data from the RAM by an SISO (soft input soft output) decoder according to decoder station indication signals; iteratively calculating backward measurement, forward measurement and a log-likelihood ratio, wherein a Log-MAP algorithm based on linear approximation is adopted, the same SISO decoder is iteratively multiplexed in front and back stages; reversely accessing an interleaving address unit; and interleaving and de-interleaving external information. According to the method of the invention, through carrying out linear approximation to the Log-MAP algorithm, compared with a traditional approximate scheme, a better error correction performance is obtained; compared with a scheme based on the searching table, the complexity is greatly reduced; and the method is applicable to an LTE system.

Description

A kind of Turbo decoder of low complex degree nearly performance limit realize method

Technical field

The invention belongs to wireless communication field, relate to Error-Control Coding, particularly to low complex degree nearly performance limit Turbo decoder realize method, can be used for LTE and satellite communication system.

Background technology

Error-Control Coding is one of key technology of guarantee information transmitting in wireless communication system. 1948, Shannon proposed famous channel coding theorem, had established the theoretical basis of error-correcting code technique. Since then, scholar and technical staff unremitting effort always, find the encoding scheme approaching channel capacity.

1993, C.Berrou et al. proposed Parallel Concatenated Convolutional Code, i.e. Turbo code, and the channel coding technology for approaching shannon limit opens new road. Substantial amounts of Computer Simulation shows, Turbo code, under the channel circumstance that signal to noise ratio is relatively low, has the error-correcting performance of excellence. Turbo code is widely used in various communication system because of its performance approaching shannon limit. At present, Turbo code has been applied to 3-G (Generation Three mobile communication system), DVB-SH standard physical layer protocol, and by the channel coding schemes of 3GPP tissue positioned LTE standard.

The optimum decoding algorithm of Turbo code is a kind of algorithm based on maximum a posteriori probability, is called for short MAP algorithm, but there is substantial amounts of multiplication and nonlinear operation in algorithm so that hardware is directly realized by hardly possible. Log-MAP algorithm is the mapping at log-domain of the MAP algorithm, the multiplying in MAP algorithm is converted to the additive operation of log-domain and loses performance hardly, although reducing complexity, but the hardware of logarithm operation realizes remaining a difficult problem. Max-Log-MAP algorithm is being similar to Log-MAP algorithm, because it realizes simple, is widely used at engineering field, but emulation shows, Max-Log-MAP algorithm is 10 in bit error rate^-6Time, coding gain have lost 0.4dB than Log-MAP algorithm.

Traditional Turbo decoder implementation based on MAP algorithm is generally all adopt the method that realizes based on look-up table, but the scale of look-up table is exponentially increased along with the increase of decoder internal information bit wide, can increase chip area, affects processing speed simultaneously. Although and implementation complexity based on Max-Log-MAP algorithm is relatively low, have lost performance.

Summary of the invention

The technology of the present invention solves problem: overcome the deficiencies in the prior art, propose a kind of low complex degree nearly performance limit Turbo decoder realize system, the program can obtain the performance of nearly Log-MAP algorithm, and complexity is far below traditional Log-MAP implementation simultaneously.

The technical solution of the present invention is: the Turbo decoder of a kind of low complex degree nearly performance limit realize system, including demultiplexing module, first memory, second memory, the 3rd memorizer, SISO decoder, adder, interleaver, deinterleaver, hard decision device;

The demultiplexing module quantization Soft Inform ation to input decoder, quantization bit wide is L, demultiplex, the Soft Inform ation that quantifies of input decoder includes the bit soft information stream of serial, the first check bit Soft Inform ation stream and the second check bit Soft Inform ation stream, obtain parallel bit soft information stream, the first check bit Soft Inform ation stream and the second check bit Soft Inform ation stream after demultiplexing shunting, be respectively stored in first memory, second memory, the 3rd memorizer;

The prior information of SISO decoder is initialized as zero, and then SISO decoder reads bit soft information and the first check bit Soft Inform ation from first memory, second memory;

While reading bit soft information and the first check bit Soft Inform ation, SISO decoder is according to the bit soft information readWith the first check bit Soft Inform ationDetermine transfering sheetState value, formula is as follows:

SetFor transfering sheet, generalTransfering sheet is mapped on Trellis figure, if on Trellis figure exist one from s to s ' path, thenIt is calculated as follows:

${\widetilde{\mathrm{\γ}}}_k(s,s^{\′})=u_{k}L\left(u_k\right)+c_k^{s}L\left(y_k^s\right)+c_k^{p}L\left(y_k^p\right)$

In formula, u_kThe bit after Soft Inform ation encodes in advance, L (u is quantified for what input_k) for u_kPrior information,WithFor bit soft informationPrior information and the first check bit Soft Inform ationPrior information;

If willBe mapped on Trellis figure for transfering sheet, Trellis figure is absent from from s to s ' path, then

According toCarrying out the iteration of backward tolerance, the initial condition of iteration isThe formula of iteration is as follows:

${\widetilde{\mathrm{\β}}}_k\left(s\right)=\underset{s^{\′}}{max}*\left({\widetilde{\mathrm{\β}}}_{k+1}\right(s^{\′})+{\widetilde{\mathrm{\γ}}}_k(s,s^{\′}\left)\right)$

In formulaRepresent the backward tolerance of current time,Represent the backward tolerance of the subsequent time of current time,Representing transfering sheet, s represents current time SISO decoder state, and s ' represents the subsequent time SISO decoder state of current time.

By the initial condition of iterationSubstitute on the right of iterative formulaNamely by the path read group total on Trellis figure, obtaining binary Jacobi logarithmic function:

Max* (x, y)=ln (e^x+e^y)=max (x, y)+log (1+e^-|x-y|)

Make following linear approximation:

As | x-y | > 2.5 time, max* (x, y)=max (x, y);

When | x-y | < when 2.5, max* (x, y)=max (x, y)-0.25 �� (| x-y |-2.5);

WithWith(x, unknown quantity x and the y in y) carries out linear approximation calculating, and (x y) is backward tolerance to the max* after calculating to replace max*

While reading bit soft information and the first check bit Soft Inform ation, SISO decoder, according to the bit soft information read and the first check bit Soft Inform ation, carries out the iteration of forward metrics, and initial condition is ${\widetilde{\mathrm{\&alpha;}}}_0\left(s\right)=\left\{\begin{array}{cc}0,& s=0\\ -\mathrm{\&infin;},& s\&NotEqual;0\end{array}\right.,$ The formula of iteration is as follows:

${\widetilde{\mathrm{\&alpha;}}}_k\left(s\right)=\underset{s^{\&prime;}}{max}*\left({\widetilde{\mathrm{\&alpha;}}}_{k-1}\right(s^{\&prime;})+{\widetilde{\mathrm{\&gamma;}}}_k(s^{\&prime;},s\left)\right);$

In formula,For the forward metrics of current time,Forward metrics for current time previous moment;

According to after current time to toleranceForward metrics with current time previous momentCalculating log-likelihood ratio, log-likelihood calculations calculates with forward metrics and carries out simultaneously, and log-likelihood calculations formula is as follows

$L\left({\hat{u}}_k\right)=\underset{(s^{\&prime;},s),u_k=1}{max*}\left({\widetilde{\mathrm{\&alpha;}}}_{k-1}\right(s^{\&prime;})+{\widetilde{\mathrm{\&gamma;}}}_{k-1}(s^{\&prime;},s)+{\widetilde{\mathrm{\&beta;}}}_k(s\left)\right)-\underset{(s^{\&prime;},s),u_k=0}{max*}\left({\widetilde{\mathrm{\&alpha;}}}_{k-1}\right(s^{\&prime;})+{\widetilde{\mathrm{\&gamma;}}}_{k-1}(s^{\&prime;},s)+{\widetilde{\mathrm{\&beta;}}}_k(s\left)\right)$

In formula,Represent log-likelihood ratio;

The prior information of SISO decoder, namely the log-likelihood ratio information initial value exported, deduct the log-likelihood ratio of SISO decoder output, obtain bit soft information, namely the input of interleaver and deinterleaver is obtained, deliver to interleaver and deinterleaver respectively, after being interleaved or deinterleaving, new prior information as SISO decoder feeds back to SISO decoder, replace the prior information of original SISO decoder, carry out the interative computation of a new round, until when reaching the maximum iteration time set, output deinterleave after bit soft information to hard decision device, this bit soft information is carried out hard decision by hard decision device, obtain final court verdict.

The Jacobi logarithmic function of described multi input adopts parallel duplex to calculate.

The present invention has the advantage that compared to existing technology

1) present invention adopts the Log-MAP decoding algorithm based on piece wire approximation, than Max-Log-MAP algorithm conventional in engineering, there is better error-correcting performance, approach the performance of Log-MAP algorithm, than the Log-MAP algorithm based on look-up tables'implementation, there is less complexity;

2) the same SISO decoder of former and later two stage multiplexings that the present invention decodes in an iteration, more less than the hardware resource that traditional implementation uses;

3) present invention is accessed by the backward of interleaving address and realizes decoding while SISO decoder receives data, it is not necessary to waits full block of data to be received, reduces decoding latency.

Accompanying drawing explanation

Fig. 1 is the flowchart of the present invention;

The hardware that Fig. 2 is the present invention realizes block diagram;

Fig. 3 is key operation element circuit figure of the present invention;

Fig. 4 is the performance of BER analogous diagram of the present invention;

Fig. 5 is the hardware synthesis resource schematic diagram of the present invention.

Detailed description of the invention

The basic ideas of the present invention are: propose a kind of low complex degree nearly performance limit Turbo decoder realize method, mainly solve traditional Turbo decoder complexity based on look-up table high, based on the problem of the decoder performance difference of Max-Log-MAP algorithm. The method includes: input Soft Inform ation stream is demultiplexed and is stored in RAM; SISO (soft-output coding) decoder selects data according to decoder state indication signal from RAM; SISO decoder iteration calculates backward tolerance, forward metrics and log-likelihood ratio, adopts the Log-MAP algorithm based on linear approximation; The front and back half wheel same SISO decoder of iteration multiplexing; Backward accesses interleaving address unit, external information is interleaved and deinterleaves. The present invention, by Log-MAP algorithm is carried out linear approximation, obtains better error-correcting performance than traditional approximate schemes, greatly reduces complexity than the scheme based on look-up table, can be used for LTE system.

Below in conjunction with the drawings and specific embodiments, the present invention is described in detail

As in figure 2 it is shown, the system enforcement step of the present invention is as follows:

Turbo code for 1/3 code check, input decoder flow of information according to systematic bits, the first check bit, the second check bit order sequentially input, first detect whether valid data input system, when detecting that input data are effective, system utilizes demultiplexing module that the flow of information of input is demultiplexed, three flow of information are obtained after demultiplexing, they are respectively: systematic bits flow of information, the first check bit flow of information and the second check bit flow of information, can by they separate storage after demultiplexing.

System utilizes finite state machine for auxiliary, establishes three states, corresponding to three flow of information, and the flow of information obtained is respectively stored among three memorizeies. Three memorizeies store systematic bits, the first check bit and the second check bit respectively, so carry out independently calling to them.

After data storage terminates, system utilizes SISO decoder to start to decode process. SISO decoder receives the prior information of feedback, system judges that decoder is in first half wheel decoding or later half takes turns decoding, calling system bit and the first check bit or systematic bits and the second check bit from memorizer, sending into SISO decoder to decode, decoder is by the prior information output after calculated posterior information and delay. System, at the same SISO decoder of former and later two stage multiplexings of an iteration, has less complexity than traditional. In calculating in SISO decoder, present invention uses the Log-MAP decoding algorithm of piece wire approximation, decoding performance approaches Log-MAP algorithm, and complexity is substantially reduced.

If last the later half of iteration is taken turns, then the posterior information that SISO decoder exports being sent into deinterleaver, and the output of deinterleaver is sent into hard decision device, the Bit data of hard decision output is exactly code word, and decoding terminates.

Later half if not last iteration is taken turns, and adder receives the posterior information of SISO decoder output and the prior information of delay, deducts the prior information of delay in adder by posterior information.

System judges that SISO decoder is in first half wheel iteration or later half takes turns iteration, data adder exported send into interleaver or deinterleaver, interleaver or the output of deinterleaver are exactly new prior information, and it feeds back to SISO decoder, continue iterative process.

Below by drawings and Examples, technological system and method to the present invention are further described.

With reference to Fig. 1, the step that implements of the present invention includes:

Step 1: decoder has detected when data input, is initialized as 0 by decoder state indication signal, and the Soft Inform ation of input decoder is demultiplexed. For the Turbo code of 1/3 code check 4 code length, if former codeword sequence is that { 1,0,1,1}, then the first check bit after coding is that { 1,0,1,1}, the second check bit is that { 1,1,0,1}, use QPSK modulation, through Gaussian white noise channel, bit signal to noise ratio is 2dB. System receive data quantization bit wide be 4 bits, wherein 2 bit decimal places, 2 bit integer positions. The systematic bits receiving code word is { { 0,1,1,1}, { 0,0,1,0}, { 0,1,1,1}, { 0,1,1,1}}, the first check bit is { { 0,1,1,1}, { 1,0,0,0}, { 0,1,1,1}, { 0,1,0,1}}, the second check bit is { { 0,1,1,1}, { 1,1,0,0}, { 1,0,1,1}, and 0,1,1,1}}, wherein input the flow of information of decoder according to systematic bits, the first check bit, the second check bit order sequentially input. System utilizes the auxiliary of finite state machine, and whole systematic bits information are write same RAM, and two groups of check bit information are respectively written into two RAM. Bit information is converted into fraction data, then system data be 1.75,0.5,1.75,1.75}, and the first check bit be 1.75 ,-1 ,-1.25,1.75}, the second check bit 1.75 ,-2,1.75,1.25}.

Step 2: after data write, the prior information of SISO decoder being initialized as zero, produces data simultaneously and effectively indicate, SISO decoder detects that data effectively indicate, and be that 0 judgement decoder is currently at first half and takes turns iteration according to decoder state signal, system information { 1.75,0.5,1.75 is read from RAM, 1.75} and the first check information { 1.75,-1 ,-1.25,1.75}.

Step 3:SISO decoder utilizes prior information and the information read from RAM to carry out the calculating of backward tolerance, and the calculating of backward tolerance carries out from back to front. First, backward tolerance is initializedN=4 in the present embodiment, the minima of initial backward tolerance is limited in more than-10 in realizing by the hardware of the present invention by decoder, then rightBe initialized as $\{{\widetilde{\mathrm{\&beta;}}}_4\left(0\right)=0,{\widetilde{\mathrm{\&beta;}}}_4\left(1\right)=-10,{\widetilde{\mathrm{\&beta;}}}_4\left(2\right)=-10,{\widetilde{\mathrm{\&beta;}}}_4\left(3\right)=-10,{\widetilde{\mathrm{\&beta;}}}_4\left(4\right)=-10,{\widetilde{\mathrm{\&beta;}}}_4\left(5\right)=-10,{\widetilde{\mathrm{\&beta;}}}_4\left(6\right)=-10,{\widetilde{\mathrm{\&beta;}}}_4\left(7\right)=-10\},$ Then according to following formula carries out iteration from back to front

${\widetilde{\mathrm{\&beta;}}}_k\left(s\right)=\underset{s^{\&prime;}}{max*}\left({\widetilde{\mathrm{\&beta;}}}_{k+1}\right(s^{\&prime;})+{\widetilde{\mathrm{\&gamma;}}}_k(s,s^{\&prime;}\left)\right)$

Wherein,For transfering sheet, if exist on Trellis figure one from s to s ' path, thenIt is calculated as follows

${\widetilde{\mathrm{\&gamma;}}}_k(s,s^{\&prime;})=u_{k}L\left(u_k\right)+c_k^{s}L\left(y_k^s\right)+c_k^{p}L\left(y_k^p\right)$

In the present embodiment, u_kFor the bit that encoder (encoder is the encoder of decoder of the corresponding present invention, and the present invention is the decoding that the concrete form that this encoder is encoded carries out correspondence) inputs, u_k=0,1} correspond in a decoder-1,1}, L (u_k) for u_kPrior information, first time iteration first half take turns in { L (u₁), L (u₂), L (u₃), L (u₄) be 0,0,0,0},The systematic bits exported for encoder in this transfer and check bit, in a decoder corresponding to 0 input of 0 state encoderWithFor-1 and-1, corresponding to 1 input of 0 state encoderWithIt is 1 and 1, corresponding to 0 input of 1 state encoderWithFor-1 and 1, corresponding to 1 input of 1 state encoderWithIt is 1 and-1 ..., corresponding to 0 input of 7 state encoderWithFor-1 and-1, corresponding to 1 input of 7 state encoderWithIt is 1 and 1,WithFor the Soft Inform ation about systematic bits and check bit, in first time iteration first half wheel in the present embodimentFor 1.75,1.75,0.5 ,-1,1.75 ,-1.25,1.75,1.75}, if Trellis figure is absent from from s to s ' path, thenIn base-2 algorithm, corresponding two the purpose states of each source state, the input of corresponding encoder is 0 and 1 respectively, therefore have only to calculate two transfers, in the present embodiment, the quantization bit wide to transfering sheet, backward tolerance, forward metrics and posterior information is 11, wherein decimal place 3 is, integer-bit 8, then calculate $\{{\widetilde{\mathrm{\&gamma;}}}_3(0,0),{\widetilde{\mathrm{\&gamma;}}}_3(0,4)\}=\{-3.5,3.5\},$ $\{{\widetilde{\mathrm{\&gamma;}}}_3(1,4),{\widetilde{\mathrm{\&gamma;}}}_3(1,0)\}=\{0,0\},......,\{{\widetilde{\mathrm{\&gamma;}}}_3(7,3),{\widetilde{\mathrm{\&gamma;}}}_3(7,7)\}=\{-3.5,3.5\},......,$ Transfering sheet is substituted into backward iterative computation formula, then

$\begin{array}{c}{\widetilde{\mathrm{\&beta;}}}_3\left(0\right)=max*\left({\widetilde{\mathrm{\&beta;}}}_4\right(0)+{\widetilde{\mathrm{\&gamma;}}}_3(0,0),{\widetilde{\mathrm{\&beta;}}}_4(4)+{\widetilde{\mathrm{\&gamma;}}}_3(0,4\left)\right),\\ {\widetilde{\mathrm{\&beta;}}}_3\left(1\right)=max*\left({\widetilde{\mathrm{\&beta;}}}_4\right(3)+{\widetilde{\mathrm{\&gamma;}}}_3(1,3),{\widetilde{\mathrm{\&beta;}}}_4(2)+{\widetilde{\mathrm{\&gamma;}}}_3(1,2\left)\right),\\ {\widetilde{\mathrm{\&beta;}}}_3\left(7\right)=max*\left({\widetilde{\mathrm{\&beta;}}}_4\right(3)+{\widetilde{\mathrm{\&gamma;}}}_3(7,3),{\widetilde{\mathrm{\&beta;}}}_4(7)+{\widetilde{\mathrm{\&gamma;}}}_3(7,7\left)\right).\end{array}$ (x, y) for binary Jacobi logarithmic function for max*

Max* (x, y)=ln (e^x+e^y)=max (x, y)+log (1+e^-|x-y|)

Calculating available segment linear approximation method to above formula, approximate regulation is as follows:

As | x-y | > 2.5 time, max* (x, y)=max (x, y);

When | x-y | < when 2.5, max* (x, y)=max (x, y)-0.25 �� (| x-y |-2.5);

The arithmetic element circuit of binary Jacobi logarithmic function is as it is shown on figure 3, wherein $\begin{array}{c}{\widetilde{\mathrm{\&alpha;}}}_{k-1}\left(s^{\&prime;}\right)\\ {\widetilde{\mathrm{\&gamma;}}}_k(s^{\&prime;},s)\end{array}$ Represent forward metrics value and the branch metric in k moment (transfering sheet) value in first group of k-1 moment respectively, $\begin{array}{c}{\widetilde{\mathrm{\&alpha;}}}_{k-1}\left(s^{\&prime;\&prime;}\right)\\ {\widetilde{\mathrm{\&gamma;}}}_k(s^{\&prime;\&prime;},s)\end{array}$ Represent forward metrics value and the branch metric in k moment (transfering sheet) value in second group of k-1 moment respectively.

First two adders of left end receive forward metrics value and the branch metric in k moment (transfering sheet) value in two groups of k-1 moment simultaneously, they are done additive operation, just obtain parameter x, y in Jacobi logarithmic function linear approximation, the output of two adders of left end is respectively fed to comparator and next stage adder. Its two inputs are done subtraction by next stage adder, result is sent into the module that takes absolute value, after taking absolute value, result is sent into adder below, adder below completes to subtract 2.5 (be more than or equal to) operation, then output is sent in shift unit. Its two inputs are compared by comparator, if difference is more than 2.5, then figure breaker in middle disconnects, and comparator selects the higher value in its input to pass to the adder of right-hand member, and the adder of right-hand member exports after subtracting 0 to comparator output; If difference is less than 2.5, then figure breaker in middle Guan Bi, what the higher value of comparator input terminal and shift unit are exported negates feeding right-hand member adder, and result is exported by right-hand member adder. The output of right-hand member adder is exactly the linear approximation of Binary logistic function.

2 are completed in each clock^mThe backward tolerance of individual state updates, and m is encoder mnemon number. In order to prevent the accumulation of state measurement in iterative process, it is necessary to state measurement is normalized by following formula

Then after normalizationSo that 0,3.5 ,-3 ,-6 ,-6 ,-3 ,-6, and-3}, obtainAfter just can continue recursion, calculate all of backward metric. The backward tolerance that each moment calculates is stored in RAM, for the calculating of follow-up log-likelihood ratio.

Step 4: after backward metric calculation completes, carries out the calculating of forward metrics, and the calculating of forward metrics carries out from front to back. First, forward metrics is initializedN=4 in the present embodiment, the minima that initial forward is measured is limited in more than-10 in realizing by the hardware of the present invention by decoder, then rightBe initialized as $\{{\widetilde{\mathrm{\&alpha;}}}_0\left(0\right)=0,{\widetilde{\mathrm{\&alpha;}}}_0\left(1\right)=-10,{\widetilde{\mathrm{\&alpha;}}}_0\left(2\right)=-10,{\widetilde{\mathrm{\&alpha;}}}_0\left(3\right)=-10,{\widetilde{\mathrm{\&alpha;}}}_0\left(4\right)=-10,{\widetilde{\mathrm{\&alpha;}}}_0\left(5\right)=-10,{\widetilde{\mathrm{\&alpha;}}}_0\left(6\right)=-10,{\widetilde{\mathrm{\&alpha;}}}_0\left(7\right)=-10\},$ The calculating of transfering sheet is identical with step 3, to each purpose state s, there are two source states and have path between s on Trellis figure. Transfering sheet is substituted into forward direction iterative computation formula:

${\widetilde{\mathrm{\&alpha;}}}_k\left(s\right)=\underset{s^{\&prime;}}{max}*\left({\widetilde{\mathrm{\&alpha;}}}_{k-1}\right(s^{\&prime;})+{\widetilde{\mathrm{\&gamma;}}}_k(s^{\&prime;}.s\left)\right)$

Equally, it is necessary to forward metrics is normalized

Then after normalizationSo that 0 ,-3 ,-3 ,-6.5,7 ,-6.5 ,-6.5, and-3}, obtainJust can continuing recursion, obtain each forward metrics value, the calculating of forward metrics is Tong Bu with the calculating of log-likelihood ratio, therefore without storing.

Step 5: utilize the rear forward metrics calculated to tolerance and step 4 that step 3 calculates to calculate about the log-likelihood ratio sending bit

$L\left({\hat{u}}_k\right)=\underset{(s^{\&prime;},s),u_k=1}{max*}\left({\widetilde{\mathrm{\&alpha;}}}_{k-1}\right(s^{\&prime;})+{\widetilde{\mathrm{\&gamma;}}}_{k-1}(s^{\&prime;},s)+{\widetilde{\mathrm{\&beta;}}}_k(s\left)\right)-\underset{(s^{\&prime;},s),u_k=0}{max*}\left({\widetilde{\mathrm{\&alpha;}}}_{k-1}\right(s^{\&prime;})+{\widetilde{\mathrm{\&gamma;}}}_{k-1}(s^{\&prime;},s)+{\widetilde{\mathrm{\&beta;}}}_k(s\left)\right)$

In the present embodiment,

$L\left({\hat{u}}_1\right)=\underset{(s^{\&prime;},s),u_k=1}{max*}\left({\widetilde{\mathrm{\&alpha;}}}_0\right(s^{\&prime;})+{\widetilde{\mathrm{\&gamma;}}}_0(s^{\&prime;},s)+{\widetilde{\mathrm{\&beta;}}}_1(s\left)\right)-\underset{(s^{\&prime;},s),u_k=0}{max*}\left({\widetilde{\mathrm{\&alpha;}}}_0\right(s^{\&prime;})+{\widetilde{\mathrm{\&gamma;}}}_0(s^{\&prime;},s)+{\widetilde{\mathrm{\&beta;}}}_1(s\left)\right)$

Corresponding forward metrics, backward tolerance and the tolerance divided are substituted into above formula, it is possible to obtain $\underset{(s^{\&prime;},s),u_k=0}{max*}\left({\widetilde{\mathrm{\&alpha;}}}_0\right(s^{\&prime;})+{\widetilde{\mathrm{\&gamma;}}}_0(s^{\&prime;},s)+{\widetilde{\mathrm{\&beta;}}}_1(s\left)\right)$ For $\underset{(s^{\&prime;},s),u_k=1}{max*}\left({\widetilde{\mathrm{\&alpha;}}}_0\right(0)+{\widetilde{\mathrm{\&gamma;}}}_0(0,0)+{\widetilde{\mathrm{\&beta;}}}_1(0),{\widetilde{\mathrm{\&alpha;}}}_0(1)+{\widetilde{\mathrm{\&gamma;}}}_0(1,4)+{\widetilde{\mathrm{\&beta;}}}_1(4),......,{\widetilde{\mathrm{\&alpha;}}}_0(7)+{\widetilde{\mathrm{\&gamma;}}}_0(7,3)+{\widetilde{\mathrm{\&beta;}}}_1(3\left)\right),$ $\underset{(s^{\&prime;},s),u_k=1}{max*}\left({\widetilde{\mathrm{\&alpha;}}}_0\right(s^{\&prime;})+{\widetilde{\mathrm{\&gamma;}}}_0(s^{\&prime;},s)+{\widetilde{\mathrm{\&beta;}}}_1(s\left)\right)$ For $\underset{(s^{\&prime;},s),u_k=1}{max*}\left({\widetilde{\mathrm{\&alpha;}}}_0\right(0)+{\widetilde{\mathrm{\&gamma;}}}_0(0,4)+{\widetilde{\mathrm{\&beta;}}}_1(4),{\widetilde{\mathrm{\&alpha;}}}_0(1)+{\widetilde{\mathrm{\&gamma;}}}_0(1,0)+{\widetilde{\mathrm{\&beta;}}}_1(0),......,{\widetilde{\mathrm{\&alpha;}}}_0(7)+{\widetilde{\mathrm{\&gamma;}}}_0(7,7)+{\widetilde{\mathrm{\&beta;}}}_1(7\left)\right).$

U on corresponding Trellis figure_kThe transfer of=1, one has 2^mBar shifts, max*{x_iIt is polynary Jacobi logarithmic function, it is possible to 2^m-1 binary Jacobi logarithmic function carries out the interative computation of equivalence, m=3 in the present embodiment, has

max*(x₁,x₂,x₃,x₄,x₅,x₆,x₇,x₈)=max* (max* (x₁,x₂),max*(x₃,x₄),max*(x₅,x₆),max*(x₇,x₈))

Can be calculated $\underset{(s^{\&prime;},s),u_k=1}{max*}\left({\widetilde{\mathrm{\&alpha;}}}_0\right(s^{\&prime;})+{\widetilde{\mathrm{\&gamma;}}}_0(s^{\&prime;},s)+{\widetilde{\mathrm{\&beta;}}}_1(s\left)\right)$ It is 6.

U on corresponding Trellis figure_kThe transfer of=0, computational methods ibid, thenFor-3.5, thenIt is 9.5. In like manner can calculate WithRespectively-4,6.5 and 4.5. for Jacobi logarithmic function carry out equivalence interative computation, this method adopts parallel and pipeline structure, have employed parallel and pipeline structure, max* unit at different levels can simultaneously concurrent operation, it is ensured that decoder can export a log-likelihood ratio sending bit in each clock.

Step 6: deduct prior information from the log-likelihood ratio of SISO decoder output, take turns prior information due to the first half of first time iteration and be initialized as 0, so the result after subtracting each other is { 9.5,-4,6.5,4.5}, subtract each other the feeding interleaver of rear result, meanwhile, decoder state indication signal switches to 1, and instruction decoder entrance is later half takes turns iteration. The output of interleaver sends into SISO decoder as new prior information, it is contemplated that SISO decoder first calculates backward tolerance, and the memory element of interleaver is conducted interviews by interleaving address backward, and the output of such interleaver reversed according to the coding moment. When SISO decoder detects new information input, judge to be currently at later half to take turns iteration according to condition indicative signal, reading the second check bit information from RAM, systematic bits information assignment is 0 (this partial information is already contained in prior information).

Step 7: repeat step 3 to step 5, completes later half to take turns iteration;

Step 8: deduct prior information from the log-likelihood ratio of SISO decoder output, sends into deinterleaver, and meanwhile, decoder state indication signal switches to 0. So far, once complete iterative process completes. The output of deinterleaver sends into SISO decoder as the prior information of next iteration, equally, the memory element of deinterleaver is conducted interviews by interleaving address backward. When SISO decoder detects new information input, judge to be currently at first half wheel iteration according to condition indicative signal, from RAM, read systematic bits information and the first check bit information, start new round iteration.

Step 9: repeat step 3 to step 8, be iterated decoding.

Step 10: when iterations reaches the maximum iteration time set, after completing last half wheel iteration, the output of SISO decoder is sent directly into deinterleaver (without deducting prior information), the output of deinterleaver is sent into decision device and is carried out hard decision, and namely output court verdict decodes result.

With reference to Fig. 1, the step that implements of the present invention includes:

Step 1: decoder has detected when data input, is initialized as 0 by decoder state indication signal, and the Soft Inform ation of input decoder is demultiplexed. Turbo code for 1/3 code check, input decoder flow of information according to systematic bits, the first check bit, the second check bit order sequentially input, utilize the auxiliary of finite state machine, whole systematic bits information are write same RAM, and two groups of check bit information are respectively written into two RAM.

Step 2: after data write, the prior information of SISO decoder is initialized as zero, produce data effectively to indicate simultaneously, SISO decoder detects that data effectively indicate, and be that 0 judgement decoder is currently at first half and takes turns iteration according to decoder state signal, from RAM, read systematic bits information and the first check bit information.

Step 3:SISO decoder utilizes prior information and the information read from RAM to carry out the calculating of backward tolerance, and the calculating of backward tolerance carries out from back to front. First, backward tolerance is initializedThen according to following formula carries out iteration from back to front

${\widetilde{\mathrm{\&beta;}}}_k\left(s\right)=\underset{s^{\&prime;}}{max*}\left({\widetilde{\mathrm{\&beta;}}}_{k+1}\right(s^{\&prime;})+{\widetilde{\mathrm{\&gamma;}}}_k(s,s^{\&prime;}\left)\right)$

Wherein,For transfering sheet, if exist on Trellis figure one from s to s ' path, thenIt is calculated as follows

${\widetilde{\mathrm{\&gamma;}}}_k(s,s^{\&prime;})=u_{k}L\left(u_k\right)+c_k^{s}L\left(y_k^s\right)+c_k^{p}L\left(y_k^p\right)$

u_kFor the bit of encoder input, L (u_k) for u_kPrior information,The systematic bits exported for encoder in this transfer and check bit,WithFor the Soft Inform ation about systematic bits and check bit, if Trellis figure is absent from from s to s ' path, thenIn base-2 algorithm, corresponding two the purpose states of each source state, the input of corresponding encoder is 0 and 1 respectively, therefore has only to calculate two transfers. (x, y) for binary Jacobi logarithmic function for max*

Max* (x, y)=ln (e^x+e^y)=max (x, y)+log (1+e^-|x-y|)

Calculating available segment linear approximation method to above formula, approximate regulation is as follows:

As | x-y | > 2.5 time, max* (x, y)=max (x, y);

When | x-y | < when 2.5, max* (x, y)=max (x, y)-0.25 �� (| x-y |-2.5);

The arithmetic element circuit of binary Jacobi logarithmic function is as shown in Figure 3. 2 are completed in each clock^mThe backward tolerance of individual state updates, and m is encoder mnemon number. In order to prevent the accumulation of state measurement in iterative process, it is necessary to state measurement is normalized by following formula

The backward tolerance that each moment calculates is stored in RAM, for the calculating of follow-up log-likelihood ratio.

Step 4: after backward metric calculation completes, carries out the calculating of forward metrics, and the calculating of forward metrics carries out from front to back. First, forward metrics is initializedThen it is iterated from front to back by following formula

${\widetilde{\mathrm{\&alpha;}}}_k\left(s\right)=\underset{s^{\&prime;}}{max}*\left({\widetilde{\mathrm{\&alpha;}}}_{k-1}\right(s^{\&prime;})+{\widetilde{\mathrm{\&gamma;}}}_k(s^{\&prime;},s\left)\right)$

The calculating of transfering sheet is identical with step 3, to each purpose state s, there are two source states and have path between s on Trellis figure. Equally, it is necessary to forward metrics is normalized

The calculating of forward metrics is Tong Bu with the calculating of log-likelihood ratio, therefore without storing.

Step 5: utilize the rear forward metrics calculated to tolerance and step 4 that step 3 calculates to calculate about the log-likelihood ratio sending bit

$L\left({\hat{u}}_k\right)=\underset{(s^{\&prime;},s),u_k=1}{max*}\left({\widetilde{\mathrm{\&alpha;}}}_{k-1}\right(s^{\&prime;})+{\widetilde{\mathrm{\&gamma;}}}_k(s^{\&prime;},s)+{\widetilde{\mathrm{\&beta;}}}_k(s\left)\right)-\underset{(s^{\&prime;},s),u_k=0}{max*}\left({\widetilde{\mathrm{\&alpha;}}}_{k-1}\right(s^{\&prime;})+{\widetilde{\mathrm{\&gamma;}}}_k(s^{\&prime;},s)+{\widetilde{\mathrm{\&beta;}}}_k(s\left)\right)$

U on Section 1 correspondence Trellis figure on the right of above formula_kThe transfer of=1, one has 2^mBar shifts, max*{x_iIt is polynary Jacobi logarithmic function, it is possible to 2^m-1 binary Jacobi logarithmic function carries out the interative computation of equivalence, adopts parallel and pipeline structure, for m=2, have in this method

max*(x₁,x₂,x₃,x₄)=max* (max* (x₁,x₂),max*(x₃,x₄))

U on Section 2 correspondence Trellis figure on the right of above formula_kThe transfer of=0, computational methods are ibid. Owing to have employed parallel and pipeline structure, max* unit at different levels can simultaneously concurrent operation, it is ensured that decoder can export a log-likelihood ratio sending bit in each clock.

Step 6: deduct prior information from the log-likelihood ratio of SISO decoder output, sends into interleaver, and meanwhile, decoder state indication signal switches to 1, and instruction decoder entrance is later half takes turns iteration. The output of interleaver sends into SISO decoder as new prior information, it is contemplated that SISO decoder first calculates backward tolerance, and the memory element of interleaver is conducted interviews by interleaving address backward, and the output of such interleaver reversed according to the coding moment. When SISO decoder detects new information input, judge to be currently at later half to take turns iteration according to condition indicative signal, reading the second check bit information from RAM, systematic bits information assignment is 0 (this partial information is already contained in prior information).

Step 7: repeat step 3 to step 5, completes later half to take turns iteration;

Step 8: deduct prior information from the log-likelihood ratio of SISO decoder output, sends into deinterleaver, and meanwhile, decoder state indication signal switches to 0. So far, once complete iterative process completes. The output of deinterleaver sends into SISO decoder as the prior information of next iteration, equally, the memory element of deinterleaver is conducted interviews by interleaving address backward. When SISO decoder detects new information input, judge to be currently at first half wheel iteration according to condition indicative signal, from RAM, read systematic bits information and the first check bit information, start new round iteration.

Step 9: repeat step 3 to step 8, be iterated decoding.

Step 10: when iterations reaches the maximum iteration time set, after completing last half wheel iteration, the output of SISO decoder is sent directly into deinterleaver (without deducting prior information), the output of deinterleaver is sent into hard decision device and is carried out hard decision, and namely output court verdict decodes result.

The effect of the present invention can be further illustrated by following simulation result:

1. simulated conditions

Adopting the Turbo code of LTE standard, code block length K=3520, code check is 1/3, iteration 10 times.

2. emulation content and result

With adopting Max-Log-MAP algorithm and the bit error rate based on the Log-MAP algorithm arrangement of look-up table, the present invention is carried out simulation comparison, and simulation result is as shown in Figure 4. As shown in Figure 4, when bit error rate is 10^-6Time, the present invention improves 0.4dB than the scheme performance adopting Max-Log-MAP algorithm, approaches the performance adopting Log-MAP algorithm arrangement.

Fig. 5 is present invention synthesis result on Xilinxx5vsx95t-2ff1136 chip. As shown in Figure 5, the present invention saves the resource of nearly half than traditional scheme, increase only the LUT resource of a times than mutually isostructural Max-Log-MAP scheme, namely achieves the nearly performance limit of low complex degree.

The content not being described in detail in the present invention belongs to techniques known.

Claims (3)

1. the Turbo decoder of the nearly performance limit of a low complex degree realize system, it is characterised in that including: demultiplexing module, first memory, second memory, the 3rd memorizer, SISO decoder, adder, interleaver, deinterleaver, hard decision device;

The demultiplexing module quantization Soft Inform ation to input decoder, quantization bit wide is L, demultiplex, the Soft Inform ation that quantifies of input decoder includes the bit soft information stream of serial, the first check bit Soft Inform ation stream and the second check bit Soft Inform ation stream, obtain parallel bit soft information stream, the first check bit Soft Inform ation stream and the second check bit Soft Inform ation stream after demultiplexing shunting, be respectively stored in first memory, second memory, the 3rd memorizer;

The prior information of SISO decoder is initialized as zero, and then SISO decoder reads bit soft information and the first check bit Soft Inform ation from first memory, second memory;

While reading bit soft information and the first check bit Soft Inform ation, SISO decoder is according to the bit soft information readWith the first check bit Soft Inform ationDetermine transfering sheetState value, formula is as follows:

SetFor transfering sheet, if exist on Trellis figure one from s to s ' path, thenIt is calculated as follows:

${\widetilde{\mathrm{\&gamma;}}}_k(s,s^{\&prime;})=u_{k}L\left(u_k\right)+c_k^{s}L\left(y_k^s\right)+c_k^{p}L\left(y_k^p\right)$

In formula, u_kThe bit after Soft Inform ation encodes in advance, L (u is quantified for what input_k) for u_kPrior information,WithFor bit soft informationPrior information and the first check bit Soft Inform ationPrior information;

If Trellis figure is absent from from s to s ' path, then

According toCarrying out the iteration of backward tolerance, the initial condition of iteration isThe formula of iteration is as follows:

${\widetilde{\mathrm{\&beta;}}}_k\left(s\right)=\underset{s^{\&prime;}}{max}*\left({\widetilde{\mathrm{\&beta;}}}_{k+1}\right(s^{\&prime;})+{\widetilde{\mathrm{\&gamma;}}}_k(s,s^{\&prime;}\left)\right)$

In formulaRepresent the backward tolerance of current time,Represent the backward tolerance of the subsequent time of current time,Representing transfering sheet, s represents current time SISO decoder state, and s ' represents the subsequent time SISO decoder state of current time;

By the initial condition of iterationSubstitute on the right of iterative formulaNamely by the path read group total on Trellis figure, obtaining binary Jacobi logarithmic function:

Max* (x, y)=ln (e^x+e^y)=max (x, y)+log (1+e^-|x-y|)

Make following linear approximation:

As | x-y | > 2.5 time, max* (x, y)=max (x, y);

When | x-y | < when 2.5, max* (x, y)=max (x, y)-0.25 �� (| x-y |-2.5);

WithWith(x, unknown quantity x and the y in y) carries out linear approximation calculating, and (x y) is backward tolerance to the max* after calculating to replace max*

While reading bit soft information and the first check bit Soft Inform ation, SISO decoder, according to the bit soft information read and the first check bit Soft Inform ation, carries out the iteration of forward metrics, and initial condition is ${\widetilde{\mathrm{\&alpha;}}}_0\left(s\right)=\left\{\begin{array}{cc}0,& s=0\\ -\mathrm{\&infin;},& s\&NotEqual;0\end{array}\right.,$ The formula of iteration is as follows:

${\widetilde{\mathrm{\&alpha;}}}_k\left(s\right)=\underset{s^{\&prime;}}{max}*\left({\widetilde{\mathrm{\&alpha;}}}_{k-1}\right(s^{\&prime;})+{\widetilde{\mathrm{\&gamma;}}}_k(s^{\&prime;},s\left)\right);$

In formula,For the forward metrics of current time,Forward metrics for current time previous moment;

According to after current time to toleranceForward metrics with current time previous momentCalculating log-likelihood ratio, log-likelihood calculations calculates with forward metrics and carries out simultaneously, and log-likelihood calculations formula is as follows

$L\left({\hat{u}}_k\right)=\underset{(s^{\&prime;},s),u_k=1}{max}*\left({\widetilde{\mathrm{\&alpha;}}}_{k-1}\right(s^{\&prime;})+{\widetilde{\mathrm{\&gamma;}}}_{k-1}(s^{\&prime;},s)+{\widetilde{\mathrm{\&beta;}}}_k(s\left)\right)-\underset{(s^{\&prime;},s),u_k=0}{max}*\left({\widetilde{\mathrm{\&alpha;}}}_{k-1}\right(s^{\&prime;})+{\widetilde{\mathrm{\&gamma;}}}_{k-1}(s^{\&prime;},s)+{\widetilde{\mathrm{\&beta;}}}_k(s\left)\right)$

In formula,Represent log-likelihood ratio;

The prior information of SISO decoder, namely the log-likelihood ratio information initial value exported, deduct the log-likelihood ratio of SISO decoder output, obtain bit soft information, namely the input of interleaver and deinterleaver is obtained, deliver to interleaver and deinterleaver respectively, after being interleaved or deinterleaving, new prior information as SISO decoder feeds back to SISO decoder, replace the prior information of original SISO decoder, carry out the interative computation of a new round, until when reaching the maximum iteration time set, output deinterleave after bit soft information to hard decision device, this bit soft information is carried out hard decision by hard decision device, obtain final court verdict.

2. the Turbo decoder of a kind of low complex degree according to claim 1 nearly performance limit realize system, it is characterised in that: from the 3rd memorizer, read the second check bit Soft Inform ation, replace the first check bit Soft Inform ation.

3. the Turbo decoder of a kind of low complex degree according to claim 1 nearly performance limit realize system, it is characterised in that: the Jacobi logarithmic function of described multi input adopts parallel duplex to calculate.