CN113114278B - Duobinary Turbo decoding implementation method, system, equipment and application - Google Patents
Duobinary Turbo decoding implementation method, system, equipment and application Download PDFInfo
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Abstract
The invention belongs to the technical field of communication, and discloses a duobinary Turbo decoding implementation method, a duobinary Turbo decoding implementation system, duobinary Turbo decoding implementation equipment and application, wherein the duobinary Turbo decoding implementation system comprises the following steps: the device comprises a sub decoder module DEC, a top layer control module, a cycle state calculation module, a data cache module, an interleaving module, a de-interleaving module, a hard decision module and an output module. The circuit structure of the whole decoder module is improved, and the circuit structure of the whole decoder module is reasonably arranged, so that the whole decoding process can be completed by the whole circuit only by using one sub decoder module, a large amount of hardware resources are saved, hardware resource consumption is reduced, and cost is reduced; by adopting the new method for acquiring the circulation state, the circulation state can be stably acquired under the condition of lower time delay and hardware complexity, and the delay of the decoding process is reduced. Meanwhile, in the top-level control module of the decoder, the whole decoding process can be controlled only through iteration times without increasing extra circuit consumption.
Description
Technical Field
The invention belongs to the technical field of communication, and particularly relates to a duo-binary Turbo decoding implementation method, a duo-binary Turbo decoding implementation system, duo-binary Turbo decoding equipment and application.
Background
At present, along with the rapid development of modern science and technology, information is visible everywhere in daily life of people, and meanwhile, the information transmission is extremely important. Modern communications are developed towards broadband, digitalization and mobility, and information dissemination into ISDN, ADSL, GSM, CDMA and wireless multimedia technologies is constantly updated, but the most basic requirement of a communication system is to be able to transmit information reliably and quickly. Shannon first stated the channel coding theorem in 1948 and indicated that communication with arbitrarily small error probability can be achieved with channel coding. In modern communications, therefore, the quality of the communication is directly affected by the quality of the channel coding technique. In 1993, berrou et al proposed a Turbo code, the performance of which approaches the shannon channel capacity limit; the channel coding technique then enters a completely new phase. Currently, turbo codes are regarded as the most great technical achievement obtained from the research of information and coding theory 23428since the advent of trellis coded modulation technology, and are a milestone in the research of information and coding theory.
Turbo code is also called as parallel concatenated convolutional code, and its coding actually uses short code to construct pseudo-random code, and adopts iterative decoding idea based on soft input and soft output at receiving end, so that it fully utilizes the advantages of concatenated code, and can approximately implement random coding, and can change short code into long code. In practical applications, turbo codes have not achieved major breakthroughs in practice for some time due to the complexity and latency of their implementation. Through the development of more than ten years, the Turbo code station is a mainstream stage and has great diversity in the communication field. In the field of deep space communication, turbo codes are used as coding standards for deep space remote sensing Data by the council for spatial Data standards consultation (CCSDS). In the field of mobile communication, turbo codes have been used as channel coding standards for transmitting high-speed data in third generation mobile communication systems. In addition, in view of the code division multiple access system,
WCDMA, CDMA-2000 and TD-SCDMA all adopt Turbo codes in channel coding.
Bcorrou proposed duo binary Turbo codes in 1996 on the basis of Tubro codes, namely component codes used in Turbo codes adopt RSC with a basic code rate of 2/3. Compared with the common binary Turbo code, the duobinary Turbo code has the following advantages:
(1) The code rate of the component code is 2/3, and the coding efficiency is improved.
(2) The interleaving length is reduced, and the decoding delay is reduced.
(3) The impact of puncturing on decoding performance is reduced.
(4) On the premise of the same complexity, the performance of the duobinary Turbo code is better.
Due to the excellent performance of the duobinary Turbo code, the duobinary Turbo code is widely applied, such as WiMAX and DVB-RCS.
Referring to Turbo decoding method for OFDM power line communication system, the overall architecture of the duo-binary Turbo decoding method is shown in FIG. 5, and includes two sub-decodersDEC1 and DEC2, two sub-decoders perform serial iterative decoding. The sub-decoder DEC1 pairs soft values Y on the basis of the received information bits ka 、Y kb And the check bit soft value calculates the conditional transition probability in the branch metric; the sub-decoder DEC2 calculates conditional transition probabilities in the branch metrics from the interleaved information bit pair soft values and the check bit soft values. The sub-decoder DEC1 decodes the information bits by using the conditional transition probabilities stored therein and the prior information transmitted from the sub-decoder DEC2, and outputs the posterior log-likelihood ratio L (u) of the information bits after decoding k ) Hard decision bits based on LLR and external information are transmitted to a sub-decoder DEC2 to be prior information after being interleaved. Then the sub-decoder DEC2 decodes using the conditional transition probability stored in itself and the prior probability transferred from DEC1, the decoding process is the same as that of the sub-decoder DEC1, but the output of the sub-decoder DEC2 needs to be deinterleaved and then transferred to the sub-decoder DEC1 as prior information. Thus, after a plurality of iterative decoding processes, in the ith iterative decoding process (i)>1) And after the decoding of each sub-decoder is finished, iteration termination judgment is carried out, if termination conditions are met, iteration is terminated, a hard judgment result is output, decoding output bits are obtained, and if not, next iteration decoding is carried out.
When the initial state and the termination state of the encoder are consistent, the receiving end needs to accurately predict the state. The general solution to this problem is to obtain the loop state S by means of pre-decoding before starting decoding c The predicted loop states are then passed to a formally decoded decoder and the metric states of the forward state metrics a and the backward state metrics β are initialized. The concrete implementation steps are as follows:
1. for the pre-decoding first iteration, the initial state is uncertain, so all states are set to equal probability:
α 0 (s)＝β N (s)＝-mlog2；
2. the loop state is detected once in each iteration, and the detection formula is as follows:
the latter two terms are constant terms, and the omission of constant term calculation does not affect the relative magnitude between the cycle states.
3. Before the next iteration, alpha is determined according to the predicted loop state 0 (s) and beta N (s) initializing:
4. after M rounds of pre-iteration, a reliable loop state S is considered to have been obtained c And then performing a formal iterative process, wherein the initial value of the state metric refers to the formula in the step (3).
In the prior art, the entire duobinary decoder includes two sub-decoders for performing serial iterative decoding. Since the two sub-decoders function identically and each sub-decoder module requires a large amount of computational and memory resources, using this technique consumes a large amount of hardware resources and increases the cost of baseband signal processing.
In the prior art, the loop state is obtained by one-time pre-decoding, but the loop states detected by each iteration of the pre-decoding are not necessarily the same, and the prediction result tends to be stable only after the pre-decoding iteration reaches a certain number of times.
Duobinary Turbo codes are widely applied to modern digital communication, but because the decoding schemes of duobinary Turbo codes are all based on blocks, particularly when an iterative decoding algorithm based on soft input and soft output is used, the decoding algorithm is complex, and large hardware resource consumption and decoding delay are generated in the decoding process, so that the performance of a decoding module can be greatly influenced by optimization of the decoding algorithm.
In the traditional duo-binary Turbo decoding cyclic iteration process, two sub-decoder modules are required to perform alternate serial decoding. Each sub-decoder module has the same function, and needs to calculate state transition metrics, extrinsic information, likelihood ratio information, etc. according to the input soft information, and a large amount of calculation and storage resources need to be consumed in the calculation process. Therefore, the presence of two sub-decoder modules in the circuit at the same time causes the whole duobinary Turbo decoding module to consume a large amount of hardware resources, so that the cost of baseband signal processing in the processor is increased.
The duobinary Turbo coding method is an 8-state self-tailing cyclic convolutional code, and the initial state and the final state of the encoder are always the same. However, at the receiving end, the duobinary Turbo decoder only knows that the initial state and the final state are the same, and cannot know the specific value of the cyclic state. If the loop state cannot be predicted accurately, the overall performance of the decoder is reduced. The conventional method is to make the data pass through a pre-decoding module to obtain the value of the cycle state, that is, to make the input data perform a decoding once, and to make the last state obtained after the decoding as the initial state of the decoder, and then perform the subsequent decoding. This corresponds to an increase in the number of decoding iterations, causing additional decoding delay.
Through the above analysis, the problems and defects of the prior art are as follows:
(1) In the existing duo-binary decoder, because the two sub-decoders have the same function and each sub-decoder module needs a large amount of calculation and storage resources, the use of the technology consumes a large amount of hardware resources and increases the cost of baseband signal processing.
(2) In the existing duo-binary decoder, a cyclic state is obtained through one-time pre-decoding, a prediction result tends to be stable after pre-decoding iteration reaches a certain number of times, and the decoder can start decoding only after waiting for a detection result of the cyclic state, so that the delay of the decoder is increased.
(3) Because the decoding scheme of the duo-binary Turbo code is based on the block unit, when the iterative decoding algorithm based on soft input and soft output is used, the decoding algorithm is more complex, and the decoding process has larger hardware resource consumption and decoding delay, so the performance of a decoding module can be greatly influenced by the optimization of the decoding algorithm.
(4) In the traditional duobinary Turbo decoding calculation process, a large amount of calculation and storage resources are required to be consumed, and the fact that two sub-decoder modules exist in a circuit at the same time can cause the whole duobinary Turbo decoding module to consume a large amount of hardware resources, so that the cost of baseband signal processing in a processor is increased.
(5) In the duo-binary Turbo coding method, a duo-binary Turbo decoder at a receiving end only knows that an initial state and a final state are the same, but cannot know a specific value of a cycle state. If the loop state cannot be predicted accurately, the overall performance of the decoder will be reduced. The conventional method increases the number of decoding iterations, resulting in additional decoding delay.
The difficulty in solving the above problems and defects is:
the duo-binary Turbo decoding adopts a cyclic iterative decoding algorithm, and is compared with other channel decoding schemes; the duo-binary Turbo decoding algorithm has very high complexity and very high hardware implementation difficulty, and a lot of storage resources and calculation resources are consumed in the process. And the decoding requires repeated iterations, the decoding delay is large. Two sub-decoder modules are required in the traditional duobinary decoding module, and the resource consumption of each sub-decoder module is very large, so that the whole decoding module needs to consume more resources. The conventional way of pre-decoding to obtain the loop state results in a larger decoding delay. Therefore, the whole decoding module must take into account many factors such as hardware implementation complexity, resource consumption, time delay, decoding performance, etc., and obtain an optimal solution on the basis.
The significance of solving the problems and the defects is as follows: the baseband signal processing is a vital part of the whole communication system, and the channel decoding module affects the accuracy and transmission rate of data transmission of the whole communication system. Therefore, the design of a decoding circuit with low complexity, small time delay and low resource consumption has great effect on the performance improvement of the whole communication system.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a duo-binary Turbo decoding implementation method, a duo-binary Turbo decoding implementation system, duo-binary Turbo decoding equipment and application.
The invention is realized in this way, a duo-binary Turbo decoding realization method, which comprises the following steps:
step one, the sub-decoder module receives the soft value Y of the information bit kp1 、Y kp2 And soft value Y of check bit ka 、Y kb Caching, wherein a top-level control module controls the soft value of the information bit to be interleaved and cached;
step two, the top control module judges the current iteration times to select the information bit soft value or the interleaved information bit soft value as the information sequence input by the current sub-decoder;
step three, selecting a soft value Y of the check bit ka Or Y kb As the check sequence input to the current sub-decoder; selecting interleaving or de-interleaving module to output prior information L as current sub-decoder input a (u k ) The first iterative decoding defaults to 0;
step four, the control parameters are input into the sub-decoder module to calculate the state transition measurement, the external information and the output soft information; and after the decoding of each sub-decoder module is finished, the top-layer control module judges whether the iteration times are reached.
The method comprises the following steps: turbo coding is a cyclic iterative coding, and requires buffering input soft information for each iterative decoding.
Step two: the encoder circuit has two identical component encoder modules, wherein the input bits of the first component encoder module are original information bits, and the input of the second component encoder module is interleaved information bits. And the decoder circuit corresponds to the encoder circuit. Since there is only one sub-decoder block in the decoding circuit, each iteration requires the control of the soft information input of the sub-decoder block. The iteration times are used for controlling the process, and the hardware implementation complexity is reduced.
Step three: turbo decoding is cyclic iterative decoding, and decoding information is exchanged between two sub-decoders to improve decoding performance. It is therefore necessary to control the outer information output of the sub-decoder to interleave or deinterleave. Because the whole circuit only uses one sub-decoder module, the external information output of the sub-decoder module is controlled to be interleaved or de-interleaved in each iteration and is used as the prior information input of the next sub-decoder.
Step four: the Turbo decoder is responsible for the calculation among the state transition measurement, the external information and the soft information in the whole decoding process. By adopting the design of module separation, the sub-decoder module is only responsible for calculating the input information, and the control is realized by the top module, so that the whole decoding circuit has simpler structure and is more convenient to debug.
Further, in step four, the determining, by the top-level control module, whether the number of iterations is reached includes:
if so, stopping iteration, controlling output soft information to perform de-interleaving, and performing hard decision to obtain a decoding sequence; if not, selecting the output external information of the sub-decoder to enter an interleaver or a de-interleaver, calculating the boundary state output by the sub-decoder module as the initial state value of the next sub-decoder module, and continuing iteration.
Further, the control process of the top control module comprises:
(1) Controlling the input information bit soft value and the check bit soft value to perform serial-parallel conversion, and dividing the input information bit soft value and the check bit soft value into two lines to be cached in a BRAM (broadband remote access module); meanwhile, counting the input enabling signal and determining the Tubro decoding code length L; inputting the soft value of the information bit into an interleaving module for interleaving, and caching the interleaved information sequence;
(2) The top-level control module starts decoding, the iteration number cnt of the initialized parameter decoding is 0, and the prior information L a (u k ) Is 0, code length L;
(3) When the cnt value is judged to be an even number, the information bit soft value and the check bit soft value Y are selected ka The output of the de-interleaver is used as the input of the information sequence, the check sequence and the prior information of the sub-decoder, and the output of the external information L is controlled after the decoding of the sub-decoder is finished e (u k ) Entering an interleaver for interleaving; when the cnt value is judged to be odd, the soft value of the interleaved information bit and the soft value Y of the check bit are selected kb The output of the interleaver is used as the input of the information sequence, the check sequence and the prior information of the sub-decoder, and the output of the external information L is controlled after the decoding of the sub-decoder is finished e (u k ) Entering a de-interleaver for de-interleaving;
(4) After each time of decoding of the sub-decoder, performing rising edge sampling on the output effective signal of the sub-decoder; when the sampling signal is valid, the cnt value is increased by 1;
(5) Judging whether the cnt value reaches the number of the loop iteration times; if so, ending the loop iteration, and controlling the sub-decoder to output soft information for de-interleaving; soft information enters a hard decision module after de-interleaving to obtain a decoding output sequence; if not, returning to the step (3) and continuing the iteration.
Further, the control process of the loop state calculation module includes:
(1) During the first iteration, all states are set to be equal, and if N states are set, the initial state P = -log (N);
(2) Inputting the initial state into a sub-decoder module, and obtaining a forward state metric end state alpha after the first iteration is completed through the calculation of the sub-decoder module N (s) and last state of backward state metric beta 0 (s) post output, s =1,2,3 \ 8230, 8;
(3) To prevent forward state metrics alpha k (s, s') and a backward state metric β k (s, s') overflowing in the iterative computation, converting the cycle state value into a cycle state probability value for transmission;
(4) Initializing the forward state metric and the backward state metric of the sub-decoder module by initial _ state(s) before the next decoding iteration starts;
(5) And (5) circularly iterating according to the method from the step (2) to the step (4) until the decoding is completed.
Further, in the step (3), the calculation of the cycle state probability value includes the following steps:
1) Find the sum state _ sum(s) of the forward state metric and the backward state metric:
state_sum(s)＝α N (s)+β 0 (s)；
2) The initial _ state(s) is calculated as follows:
further, in step (4), the initializing forward state metrics and backward state metrics of the sub-decoder modules with initial _ state(s) before the next decoding iteration starts includes:
α 1～8 0 (s)＝β 1～8 N (s)＝initial_state(s)。
it is a further object of the invention to provide a computer device comprising a memory and a processor, the memory storing a computer program which, when executed by the processor, causes the processor to perform the steps of:
the sub-decoder module receives the soft value Y of the information bit kp1 、Y kp2 And checking the bit soft value Y ka 、Y kb Carrying out caching, wherein the top control module controls the soft value of the information bit to be interleaved and cached;
the top-level control module judges the current iteration times to select the information bit soft value or the interleaved information bit soft value as the information sequence input by the current sub-decoder;
selecting soft value Y of check bit ka Or Y kb As the check sequence input to the current sub-decoder; selecting interleaving or de-interleaving module to output prior information L as current sub-decoder input a (u k ) The first iterative decoding defaults to 0;
the control parameters are input into the sub-decoder module to calculate state transition metrics, external information and output soft information; and after the decoding of each sub-decoder module is finished, the top-layer control module judges whether the iteration times are reached.
Another objective of the present invention is to provide an information data processing terminal, where the information data processing terminal is configured to implement the duo-binary Turbo decoding implementation method.
Another objective of the present invention is to provide a duo-binary Turbo decoding implementation system for implementing the duo-binary Turbo decoding implementation method, where the duo-binary Turbo decoding implementation system includes:
a sub-decoder module DEC for soft values Y of the received information bits kp1 、Y kp2 And soft value Y of check bit ka 、Y kb Caching, calculating state transition measurement, external information and output soft information;
the top-level control module is used for controlling the soft value of the information bit to be interleaved and cached, and judging the current iteration times to select the soft value of the information bit or the interleaved soft value of the information bit as an information sequence input by the current sub-decoder; meanwhile, after the decoding of each sub-decoder module is finished, whether the iteration times are reached is judged;
the loop state calculation module is used for performing loop iteration until decoding is completed;
a data buffer module for performing information bit soft value Y kp1 、Y kp2 And checking the bit soft value Y ka 、Y kb The cache of (2);
an interleaving module for outputting the prior information L as the input of the current sub-decoder a (u k ) The first iterative decoding defaults to 0;
a de-interleaving module for outputting the prior information L as the current sub-decoder input a (u k ) The first iterative decoding defaults to 0.
The invention also aims to provide a mobile communication control system, which is used for realizing the duo-binary Turbo decoding realization method.
By combining all the technical schemes, the invention has the advantages and positive effects that: the duobinary Turbo decoding implementation system provided by the invention has the advantages that the circuit structure of the whole decoder module is improved, and the circuit structure of the whole decoder module is reasonably arranged, so that the whole decoding process of the whole circuit can be completed by only one sub decoder module, a large amount of hardware resources are saved, the hardware resource consumption is reduced, and the cost is reduced; by adopting a new method for acquiring the circulation state, the circulation state can be stably acquired under the condition of lower time delay and hardware complexity, and the delay of the decoding process is reduced.
In the duobinary Turbo decoder, extra circuit consumption is not increased in a control module at the top layer of the decoder, and the whole decoding process can be controlled only by iteration times. The structure of the duobinary Turbo decoding circuit is reasonably arranged, so that only one sub-decoder module is arranged in the whole circuit. A large amount of hardware resources are saved, and the hardware cost is reduced.
The receiving end of the invention fully embodies the idea of iterative decoding through the feedback type cyclic state acquisition method, and the structure of the original decoder is not changed, so the method can stably acquire the cyclic state without pre-decoding on the basis of not increasing the complexity of hardware realization, thereby effectively reducing the decoding time delay. In the process of transferring the circulation state, the circulation state transfer is further improved in consideration of calculation overflow, and the circulation state value is converted into the state probability to be transferred.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments of the present invention will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a block diagram of a duo-binary Turbo decoding implementation system according to an embodiment of the present invention;
in the figure: 1. a sub-decoder module DEC; 2. a top layer control module; 3. a cycle state calculation module; 4. a data caching module; 5. an interleaving module; 6. a de-interleaving module; 7. a hard decision module; 8. and a soft output module.
FIG. 2 is a schematic diagram of a duo-binary Turbo decoding implementation system according to an embodiment of the present invention.
FIG. 3 is a flowchart of a duo-binary Turbo decoding implementation method according to an embodiment of the present invention.
Fig. 4 is a loop state acquisition diagram provided by an embodiment of the invention.
FIG. 5 is a block diagram of a prior art duobinary decoding framework according to an embodiment of the present invention.
FIG. 6 is a decoding performance diagram of two loop state acquisition modes according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The decoding algorithm is deeply understood, and on the basis of ensuring the decoding performance, the complexity of decoding implementation is simplified, the resource consumption is reduced, and the decoding delay is reduced. The circuit structure is adjusted by simplifying the decoding algorithm. The consumption of resources is reduced by increasing the idea of module multiplexing; the two sub-decoders in the conventional decoder are identical, so that the resource consumption is reduced by multiplexing the sub-decoder modules. Duobinary Turbo decoding is cyclic iterative decoding, so the number of iterations determines the decoding delay. The conventional loop state acquisition method needs several pre-decoding, which undoubtedly increases the number of iterations and delays in decoding. Therefore, the method of feedback type loop iteration acquisition is adopted, and the decoding delay is reduced on the basis of ensuring the decoding performance. And moreover, the overflow of data in the hardware implementation process is considered, the state transfer is normalized, and the cycle state transfer is ensured to be correct.
In view of the problems in the prior art, the present invention provides a duo-binary Turbo decoding method, system, device and application thereof, which are described in detail below with reference to the accompanying drawings.
As shown in fig. 1, the duo-binary Turbo decoding implementation system provided in the embodiment of the present invention includes: the device comprises a sub decoder module DEC1, a top layer control module 2, a cycle state calculation module 3, a data cache module 4, an interleaving module 5, a de-interleaving module 6, a hard decision module 7 and a soft output module 8.
A sub-decoder module DEC1 for receiving the information bitsSoft value Y kp1 、Y kp2 And soft value Y of check bit ka 、Y kb Caching, calculating state transition measurement, external information and output soft information;
the top-level control module 2 is used for controlling the soft values of the information bits to be interleaved and cached, and judging the current iteration times to select the soft values of the information bits or the interleaved soft values of the information bits as an information sequence input by the current sub-decoder; meanwhile, after the decoding of each sub-decoder module is finished, whether the iteration times are reached is judged;
the loop state calculation module 3 is used for performing loop iteration until decoding is completed;
a data buffer module 4 for carrying out the information bit soft value Y kp1 、Y kp2 And checking the bit soft value Y ka 、Y kb Caching;
an interleaving module 5 for outputting the prior information L as the input of the current sub-decoder a (u k ) The first iterative decoding defaults to 0;
a de-interleaving module 6 for outputting the prior information L as the input of the current sub-decoder a (u k ) The first iterative decoding defaults to 0.
The schematic diagram of a duo-binary Turbo decoding implementation system provided by the embodiment of the invention is shown in fig. 2.
As shown in fig. 3, the duo-binary Turbo decoding implementation method provided by the embodiment of the present invention includes the following steps:
s101, the sub-decoder module receives the soft value Y of the information bit kp1 、Y kp2 And checking the bit soft value Y ka 、Y kb Caching, wherein a top-level control module controls the soft value of the information bit to be interleaved and cached;
s102, the top-level control module judges the current iteration times to select the information bit soft value or the interleaved information bit soft value as the information sequence input by the current sub-decoder;
s103, selecting a soft value Y of the check bit ka Or Y kb As the check sequence input to the current sub-decoder; selecting an interleaving or de-interleaving module output asPrior information L for the current sub-decoder input a (u k ) The first iterative decoding defaults to 0;
s104, inputting control parameters into the sub-decoder module to calculate state transition metrics, external information and output soft information; and after the decoding of each sub-decoder module is finished, the top-layer control module judges whether the iteration times are reached.
The technical solution of the present invention is further described with reference to the following examples.
1. It is a first object of the present invention to improve the circuit structure of the entire decoder block so that the entire decoding process can be completed with only one sub-decoder block. Hardware resource consumption is reduced, and cost is reduced. The second purpose of the invention is to obtain the loop iteration state in a new mode, and the loop iteration state can be stably and accurately obtained without pre-decoding, so that the time delay of a decoder is reduced.
2. The block diagram of the duo-binary Turbo decoder aimed at by the invention is shown in fig. 2, and comprises a sub-decoder module DEC; firstly, the received information bit soft value Y is kp1 、Y kp2 And checking the bit soft value Y ka 、Y kb And (6) caching. The top control module controls the soft value of the information bit to be interleaved and buffered. Then the top control module judges the current iteration times to select the information bit soft value or the interleaved information bit soft value as the information sequence input by the current sub-decoder; selecting soft value Y of check bit ka Or Y kb As the check sequence input to the current sub-decoder; selecting interleaving or de-interleaving module to output prior information L as current sub-decoder input a (u k ) (the first iterative decoding defaults to 0). The control parameters are input to the sub-decoder module to calculate state transition metrics, extrinsic information, and output soft information. After the decoding of each sub-decoder module is finished, the top-level control module judges whether the iteration times are reached; if so, stopping iteration, controlling output soft information to perform de-interleaving, and performing hard decision to obtain a decoding sequence. If not, selecting the outer information output by the sub-decoder to enter the interleaver or the de-interleaver, and calculating the boundary state output by the sub-decoder moduleAnd taking the initial value of the state of the next sub-decoder module, and continuing iteration.
In the Turbo decoding mode in the specific implementation of the present invention, the control process of the top control module includes the following steps:
(1) Controlling the input information bit soft value and the check bit soft value to perform serial-parallel conversion, and dividing the input information bit soft value and the check bit soft value into two lines to be cached in a BRAM (broadband remote access module); meanwhile, the input enable signal is counted to determine the Tubro decoding code length L. Then, the soft value of the information bit is input to an interleaving module for interleaving, and the interleaved information sequence is cached.
(2) And the top-level control module starts decoding, the number cnt of initialization parameter decoding iterations is 0, the prior information La (uk) is 0, and the code length L is obtained.
(3) When the cnt value is judged to be an even number, the information bit soft value and the check bit soft value Y are selected ka The output of the de-interleaver is used as the input of the information sequence, the check sequence and the prior information of the sub-decoder, and the output of the external information L is controlled after the decoding of the sub-decoder is finished e (u k ) And entering an interleaver for interleaving. When the cnt value is judged to be odd, the soft value of the interleaved information bit and the soft value Y of the check bit are selected kb The output of the interleaver is used as the input of the information sequence, the check sequence and the prior information of the sub-decoder, and the output of the external information L is controlled after the decoding of the sub-decoder is finished e (u k ) And entering a de-interleaver for de-interleaving.
(4) After each time of decoding of the sub-decoder, performing rising edge sampling on an output effective signal of the sub-decoder; when the sample signal is active, the cnt value is incremented by 1.
(5) And judging whether the cnt value reaches the number of the circulating iteration times, if so, ending the circulating iteration, and controlling the sub-decoder to output soft information for de-interleaving. And after de-interleaving, the soft information enters a hard decision module to obtain a decoding output sequence. If not, returning to the step (3) and continuing the iteration.
As shown in fig. 4, in the Turbo decoding mode in the specific implementation of the present invention, the loop state calculation module includes the following steps:
(1) And setting all states to be equal at the first iteration, and setting N states in total, wherein the initial state P = -log (N).
(2) Inputting the initial state into a sub-decoder module, and obtaining a forward state metric end state alpha after the first iteration is completed through the calculation of the sub-decoder module N (s) and last state β of the backward state metric 0 And(s) post-output, s =1,2,3 \ 8230, 8.
(3) To prevent forward state metrics alpha k (s, s') and a backward state metric β k (s, s') overflow in the iterative computation, and the cycle state value is converted into a cycle state probability value to be transmitted. The calculation steps of the cycle state probability value are as follows:
1) Find the sum state _ sum(s) of the forward state metric and the backward state metric:
state_sum(s)＝α N (s)+β 0 (s)；
2) The initial _ state(s) is calculated as follows:
(4) Initializing forward state metrics and backward state metrics of the sub-decoder blocks with initial _ state(s) before beginning a next decoding iteration, comprising:
α 1～8 0 (s)＝β 1～8 N (s)＝initial_state(s)。
(5) And (5) circularly iterating according to the method from the step (2) to the step (4) until the decoding is completed.
3. Key point and point to be protected of the invention
(1) In the duobinary Turbo decoder, extra circuit consumption is not increased in a control module at the top layer of the decoder, and the whole decoding process can be controlled only by iteration times. The structure of the duo-binary Turbo decoding circuit is reasonably arranged, so that only one sub-decoder module is arranged in the whole circuit. A large amount of hardware resources are saved, and the hardware cost is reduced.
(2) The receiving end of the invention fully embodies the idea of iterative decoding through the feedback type cyclic state acquisition method, and the structure of the original decoder is not changed, so that the method can stably acquire the cyclic state without pre-decoding on the basis of not increasing the complexity of hardware realization, and effectively reduces the decoding time delay. In the process of transmitting the circulating state, the circulating state transmission is further improved in consideration of calculating overflow, and the circulating state value is converted into the state probability for transmission.
4. Advantages of the invention
(1) The invention can complete the whole decoding process by only using one sub-decoder through reasonably arranging the decoder circuit structure, thereby saving the hardware resource of one sub-decoder and reducing the hardware cost.
(2) The invention is stable and accurate by a feedback type cyclic state acquisition method, and effectively reduces the decoding delay.
In the duo-binary Turbo decoder, the code length is 520 bytes, and the code rate is 1/2. Respectively implementing hardware of the traditional scheme and the scheme of the invention under the same parameters, respectively integrating the traditional duo binary Turbo decoding module and the new duo binary Turbo decoding module in Vivado 2017.4 to obtain the resource consumption comparison:
matlab simulates the two cyclic state acquisition methods to acquire an error rate curve graph. The Turbo code length is 520 bytes, the code rate is 1/2, the traditional method pre-decodes once, and formally decodes four times. The number of decoding iterations of the feedback iteration method is 4.
As can be seen from fig. 6, in the case of one-time pre-decoding, the decoding performance is very poor because the accuracy of obtaining the loop state is not high after one-time pre-decoding iteration, and if the detection is wrong, the performance of formal iterative decoding is reduced, and the pre-decoding mode has an error code platform in a high signal-to-noise ratio region, and the decoding performance is improved little along with the improvement of the signal-to-noise ratio. If better decoding performance is desired by the pre-decoding method, the number of pre-decoding operations is increased, which increases the decoding delay. And the loop state is obtained by adopting feedback iteration, the decoding performance is good, and the time for pre-decoding can be saved, thereby effectively reducing the decoding delay.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When used in whole or in part, can be implemented in a computer program product that includes one or more computer instructions. When loaded or executed on a computer, cause the flow or functions according to embodiments of the invention to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions may be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center via wire (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL), or wireless (e.g., infrared, wireless, microwave, etc.)). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that includes one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk (SSD)), among others.
The above description is only for the purpose of illustrating the present invention and the appended claims are not to be construed as limiting the scope of the invention, which is intended to cover all modifications, equivalents and improvements that are within the spirit and scope of the invention as defined by the appended claims.
Claims (5)
1. A duo-binary Turbo decoding implementation method is characterized in that the duo-binary Turbo decoding implementation method comprises the following steps:
sub-decoder moduleSoft value Y of received information bit kp1 、Y kp2 And checking the bit soft value Y ka 、Y kb Carrying out caching, wherein the top control module controls the soft value of the information bit to be interleaved and cached;
the top-level control module judges the current iteration times to select the information bit soft value or the interleaved information bit soft value as the information sequence input by the current sub-decoder;
selecting soft value Y of check bit ka Or Y kb As the check sequence input to the current sub-decoder; selecting interleaving or de-interleaving module to output prior information L as current sub-decoder input a (u k ) The first iterative decoding defaults to 0;
the control parameters are input into the sub-decoder module to calculate the state transition measurement, the external information and the output soft information; after the decoding of each sub-decoder module is finished, the top control module judges whether the iteration times are reached;
the top control module judges whether the iteration times are reached, and the method comprises the following steps: if so, stopping iteration, controlling output soft information to perform de-interleaving, and performing hard decision to obtain a decoding sequence; if not, selecting the output external information of the sub-decoder to enter an interleaver or a de-interleaver, calculating the boundary state output by the sub-decoder module as the initial state value of the next sub-decoder module, and continuing iteration;
the control process of the top control module comprises the following steps:
(1) Controlling the input information bit soft value and the check bit soft value to perform serial-parallel conversion, and dividing the input information bit soft value and the check bit soft value into two lines to be cached in a BRAM (block buffer memory); meanwhile, counting the input enabling signals and determining the Tubro decoding code length L; inputting the soft value of the information bit into an interleaving module for interleaving, and caching the interleaved information sequence;
(2) The top-level control module starts decoding, the iterative times cnt of the initialized parameter decoding are 0, and the prior information L a (u k ) Is 0, code length L;
(3) When the cnt value is judged to be an even number, the information bit soft value and the check bit soft value Y are selected ka The deinterleaver outputs the information sequence as a sub-decoder, and the correctionThe test sequence and the prior information are input, and the output external information L is controlled after the decoding of the sub-decoder is finished e (u k ) Entering an interleaver for interleaving; when the cnt value is judged to be odd, the soft value of the interleaved information bit and the soft value Y of the check bit are selected kb The output of the interleaver is used as the input of the information sequence, the check sequence and the prior information of the sub-decoder, and the output of the external information L is controlled after the decoding of the sub-decoder is finished e (u k ) Entering a de-interleaver for de-interleaving;
(4) After each time of decoding of the sub-decoder, performing rising edge sampling on an output effective signal of the sub-decoder; when the sampling signal is valid, the cnt value is increased by 1;
(5) Judging whether the cnt value reaches the number of the loop iteration times; if so, ending the loop iteration, and controlling the sub-decoder to output soft information for de-interleaving; soft information enters a hard decision module after de-interleaving to obtain a decoding output sequence; if not, returning to the step (3) and continuing iteration;
the control process of the circulation state calculation module comprises the following steps:
(1) During the first iteration, all states are set to be equivalent, and if N states are set, the initial state P = -log (N);
(2) Inputting the initial state into a sub-decoder module, and obtaining a forward state metric final state alpha after the first iteration is completed through the calculation of the sub-decoder module N (s) and last state of backward state metric beta 0 (s) post output, s =1,2,3 \ 8230, 8;
(3) To prevent forward state metrics alpha k (s, s') and a backward state metric β k (s, s') overflowing in the iterative computation, converting the cycle state value into a cycle state probability value for transmission;
(4) Initializing the forward state metric and the backward state metric of the sub-decoder module with initial _ state(s) before the next decoding iteration starts;
(5) Iterating according to the method of the step (2) to the step (4) until the decoding is completed;
in the step (3), the calculation of the cycle state probability value comprises the following steps:
1) Find the sum state _ sum(s) of the forward state metric and the backward state metric:
state_sum(s)＝α N (s)+β 0 (s)；
2) The initial _ state(s) is calculated as follows:
in step (4), initializing the forward state metric and the backward state metric of the sub-decoder module with initial _ state(s) before the next decoding iteration starts, including:
α 1～8 0 (s)＝β 1～8 N (s)＝initial_state(s)。
2. a computer device comprising a memory and a processor, the memory storing a computer program that, when executed by the processor, causes the processor to perform the duobinary Turbo decoding implementation of claim 1.
3. An information data processing terminal, characterized in that, the information data processing terminal is used to implement the duo-binary Turbo decoding implementation method of claim 1.
4. A duo-binary Turbo decoding implementation system for implementing the duo-binary Turbo decoding implementation method of claim 1, wherein the duo-binary Turbo decoding implementation system comprises:
a sub-decoder module DEC for decoding the received information bit soft values Y kp1 、Y kp2 And checking the bit soft value Y ka 、Y kb Caching, calculating state transition measurement, external information and output soft information;
the top-level control module is used for controlling the soft values of the information bits to be interleaved and cached, and judging the current iteration times to select the soft values of the information bits or the interleaved soft values of the information bits as an information sequence input by the current sub-decoder; meanwhile, after the decoding of each sub-decoder module is finished, whether the iteration times are reached is judged;
the loop state calculation module is used for performing loop iteration until decoding is completed;
a data buffer module for performing soft value Y of information bit kp1 、Y kp2 And checking the bit soft value Y ka 、Y kb Caching;
an interleaving module for outputting the prior information L as the input of the current sub-decoder a (u k ) The first iterative decoding defaults to 0;
a de-interleaving module for outputting the prior information L as the current sub-decoder input a (u k ) The first iterative decoding defaults to 0.
5. A mobile communication control system, wherein the mobile communication control system is configured to implement the duo-binary Turbo decoding implementation method of claim 1.
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