CN113872615A - Variable-length Turbo code decoder device - Google Patents

Variable-length Turbo code decoder device Download PDF

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CN113872615A
CN113872615A CN202111176822.1A CN202111176822A CN113872615A CN 113872615 A CN113872615 A CN 113872615A CN 202111176822 A CN202111176822 A CN 202111176822A CN 113872615 A CN113872615 A CN 113872615A
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杨丽云
张亚林
方真
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CETC 54 Research Institute
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2771—Internal interleaver for turbo codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H03M13/296—Particular turbo code structure
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H03M13/2978—Particular arrangement of the component decoders

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Abstract

The invention discloses a variable-length Turbo code decoder device, and belongs to the field of Turbo code decoders. The device comprises a variable-length interleaver module, a controller, a SISO component decoder module and a data storage module, can set the length of an input data frame by a user according to different index requirements of the system on information reliability and data real-time property, can adapt to different application scenes, and has wide application value.

Description

Variable-length Turbo code decoder device
Technical Field
The invention relates to the technical field of Turbo code decoders, in particular to a variable-length Turbo code decoder device.
Background
Turbo codes, proposed in 1993 by c.berrou and Alain Glavieux, have been widely used in communication systems due to their excellent performance approaching the shannon theoretical limit. The Turbo code is a parallel cascade convolution code, combines component code and random interleaver, adopts parallel cascade structure, and realizes the idea of random coding. The Turbo decoding adopts the iterative decoding idea of soft input and soft output, and achieves the performance close to the Shannon theoretical limit.
A common Turbo code decoder principle is shown in fig. 1 and consists of two soft-input soft-output (SISO) component decoders DEC1 and DEC2 cascaded in series, the interleaver used in the decoder must be the same as the interleaver in the encoder. The DEC1 and DEC2 respectively perform optimal decoding on two component codes in the encoder, and send each obtained extrinsic information to the other component decoder as the prior information of the extrinsic information. After multiple iterations, the external information of DEC1 and DEC2 tends to be stable, the likelihood ratio approaches to maximum likelihood decoding, and then hard decision is carried out on the likelihood ratio to finish the decoding process.
The error code performance and the time delay of the Turbo code are greatly dependent on the length of an information frame, the longer the frame length is, the longer the interleaving length of the interleaver is, the more the Turbo code is similar to a random long code, the better the decoding performance is, and the larger the decoding time delay is. The traditional Turbo code decoder hardware design is a solidified design by selecting a single parameter according to a simulation result, when indexes change, a program needs to be greatly modified and reconfigured, even a system scheme is replaced, and the universality is lacked.
Disclosure of Invention
In view of the above, the present invention provides a variable-length Turbo code decoder device to avoid the above drawbacks in the background art, and the device can set the frame length by the user according to the requirement, so that the decoding delay and the decoding performance can reach the optimal balance under different channel environments, and has a wide application value.
In order to achieve the purpose, the invention adopts the technical scheme that:
a variable length Turbo code decoder device comprises a variable length interleaver module, a controller, a SISO component decoder module and a data storage module; wherein the content of the first and second substances,
the Turbo code decoder device stores the data into the data storage module after receiving a frame of data to be decoded;
the controller sends out a starting identifier, starts the variable-length interleaver module, finishes interleaving operation according to different data lengths, and writes the mapping pattern into the data storage module for storage;
after the generation of the interleaving address is finished, the controller sends out a first frame data decoding starting identifier to control the SISO component decoder module to start iterative decoding;
the SISO component decoder module adopts a component decoder circuit, and realizes the functions of two component decoders in a multiplexing mode under the control of a controller; the SISO component decoder module uniformly subdivides an input data frame into small data frames by adopting a sliding window MAX-LOG-MAP decoding algorithm, and performs independent decoding on each sub-frame until all sub-frames are decoded;
and when the iteration times reach a program set value, the controller performs hard judgment on the likelihood ratio output by the SISO component decoder module to obtain a decoding result.
Furthermore, the variable-length interleaver module adopts an interleaver generation mode recommended in the 3GPP standard, the interleaver is variable in length, and the length of the interleaver is controlled by user input; the variable-length interleaver module calculates the mapping patterns of interleaving and deinterleaving, writes the mapping patterns into the data storage module, and reads the mapping patterns through the controller when the mapping patterns are to be used, so that the interleaving and deinterleaving are completed.
Further, the SISO component decoder module comprises a branch transition metric γ calculating module, a training backward metric train- β calculating module, a valid backward metric β calculating module, a forward metric α and a log likelihood ratio llr calculating module; wherein the content of the first and second substances,
uniformly dividing a frame of data into subframe data with consistent length, wherein each subframe data becomes an independent window, and performing independent decoding operation on each subframe data; the SISO component decoder module uses a sliding window MAX-LOG-MAP algorithm, and the decoding process is as follows:
(1) calculating branch transfer metric gamma and storing the branch transfer metric gamma in a memory;
(2) assuming that the initial training backward metric train-beta of each window is 0 or an equal probability value, calculating the first bit of the window by using the reverse recursion of the previous window, wherein the state information of the bit is the train-beta of the window;
(3) taking the value of train-beta as an initial value of effective backward measurement beta recursive calculation of a current window, and reading gamma for solving beta;
(4) reading γ and β to solve for the forward metric α and log likelihood ratio llr;
(5) continuously recursion is carried out according to the grid time until a complete frame of data is solved;
(6) the above operation is repeated until the number of iterations satisfies the value set in the program.
Compared with the background technology, the invention has the following advantages:
(1) the invention adopts a sliding window MAX-LOG-MAP algorithm and combines a storage table to realize a variable length interleaver, effectively solves the problems of excessive resource occupation and prolonged decoding time, and has the characteristics of novelty and creativity.
(2) The invention is suitable for decoding variable-length data frames, makes the decoding performance and the decoding time delay reach the optimal balance, has the characteristics of multiple application scenes and strong practicability, and has wide application value.
Drawings
Fig. 1 is a block diagram illustrating a Turbo decoding principle commonly used in the background art.
FIG. 2 is a block diagram of a Turbo decoding apparatus according to an embodiment of the present invention.
Fig. 3 is a detailed block diagram of the SISO module of fig. 2.
Detailed Description
The technical solution of the present invention will be further described in detail with reference to the accompanying drawings and the detailed description.
As shown in fig. 1-3, a variable-length Turbo code decoder device includes a variable-length interleaver module, a controller, a SISO component decoder module, and a data storage module, in this case, the data storage module employs a RAM; wherein the content of the first and second substances,
the Turbo code decoder device stores the data into the RAM after receiving a frame of data to be decoded; the controller sends out a starting identifier, starts a variable-length interleaver module, finishes interleaving operation according to different data lengths, and writes the mapping pattern into the RAM for storage; after the generation of the interleaving address is finished, the controller sends out a first frame data decoding starting identifier to control the SISO component decoder module to start iterative decoding. The SISO component decoder module adopts a component decoder circuit, realizes the functions of two component decoders in a multiplexing mode under the control of a controller, uniformly subdivides an input data frame into small data frames by adopting a sliding window MAX-LOG-MAP decoding algorithm, and independently decodes each sub-frame until all sub-frames finish decoding. And repeating the decoding process, and when the iteration times reach a program set value, performing hard judgment on the likelihood ratio output by the component decoder to obtain a decoding result.
Further, the variable-length interleaver module adopts an interleaver generation method recommended in the 3GPP standard, and the interleaver is variable-length. In order to reduce the hardware complexity and save hardware resources, a C program is designed to calculate a mapping pattern of interleaving and de-interleaving during implementation, the mapping pattern is written into an RAM, and the mapping pattern is read and used under the control of a controller when the mapping pattern is to be used, so that interleaving and de-interleaving are completed.
Further, the controller mainly performs the following control:
1) controlling the read-write operation of the RAM;
2) controlling the multiplexing of the component decoder to determine whether to use as DEC1 or DEC 2;
3) deciding to interleave or deinterleave the external information;
4) controlling the iteration times;
5) a hard decision output is enabled.
The specific process is as follows:
1) waiting for external input data, starting a variable-length interleaver module, calculating a mapping pattern according to the length of the input data, and storing the mapping pattern into an RAM;
2) sending the identification signal of starting calculation of the window to each decoder module;
3) sending a first iteration starting signal and a signal for selecting whether to carry out interleaving and de-interleaving to each module;
4) sending a starting signal for next iteration to each decoder module;
5) waiting for the identification signal of the end of the window operation when all the modules end the operation;
6) and outputting the decoded data according to the received window ending identification signal.
Furthermore, the SISO component decoder module adopts a component decoder circuit, and realizes the functions of two component decoders in a multiplexing mode under the action of the controller. In the embodiment, a sliding window MAX-LOG-MAP decoding algorithm is adopted, an input data frame is uniformly subdivided into small data frames, and each sub-frame is decoded independently. The method comprises a branch transfer metric gamma calculation module, a training backward metric train-beta calculation module, an effective backward metric beta calculation module, a forward metric alpha and a log likelihood ratio llr calculation module for one-time complete component decoding. Wherein the content of the first and second substances,
the solution of the branch transition metric γ is the key to solving for each of the other modules. The forward metric α, the backward metric β and the log-likelihood ratio llr all need to be computed using the value of γ. Branch transition metric calculation formula:
Figure BDA0003295504540000061
in the above formula, MK(s', s) is the logarithmic value of the branch transition metric γ;
Figure BDA0003295504540000062
the information bits and the check bits are respectively input by the decoder at the moment k; u. ofk、
Figure BDA0003295504540000063
Respectively an information bit and a check bit output by the encoder; l isa(uk) Is prior information, the outer information generated by the last component decoder is interleaved or de-interleaved, and L is the first iteration of decodinga(uk) Is 0; l isCThe channel confidence is taken as 2.
After the result of the branch transition metric is solved, the solved branch metric is separately stored in two hardware memories according to whether the input information bit is '1' or '0'. The memory co-stores three identical branch metrics, which are used to solve the training backward metric train- β module, the effective backward metric β module, the forward metric α and the log-likelihood ratio llr module, respectively.
The calculation process of the training backward metric train-beta calculation is as follows:
assuming that the initial backward metric value train- β of each window is 0 or an equivalent value, the backward recursion of the previous window is used until the first bit of the window, and at this time, the bit state information train- β is used as the initial value for the effective backward metric β of the current window. To find the initial state of the accurate effective backward metric, it is necessary to train 5 to 8 times the constraint length of the convolutional code encoder, which in this example is a (13, 15) component code, the constraint length is 4, so the length setting of the training window is 32 bits. And storing the computed train-beta value into a RAM (random access memory) and providing the RAM with the computed train-beta value for the computation of the effective backward measurement module as an initial value of the recursive computation.
Effective backward measure β calculation formula:
Bk(s)＝lnβk(s')＝max(Bk+1(s)+MK(s',s))
in the formula, Bk(s) is the logarithm of the effective backward measure β, MK(s', s) is the logarithm of the branch transition metric γ.
The effective backward measurement is calculated according to the initial value from back to front, the beta value at the next moment is used for calculating the beta value at the current moment, and the obtained calculation result needs to be stored in a memory for calculating the beta value at the previous grid moment.
The forward metric α is calculated as:
Ak(s)＝lnαk(s)＝max(Ak-1(s')+MK(s',s))
in the formula, Ak(s) is the logarithm of the forward metric α, MK(s', s) is the logarithm of the branch transition metric γ.
The calculation of the forward measurement alpha is performed forward recursion calculation according to the forward state initial value, the alpha value of the previous time is used for the alpha calculation of the current time, and the obtained calculation result needs to be stored in a memory for calculating the alpha value of the next grid time.
The log-likelihood ratio llr is calculated as:
Figure BDA0003295504540000081
in the formula, Ak-1(s') is the logarithm of the forward metric, MK(s', s) is the logarithm of the branch transition metric, Bk(s) is the log of the backward metric.
The values α, β and γ must be determined in the calculation of the log-likelihood ratios llr. In the implementation process, the order of sequentially outputting the extrinsic information is adopted, the β value is calculated first, and then the α value and llr are calculated to perform decision output. The log-likelihood ratios llr are calculated in the order:
1) the gamma value is calculated and stored as 3 backup;
2) solving the beta value according to the solved gamma value and storing the beta value;
3) according to the gamma value, the alpha value is obtained;
4) the values of log-likelihood ratios llr are solved from the values of alpha and beta.
In a word, the device can set the length of the input data frame by the user according to different index requirements of the system on information reliability and data real-time performance, can adapt to different application scenes, and has wide application value.
It should be noted that the present invention may have other embodiments besides the above-described implementation steps. All technical solutions which adopt equivalent substitutions or equivalent transformations fall within the protection scope of the claims of the present invention.

Claims (3)

1. A variable-length Turbo code decoder device is characterized by comprising a variable-length interleaver module, a controller, a SISO component decoder module and a data storage module; wherein the content of the first and second substances,
the Turbo code decoder device stores the data into the data storage module after receiving a frame of data to be decoded;
the controller sends out a starting identifier, starts the variable-length interleaver module, finishes interleaving operation according to different data lengths, and writes the mapping pattern into the data storage module for storage;
after the generation of the interleaving address is finished, the controller sends out a first frame data decoding starting identifier to control the SISO component decoder module to start iterative decoding;
the SISO component decoder module adopts a component decoder circuit, and realizes the functions of two component decoders in a multiplexing mode under the control of a controller; the SISO component decoder module uniformly subdivides an input data frame into small data frames by adopting a sliding window MAX-LOG-MAP decoding algorithm, and performs independent decoding on each sub-frame until all sub-frames are decoded;
and when the iteration times reach a program set value, the controller performs hard judgment on the likelihood ratio output by the SISO component decoder module to obtain a decoding result.
2. The variable-length Turbo code decoder device according to claim 1, wherein the variable-length interleaver module employs an interleaver generation method recommended in 3GPP standard, the interleaver is variable-length, and the length of the interleaver is controlled by a user input; the variable-length interleaver module calculates the mapping patterns of interleaving and deinterleaving, writes the mapping patterns into the data storage module, and reads the mapping patterns through the controller when the mapping patterns are to be used, so that the interleaving and deinterleaving are completed.
3. The variable length Turbo code decoder arrangement according to claim 2, wherein said SISO component decoder blocks comprise a branch transition metric γ computation block, a training backward metric train- β computation block, an effective backward metric β computation block, a forward metric α and a log likelihood ratio llr computation block; wherein the content of the first and second substances,
uniformly dividing a frame of data into subframe data with consistent length, wherein each subframe data becomes an independent window, and performing independent decoding operation on each subframe data; the SISO component decoder module uses a sliding window MAX-LOG-MAP algorithm, and the decoding process is as follows:
(1) calculating branch transfer metric gamma and storing the branch transfer metric gamma in a memory;
(2) assuming that the initial training backward metric train-beta of each window is 0 or an equal probability value, calculating the first bit of the window by using the reverse recursion of the previous window, wherein the state information of the bit is the train-beta of the window;
(3) taking the value of train-beta as an initial value of effective backward measurement beta recursive calculation of a current window, and reading gamma for solving beta;
(4) reading γ and β to solve for the forward metric α and log likelihood ratio llr;
(5) continuously recursion is carried out according to the grid time until a complete frame of data is solved;
(6) the above operation is repeated until the number of iterations satisfies the value set in the program.
CN202111176822.1A 2021-10-09 2021-10-09 Variable-length Turbo code decoder device Pending CN113872615A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114745076A (en) * 2022-03-22 2022-07-12 中国电子科技集团公司第五十四研究所 Code length self-adaptive interleaving/de-interleaving device and method based on FPGA

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114745076A (en) * 2022-03-22 2022-07-12 中国电子科技集团公司第五十四研究所 Code length self-adaptive interleaving/de-interleaving device and method based on FPGA
CN114745076B (en) * 2022-03-22 2024-04-30 中国电子科技集团公司第五十四研究所 FPGA-based code length self-adaptive interleaving/de-interleaving device and method

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