CN105630242A - shift register circuit - Google Patents
shift register circuit Download PDFInfo
- Publication number
- CN105630242A CN105630242A CN201511019032.7A CN201511019032A CN105630242A CN 105630242 A CN105630242 A CN 105630242A CN 201511019032 A CN201511019032 A CN 201511019032A CN 105630242 A CN105630242 A CN 105630242A
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- current potential
- reference voltage
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- 239000013078 crystal Substances 0.000 claims description 25
- 230000000977 initiatory effect Effects 0.000 claims description 22
- 210000000080 chela (arthropods) Anatomy 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 5
- 230000008878 coupling Effects 0.000 claims description 3
- 238000010168 coupling process Methods 0.000 claims description 3
- 238000005859 coupling reaction Methods 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 9
- 230000000875 corresponding effect Effects 0.000 description 5
- 230000005669 field effect Effects 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 230000002452 interceptive effect Effects 0.000 description 2
- -1 A-Si) technique Inorganic materials 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0412—Digitisers structurally integrated in a display
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
- Electronic Switches (AREA)
Abstract
A shift register circuit comprises a switch circuit, a pull-up circuit, a pull-down circuit and a clamp circuit. The pull-up circuit is electrically connected to the switch circuit, the pull-down circuit and the clamping circuit. The switch circuit comprises a first transistor, a second transistor and a third transistor. The gate of the first transistor is electrically connected to the second transistor and the third transistor. The first transistor adjusts the potential of the control signal to a first reference voltage according to the potential of the conducting signal on the grid electrode of the first transistor. The second transistor pulls up the potential of the conducting signal according to the starting signal. The third transistor resets the potential of the on signal to a second reference voltage according to the reset signal.
Description
Technical field
The present invention is about a kind of shift scratch circuit, particularly a kind of shift scratch circuit being applied to embedded touch control panel.
Background technology
In interior embedded (in-cell) contact panel, embedded touch control panel is provided with gate driver circuit and touch-control circuit on same piece of substrate, and gate drive signal line and touching signals line each other may be very close, therefore gate drive signal and touching signals can be interfering with each other. Owing to the intensity of gate drive signal is relatively strong, via capacitance coupling effect, gate drive signal often causes noise and disturbs touching signals, and reduces the signal to noise ratio (signaltonoiseratio, SNR) of touch control operation.
In traditional practice, in order to avoid touching signals to be disturbed by gate drive signal, generally when enable touch-control circuit, several signal specific in shift scratch circuit can be pulled low to low level, to avoid gate driver circuit and touch-control circuit to operate and interfering with each other simultaneously. But simultaneously, how to allow gate driver circuit is enabled in touch-control circuit this during later can normal operation again fast, then become the big problem of slip-stick artist when designing shift scratch circuit.
Summary of the invention
The invention reside in and a kind of shift scratch circuit is provided, allow shift scratch circuit is enabled at touch-control circuit this during after, can normal operation again fast.
A kind of shift scratch circuit disclosed by the present invention has switch circuit, pull-up circuit, lower puller circuit and pincers circuit. Pull-up circuit is electrically connected to switch circuit, lower puller circuit and pincers circuit. Switch circuit comprises first crystal pipe, two-transistor and third transistor. The grid of first crystal pipe is electrically connected to two-transistor and third transistor. First crystal pipe is according to current potential to the first reference voltage of the current potential adjustment control signal of the conducting signal on the grid of first crystal pipe. Two-transistor draws high the current potential of conducting signal according to initiating signal. Third transistor foundation reset signal resets the current potential of conducting signal to the 2nd reference voltage. The current potential of output signal is adjusted to the current potential of clock signal according to control signal by pull-up circuit. The current potential of output signal is adjusted to the 2nd reference voltage according to pulldown signal and control signal by lower puller circuit. The current potential of the current potential of control signal and output signal is adjusted to the 2nd reference voltage according to pincers signal by pincers circuit.
Comprehensive the above, disclosed herein a kind of shift scratch circuit, the specific node of at least one in shift scratch circuit is carried out discharge and recharge by a switch circuit in good time, so that described specific node also can be allowed to maintain desired voltage when drawing multiple signal of low shift scratch circuit, thus allow shift scratch circuit is enabled at touch-control circuit this during after, can normal operation again fast.
The above explanation about this disclosure and the explanation of following enforcement mode are in order to demonstration and spirit and the principle of explaining the present invention, and the patent application scope providing the present invention is further explained.
Accompanying drawing explanation
Fig. 1 is the function block schematic diagram of the gate driver circuit illustrated according to one embodiment of the invention.
Fig. 2 is the circuit diagram of one of them shift scratch circuit illustrated according to Fig. 1 of the present invention.
Fig. 3 is the time diagram of the shift scratch circuit illustrated according to Fig. 2 of the present invention.
Fig. 4 is the reset signal that illustrates according to one embodiment of the invention time diagram relative to the electric capacity C1 of different capacitance.
Drawing reference numeral illustrates:
1 gate driver circuit
10_1��10_10 shift scratch circuit
102 switch circuits
104 times puller circuits
106 pull-up circuits
108 pincers circuit
C1, C2 electric capacity
CK (1)��CK (10) clock signal
G (1)��G (10) gate drive signal
K (5) reset signal
LC1, LC2 pulldown signal
Q (1), Q (3), Q (5), Q (7) control signal
ST (1), ST (3), ST (5), ST (9) initiating signal
T11��T74 transistor
TP_EN touches the enable signal of control
VDD_G first reference voltage
VSS the 2nd reference voltage
Embodiment
Hereinafter detailed features and the advantage of the present invention is described in embodiments in detail, its content is enough to make those skilled in the art to understand the technology contents of the present invention and implement according to this, and content disclosed by this specification sheets, claim and graphic, those skilled in the art can understand object and the advantage that the present invention is correlated with easily. Following embodiment is the viewpoint further describing the present invention, but the non-category limiting the present invention with any viewpoint.
Please refer to Fig. 1, Fig. 1 is the function block schematic diagram of the gate driver circuit illustrated according to one embodiment of the invention. As shown in Figure 1, gate driver circuit 1 comprises shift scratch circuit 10_1��10_10. In this embodiment, gate driver circuit 1 is the structure adopting a biography three, and therefore shift scratch circuit 10_1,10_3,10_5,10_7,10_9 is sequentially connected in series each other, and shift scratch circuit 10_2,10_4,10_6,10_8,10_10 are sequentially connected in series each other. Shift scratch circuit 10_1 produces gate drive signal G (1) according to clock signal CK (1) and initiating signal ST (1), and shift scratch circuit 10_3 produces gate drive signal G (3) according to clock signal CK (3) and gate drive signal G (1). Relevant start as shift scratch circuit 10_2,10_4��10_10 is worked as and can be analogized according to Fig. 1 and foregoing, then repeats no more in this. Shift scratch circuit 10_1��10_10 makes with non-crystalline silicon (AmorphousSilicon, A-Si) technique, polysilicon (Poly-Silicon) technique or low temperature silicon substrate (low-temperaturesiliconsubstrate) technique. Follow-up is be described as demonstration example, and so in fact gate driver circuit 1 also can adopt the structure of a biography two, and not as limit.
Please then with reference to the circuit diagram that Fig. 2, Fig. 2 are one of them shift scratch circuit illustrated according to Fig. 1 of the present invention. Embodiment corresponding to Fig. 2 is be introduced for shift scratch circuit 10_5, the structure that right shift scratch circuit 10_1��10_4,10_6��10_10 have and start and shift scratch circuit 10_5 are similar, and those skilled in the art are when analogizing from this specification sheets and obtain. Shift scratch circuit 10_5 comprises switch circuit 102, lower puller circuit 104, pull-up circuit 106 and pincers circuit 108. Pull-up circuit 106 is electrically connected to switch circuit 102. Lower puller circuit 104 is electrically connected to pull-up circuit 106. Pincers circuit 108 is electrically connected to pull-up circuit 106. Shift scratch circuit 10_5 produces gate drive signal G (5) according to clock signal CK (5), initiating signal ST (3), initiating signal ST (5), initiating signal ST (9), gate drive voltage G (3), pulldown signal LC1, pulldown signal LC2, the first reference voltage VDD_G and the 2nd reference voltage VSS. Wherein, initiating signal ST (3) in shift scratch circuit 10_5 and initiating signal ST (9) can be replaced into gate drive signal G (3) and gate drive signal G (9) respectively, and the gate drive signal G (3) in shift scratch circuit 10_5 also can be replaced into initiating signal ST (3).
The current potential of gate drive signal G (5), according to pulldown signal LC1, LC2 and control signal Q (5), is adjusted to the 2nd reference voltage VSS by lower puller circuit 104. In this embodiment, in the middle of pulldown signal LC1 or pulldown signal LC2 at least in one when being noble potential, the current potential of gate drive signal G (5) and the current potential of control signal Q (5) are adjusted to the 2nd reference voltage VSS. But in another embodiment, in the middle of pulldown signal LC1 or pulldown signal LC2 at least in one when being low potential, the current potential of gate drive signal G (5) and the current potential of control signal Q (5) are adjusted to the 2nd reference voltage VSS. Under this does not limit, puller circuit 104 is that the current potential of gate drive signal is adjusted to the 2nd reference voltage VSS when which kind of voltage quasi position pulldown signal LC1, LC2 are.
The current potential of gate drive signal G (5) is adjusted to the current potential of clock signal CK (5) by pull-up circuit 106 according to control signal Q (5). In this embodiment, when control signal Q (5) is for noble potential, transistor T21 is switched on, and the current potential of gate drive signal G (5) is adjusted to the current potential of clock signal CK (5).
The current potential of the current potential of control signal Q (5) and gate drive signal G (5) is adjusted to the 2nd reference voltage VSS according to pincers signal by pincers circuit 108. It is using initiating signal ST (9) as pincers signal in this embodiment, and when initiating signal ST (9) is for noble potential, gate drive signal G (5) and control signal Q (5) are adjusted to the 2nd reference voltage VSS.
Switch circuit 102 is current potential to the first reference voltage VDD_G optionally adjusting control signal Q (5) according to initiating signal and reset signal. In this embodiment, it is using initiating signal ST (3) and initiating signal ST (5) as initiating signal and reset signal, but in fact initiating signal ST (3) and initiating signal ST (5) can be replaced into gate drive signal G (3), G (5) respectively, those skilled in the art should it will be appreciated that in follow-up style of writing occur initiating signal also optionally can exchange it with corresponding gate drive signal.
Switch circuit 102 has first crystal pipe T11, two-transistor T71, third transistor T72 and electric capacity C1. The first end of first crystal pipe T11 receives the first reference voltage VDD_G, and the 2nd end of first crystal pipe T11 is electrically connected to lower puller circuit 104 and pull-up circuit 106. The control end of first crystal pipe T11 receives reset signal K (5). The first end of two-transistor T71 receives gate drive signal G (3). 2nd end of two-transistor T71 is coupled to the control end of first crystal pipe T11, and the control end of two-transistor T71 receives initiating signal ST (3). Reception reset signal K (5) of third transistor T72, the 2nd termination of third transistor T72 receives the 2nd reference voltage VSS. The control end of third transistor T72 receives initiating signal ST (5). The 2nd termination that the first end of electric capacity C1 receives the 2nd reference voltage VSS, electric capacity C1 receives reset signal K (5).
In an embodiment, first crystal pipe T11, two-transistor T71 and third transistor T72 are N-type metal oxide semiconductcor field effect transistor (Metal-Oxide-SemiconductorField-EffectTransistor, MOSFET). In this embodiment, the conduction impedance r of third transistor T72ds_ON3It is greater than the conduction impedance r of first crystal pipe T11ds_ON1, and the conduction impedance r of third transistor T72ds_ON3It is greater than the conduction impedance r of two-transistor T71ds_ON2. In practice, the conduction impedance r of first crystal pipe T11ds_ON1With the conduction impedance r of two-transistor T71ds_ON2It is designed to substantially equal, but not as limit. Wherein, conduction impedance rds_ONIt is associated with carrier transport factor (carriermobility), the grid width of metal oxide semiconductcor field effect transistor, the grid length of metal oxide semiconductcor field effect transistor, and the specific capacitance size of the grid oxic horizon of metal-oxide half field effect transistor.
In practice, the first end of electric capacity C1 also can receive the first reference voltage VDD_G, to form a coupling path between the first reference voltage VDD_G and reset signal K (5). Or the first end of electric capacity C1 also can be coupled to pull-up circuit 106, to form a coupling path between control signal Q (5) and reset signal K (5). It should be noted that in the embodiment of another kind, switch circuit 102 does not have electric capacity C1. In one embodiment, the first reference voltage VDD_G is greater than the 2nd reference voltage VSS, but not as limit.
Switch circuit 102 adjusts the current potential of control signal Q (5) in order to selectivity, thus adjusts the current potential of gate drive signal G (5) linkedly. In switch circuit 102, first crystal pipe T11 is according to current potential to the first reference voltage VDD_G of current potential adjustment control signal Q (5) of the reset signal K (5) on the grid of first crystal pipe T11. Two-transistor T71 draws high the current potential of reset signal K (5) according to initiating signal ST (3). Third transistor T72 foundation reset signal ST (5) resets the current potential of reset signal K (5) to the 2nd reference voltage VSS.
, as Figure 2 illustrates, in addition switch circuit 102 also has transistor T73 or transistor T74. The 2nd termination that the first end of transistor T73 receives the 2nd reference voltage VSS, transistor T73 receives control signal Q (5), and the control end of transistor T73 receives the enable signal TP_EN of tactile control. The 2nd termination that the first end of transistor T74 receives the 2nd reference voltage VSS, transistor T74 receives gate drive signal G (5), and the control end of transistor T74 receives the enable signal TP_EN of tactile control. In this embodiment, when the enable signal TP_EN of tactile control is noble potential, gate drive signal G (5) and control signal Q (5) are adjusted to the 2nd reference voltage VSS. Wherein, touch the enable signal TP_EN of control and indicate whether touch-control circuit is scanning, to make shift scratch circuit 10_5 carry out corresponding start.
Please refer to Fig. 3, Fig. 3 is the time diagram of the shift scratch circuit illustrated according to Fig. 2 of the present invention. Fig. 3 illustrates the relative timing touching the enable signal TP_EN of control, the first reference voltage VDD_G, reset signal K (5), control signal Q (1), control signal Q (3), control signal Q (5), control signal Q (7), gate drive signal G (1), gate drive signal G (3), gate drive signal G (5) and gate drive signal G (7).
As earlier mentioned, touch the enable signal TP_EN of control in order to indicate whether touch-control circuit is scanning, and when touch-control circuit is when scanning, touch the enable signal TP_EN of control and be adjusted to noble potential. As shown in Figure 3, before the enable signal TP_EN of tactile control is adjusted to noble potential, the first reference voltage VDD_G can be first adjusted to low potential. Now, control signal Q (5) can be adjusted to low potential by related, and gate drive signal G (5) is not therefore driven high noble potential, thus can reduce the time that transistor T21 is subject to bias pressure (stress). In addition, other input and output signals of shift scratch circuit 10_5 are all pulled low to low potential. Therefore, when touch-control circuit is during carrying out scanning, each node potential in shift scratch circuit 10_5 is roughly upper maintains current potential originally. Wherein, when the enable signal TP_EN of tactile control is high voltage level, or say when each input and output signal of shift scratch circuit 10_5 is adjusted to low potential, the current potential of reset signal K (5) roughly on be maintained definite value. In one embodiment, now each input and output signal is adjusted to the 2nd reference voltage VSS, but not as limit.
And when touch-control circuit terminates scanning, touch the enable signal TP_EN of control and be pulled low to low potential by noble potential, and the first reference voltage VDD_G is adjusted to noble potential by low potential. As shown in Figure 3, now reset signal K (5) is adjusted to noble potential again, and makes control signal Q (5) be adjusted to noble potential relatedly, and therefore gate drive signal G (5) is also adjusted to noble potential.
In the circuit of reality, the current potential of reset signal K (5) likely reduces gradually because of the electric leakage problem of circuit. Therefore, the speed that can decline because of circuit electric leakage to control the current potential of reset signal K (5) according to the capacitance size of actual required adjustment electric capacity C1 in practice. Please with reference to Fig. 4 to be described, Fig. 4 is the reset signal that illustrates according to one embodiment of the invention time diagram relative to the electric capacity C1 of different capacitance. Illustrating in the diagram when the capacitance that electric capacity C1 has changes, reset signal K (5) is relative to the change of the electric capacity of electric capacity C1. As shown in Figure 3, Figure 4, during touch-control circuit scans, also it is exactly during the enable signal TP_EN of tactile control is high levle, although reset signal K (5) roughly on remain unchanged, but the impact due to circuit electric leakage, the current potential of reset signal K (5) is still along with the time declines in the past gradually. And the electric capacity C1 corresponding to different capacitance, when the capacitance of electric capacity C1 is more big, the current potential of reset signal K (5) declines more slow. Wherein, the capacitance of electric capacity C1 is the curve that 0 skin farad (picofarad, pF) is formed, and namely corresponding aforesaid shift register device 10_5 does not have the embodiment of electric capacity C1.
Comprehensive the above, disclosed herein a kind of shift scratch circuit, the specific node of at least one in shift scratch circuit is carried out discharge and recharge by a switch circuit in good time, when In-cell touch display panel draws multiple input signal or the output signal of low shift scratch circuit in response to touch-control circuit to carry out touching control scanning, the specific node in shift scratch circuit also can be allowed to maintain desired voltage. Thus allow shift scratch circuit the enable touch-control circuit of In-cell touch display panel this during in, avoid the current potential of each node in shift scratch circuit to have unsuitable change. And make shift scratch circuit during this period later can normal operation again fast, and export correct gate drive signal.
Although the present invention with aforesaid embodiment disclose as above, so itself and be not used to limit the present invention. Without departing from the spirit and scope of the present invention, change for it and retouching, all belong to the scope of patent protection of the present invention. The protection domain defined about the present invention please refer to right.
Claims (10)
1. a shift scratch circuit, it is characterised in that, comprise:
One switch circuit, comprises:
One first crystal pipe, adjusts current potential to one first reference voltage of a control signal according to the current potential of the conducting signal on the grid of this first crystal pipe;
One two-transistor, is electrically connected to the grid of this first crystal pipe, draws high the current potential of this conducting signal according to an initiating signal; And
One third transistor, is electrically connected to the grid of this first crystal pipe, resets current potential to the 2nd reference voltage of this conducting signal according to a reset signal;
One pull-up circuit, is electrically connected to this first crystal pipe, and the current potential that outputs signal is adjusted to the current potential of a clock signal according to this control signal;
Puller circuit once, is electrically connected to this pull-up circuit, according to a pulldown signal and this control signal, the current potential of this output signal is adjusted to the 2nd reference voltage; And
One pincers circuit, is electrically connected to this pull-up circuit, according to a pincers signal, the current potential of the current potential of this control signal and this output signal is adjusted to the 2nd reference voltage.
2. shift scratch circuit as claimed in claim 1, it is characterised in that, more comprise an electric capacity, one end of this electric capacity is electrically connected with the grid of this first crystal pipe, and the other end of this electric capacity is electrically connected with this first reference voltage or the 2nd reference voltage.
3. shift scratch circuit as claimed in claim 1, it is characterized in that, more comprising an electric capacity, one end of this electric capacity is electrically connected with the grid of this first crystal pipe, the other end of this electric capacity is electrically connected to this pull-up circuit, to form a coupling path between this control signal and this conducting signal.
4. shift scratch circuit as claimed in claim 1, it is characterised in that, the conduction impedance of this third transistor is greater than the conduction impedance of this first crystal pipe and the conduction impedance of this two-transistor.
5. shift scratch circuit as claimed in claim 1, it is characterised in that, more comprise one the 4th transistor, it is electrically connected to this pull-up circuit, the foundation one enable signal of tactile control resets the current potential of this output signal to the 2nd reference voltage.
6. shift scratch circuit as claimed in claim 5, it is characterised in that, the conduction impedance of the 4th transistor is greater than the conduction impedance of this first crystal pipe and the conduction impedance of this two-transistor.
7. shift scratch circuit as claimed in claim 1, it is characterised in that, more comprise one the 5th transistor, it is electrically connected to this pull-up circuit, touch the control heavy current potential to this control signal of enable signal to the 2nd reference voltage according to one.
8. shift scratch circuit as claimed in claim 7, it is characterised in that, the conduction impedance of the 5th transistor is greater than the conduction impedance of this first crystal pipe and the conduction impedance of this two-transistor.
9. shift scratch circuit as according to any one of claim 1 to 8, it is characterised in that, the conduction impedance of this first crystal pipe is equal with the conduction impedance essence of this two-transistor.
10. shift scratch circuit as according to any one of claim 1 to 8, it is characterised in that, this circuit makes with amorphous silicon technology, polysilicon process or low temperature silicon substrate process.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104136684A TWI562041B (en) | 2015-11-06 | 2015-11-06 | Shift register circuit |
| TW104136684 | 2015-11-06 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105630242A true CN105630242A (en) | 2016-06-01 |
| CN105630242B CN105630242B (en) | 2018-11-02 |
Family
ID=56045259
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201511019032.7A Expired - Fee Related CN105630242B (en) | 2015-11-06 | 2015-12-30 | shift register circuit |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN105630242B (en) |
| TW (1) | TWI562041B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106297888A (en) * | 2016-07-06 | 2017-01-04 | 友达光电股份有限公司 | Shift temporary storage device |
| TWI602168B (en) * | 2016-11-28 | 2017-10-11 | 友達光電股份有限公司 | Shift register and timimg control method thereof |
| CN107680552A (en) * | 2017-09-30 | 2018-02-09 | 友达光电股份有限公司 | Shift register circuit and operation method thereof |
| CN109147637A (en) * | 2017-06-15 | 2019-01-04 | 乐金显示有限公司 | Shift register and display device including it |
| CN109754749A (en) * | 2017-11-08 | 2019-05-14 | 乐金显示有限公司 | Gate driving circuit and display device including the gate driving circuit |
| TWI690837B (en) * | 2019-01-07 | 2020-04-11 | 友達光電股份有限公司 | Shift register |
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| CN103198783B (en) * | 2013-04-01 | 2015-04-29 | 京东方科技集团股份有限公司 | Shifting register unit, shifting register and display device |
| TWI473059B (en) * | 2013-05-28 | 2015-02-11 | Au Optronics Corp | Shift register circuit |
| CN104217763B (en) * | 2014-08-28 | 2018-01-02 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit, display device |
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| US20120051494A1 (en) * | 2010-09-01 | 2012-03-01 | Au Optronics Corp. | Shift register circuit |
| CN103943055A (en) * | 2014-03-27 | 2014-07-23 | 京东方科技集团股份有限公司 | Gate drive circuit and method and display device |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106297888A (en) * | 2016-07-06 | 2017-01-04 | 友达光电股份有限公司 | Shift temporary storage device |
| CN106297888B (en) * | 2016-07-06 | 2019-11-08 | 友达光电股份有限公司 | Shift temporary storage device |
| TWI602168B (en) * | 2016-11-28 | 2017-10-11 | 友達光電股份有限公司 | Shift register and timimg control method thereof |
| CN109147637A (en) * | 2017-06-15 | 2019-01-04 | 乐金显示有限公司 | Shift register and display device including it |
| CN107680552A (en) * | 2017-09-30 | 2018-02-09 | 友达光电股份有限公司 | Shift register circuit and operation method thereof |
| CN107680552B (en) * | 2017-09-30 | 2020-08-04 | 友达光电股份有限公司 | Shift register circuit and operation method thereof |
| CN109754749A (en) * | 2017-11-08 | 2019-05-14 | 乐金显示有限公司 | Gate driving circuit and display device including the gate driving circuit |
| TWI690837B (en) * | 2019-01-07 | 2020-04-11 | 友達光電股份有限公司 | Shift register |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105630242B (en) | 2018-11-02 |
| TW201716947A (en) | 2017-05-16 |
| TWI562041B (en) | 2016-12-11 |
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