TW201716947A - Shift register circuit - Google Patents
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- TW201716947A TW201716947A TW104136684A TW104136684A TW201716947A TW 201716947 A TW201716947 A TW 201716947A TW 104136684 A TW104136684 A TW 104136684A TW 104136684 A TW104136684 A TW 104136684A TW 201716947 A TW201716947 A TW 201716947A
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- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
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Abstract
Description
本發明係關於一種移位暫存電路，特別是一種應用於內嵌式觸控面板的移位暫存電路。The invention relates to a shift temporary storage circuit, in particular to a shift temporary storage circuit applied to an embedded touch panel.
在內嵌式（in-cell）觸控面板中，內嵌式觸控面板在同一塊基板上設置有閘極驅動電路以及觸控電路，且閘極驅動信號線與觸控信號線彼此可能會很接近，因此閘極驅動信號與觸控信號會彼此干擾。由於閘極驅動信號的強度較強，經由電容耦合效應，閘極驅動信號往往會造成雜訊而干擾觸控信號，而降低了觸控操作的訊雜比（signal to noise ratio, SNR）。In an in-cell touch panel, the in-cell touch panel is provided with a gate driving circuit and a touch circuit on the same substrate, and the gate driving signal line and the touch signal line may be mutually Very close, so the gate drive signal and the touch signal will interfere with each other. Due to the strong intensity of the gate drive signal, the gate drive signal often causes noise and interferes with the touch signal through the capacitive coupling effect, and reduces the signal to noise ratio (SNR) of the touch operation.
在傳統的作法中，為了避免觸控信號被閘極驅動信號所干擾，一般會在致能觸控電路時，將移位暫存電路中的幾個特定信號拉低至低準位，以避免閘極驅動電路與觸控電路同時運作而彼此干擾。但於此同時，如何讓閘極驅動電路於觸控電路被致能的此期間過後能快速地重新正常運作，則成為工程師在設計移位暫存電路時的一大課題。In the conventional method, in order to prevent the touch signal from being interfered by the gate driving signal, generally, when the touch circuit is enabled, several specific signals in the shift register circuit are pulled down to a low level to avoid The gate driving circuit and the touch circuit operate simultaneously and interfere with each other. However, at the same time, how to make the gate driving circuit can resume normal operation after the touch circuit is enabled is a major issue for engineers in designing the shift register circuit.
本發明在於提供一種移位暫存電路，讓移位暫存電路在觸控電路被致能的此期間過後，能快速地重新正常運作。The present invention provides a shift temporary storage circuit that allows the shift temporary storage circuit to quickly resume normal operation after the touch circuit is enabled.
本發明所揭露的一種移位暫存電路具有開關電路、上拉電路、下拉電路與箝制電路。上拉電路電性連接至開關電路、下拉電路與箝制電路。開關電路包含第一電晶體、第二電晶體與第三電晶體。第一電晶體的閘極電性連接至第二電晶體與第三電晶體。第一電晶體依據第一電晶體的閘極上的導通信號的電位調整控制信號的電位至第一參考電壓。第二電晶體依據啟動信號拉升導通信號的電位。第三電晶體依據重置信號重置導通信號的電位至第二參考電壓。上拉電路依據控制信號將輸出信號 的電位調整為時脈信號的電位。下拉電路依據下拉信號與控制信號將輸出信號的電位調整至第二參考電壓。箝制電路依據箝制信號將控制信號的電位與輸出信號的電位調整至第二參考電壓。A shift temporary storage circuit disclosed in the present invention has a switch circuit, a pull-up circuit, a pull-down circuit and a clamp circuit. The pull-up circuit is electrically connected to the switch circuit, the pull-down circuit, and the clamp circuit. The switching circuit includes a first transistor, a second transistor, and a third transistor. The gate of the first transistor is electrically connected to the second transistor and the third transistor. The first transistor adjusts the potential of the control signal to the first reference voltage according to the potential of the on signal on the gate of the first transistor. The second transistor pulls up the potential of the on signal according to the enable signal. The third transistor resets the potential of the on signal to the second reference voltage according to the reset signal. The pull-up circuit adjusts the potential of the output signal to the potential of the clock signal in accordance with the control signal. The pull-down circuit adjusts the potential of the output signal to the second reference voltage according to the pull-down signal and the control signal. The clamping circuit adjusts the potential of the control signal and the potential of the output signal to the second reference voltage according to the clamp signal.
綜合以上所述，本發明揭露了一種移位暫存電路，藉由一開關電路適時地對移位暫存電路中的至少一個特定節點進行充放電，以在拉低移位暫存電路的多個信號時也能讓所述的特定節點維持所欲的電壓，從而讓移位暫存電路在觸控電路被致能的此期間過後，能快速地重新正常運作。In summary, the present invention discloses a shift temporary storage circuit in which a switching circuit timely charges and discharges at least one specific node in the shift temporary storage circuit to lower the shift temporary storage circuit. The signal also allows the particular node to maintain the desired voltage, thereby allowing the shift register circuit to quickly resume normal operation after the touch circuit is enabled.
以上之關於本揭露內容之說明及以下之實施方式之說明係用以示範與解釋本發明之精神與原理，並且提供本發明之專利申請範圍更進一步之解釋。The above description of the disclosure and the following description of the embodiments of the present invention are intended to illustrate and explain the spirit and principles of the invention, and to provide further explanation of the scope of the invention.
以下在實施方式中詳細敘述本發明之詳細特徵以及優點，其內容足以使任何熟習相關技藝者了解本發明之技術內容並據以實施，且根據本說明書所揭露之內容、申請專利範圍及圖式，任何熟習相關技藝者可輕易地理解本發明相關之目的及優點。以下之實施例係進一步詳細說明本發明之觀點，但非以任何觀點限制本發明之範疇。The detailed features and advantages of the present invention are set forth in the Detailed Description of the Detailed Description of the <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; The objects and advantages associated with the present invention can be readily understood by those skilled in the art. The following examples are intended to describe the present invention in further detail, but are not intended to limit the scope of the invention.
請參照圖1，圖1係為根據本發明一實施例所繪示之閘極驅動電路的功能方塊示意圖。如圖1所示，閘極驅動電路1包含移位暫存電路10_1~10_10。在此實施例中，閘極驅動電路1係採用一傳三的結構，因此移位暫存電路10_1、10_3、10_5、10_7、10_9彼此依序串接，而移位暫存電路10_2、10_4、10_6、10_8、10_10彼此依序串接。移位暫存電路10_1依據時脈信號CK(1)與啟動信號ST(1)產生閘極驅動信號G(1)，而移位暫存電路10_3依據時脈信號CK(3)與閘極驅動信號G(1)產生閘極驅動信號G(3)。至於移位暫存電路10_2、10_4~10_10的相關作動當可依圖1與上述內容類推，於此則不再贅述。移位暫存電路10_1~10_10係以非晶矽(Amorphous Silicon, A-Si)製程、多晶矽（Poly-Silicon）製程或低溫矽基板（low-temperature silicon substrate）製程製成。後續係以此為示範例進行說明，然實際上閘極驅動電路1也可採用一傳二的結構，而並不以此為限。Please refer to FIG. 1. FIG. 1 is a functional block diagram of a gate driving circuit according to an embodiment of the invention. As shown in FIG. 1, the gate driving circuit 1 includes shift register circuits 10_1~10_10. In this embodiment, the gate driving circuit 1 adopts a structure of three transmissions, so the shift register circuits 10_1, 10_3, 10_5, 10_7, and 10_9 are serially connected to each other, and the shift register circuits 10_2, 10_4, 10_6, 10_8, and 10_10 are serially connected to each other. The shift register circuit 10_1 generates a gate drive signal G(1) according to the clock signal CK(1) and the start signal ST(1), and the shift register circuit 10_3 is driven according to the clock signal CK(3) and the gate. Signal G(1) generates gate drive signal G(3). The related operations of the shift register circuits 10_2, 10_4~10_10 can be analogized with the above contents according to FIG. 1, and will not be described herein. The shift register circuits 10_1~10_10 are fabricated by an amorphous silicon (A-Si) process, a poly-Silicon process, or a low-temperature silicon substrate process. The following is a description of the example. However, the gate driving circuit 1 can also adopt a structure of one transmission, and is not limited thereto.
請接著參照圖2，圖2係為根據本發明圖1所繪示之其中一個移位暫存電路的電路示意圖。在圖2所對應的實施例中係以移位暫存電路10_5為例進行介紹，然移位暫存電路10_1~10_4、10_6~10_10具有之結構及作動與移位暫存電路10_5相仿，所屬技術領域具有通常知識者當可從本說明書類推而得。移位暫存電路10_5包含開關電路102、下拉電路104、上拉電路106與箝制電路108。上拉電路106電性連接至開關電路102。下拉電路104電性連接至上拉電路106。箝制電路108電性連接至上拉電路106。移位暫存電路10_5係依據時脈信號CK(5)、啟動信號ST(3)、啟動信號ST(5)、啟動信號ST(9)、閘極驅動電壓G(3)、下拉信號LC1、下拉信號LC2、第一參考電壓VDD_G與第二參考電壓VSS產生閘極驅動信號G(5)。其中，移位暫存電路10_5中的啟動信號ST(3)與啟動信號ST(9)可分別被置換為閘極驅動信號G(3)與閘極驅動信號G(9)，且移位暫存電路10_5中的閘極驅動信號G(3)亦可被置換為啟動信號ST(3)。Please refer to FIG. 2. FIG. 2 is a schematic circuit diagram of one of the shift register circuits according to FIG. 1 of the present invention. In the embodiment corresponding to FIG. 2, the shift temporary storage circuit 10_5 is taken as an example, and the shift temporary storage circuits 10_1~10_4, 10_6~10_10 have the same structure and actuation as the shift temporary storage circuit 10_5. Those of ordinary skill in the art will be able to derive from this specification. The shift register circuit 10_5 includes a switch circuit 102, a pull-down circuit 104, a pull-up circuit 106, and a clamp circuit 108. The pull-up circuit 106 is electrically connected to the switch circuit 102. The pull-down circuit 104 is electrically connected to the pull-up circuit 106. The clamping circuit 108 is electrically connected to the pull-up circuit 106. The shift register circuit 10_5 is based on the clock signal CK(5), the start signal ST(3), the start signal ST(5), the start signal ST(9), the gate drive voltage G(3), and the pull-down signal LC1. The pull-down signal LC2, the first reference voltage VDD_G, and the second reference voltage VSS generate a gate drive signal G(5). The start signal ST(3) and the enable signal ST(9) in the shift temporary storage circuit 10_5 can be replaced with the gate drive signal G(3) and the gate drive signal G(9), respectively, and the shift is temporarily suspended. The gate drive signal G(3) in the memory circuit 10_5 can also be replaced with the enable signal ST(3).
下拉電路104依據下拉信號LC1、LC2與控制信號Q(5)，將閘極驅動信號G(5)的電位調整至第二參考電壓VSS。在此實施例中，當下拉信號LC1或下拉信號LC2當中的至少中一個為高電位的時候，閘極驅動信號G(5)的電位與控制信號Q(5)的電位被調整至第二參考電壓VSS。但在另一實施例中，當下拉信號LC1或下拉信號LC2當中的至少中一個為低電位的時候，閘極驅動信號G(5)的電位與控制信號Q(5)的電位被調整至第二參考電壓VSS。在此並不限制下拉電路104係在下拉信號LC1、LC2為何種電壓準位時將閘極驅動信號的電位調整至第二參考電壓VSSThe pull-down circuit 104 adjusts the potential of the gate drive signal G(5) to the second reference voltage VSS according to the pull-down signals LC1, LC2 and the control signal Q(5). In this embodiment, when at least one of the pull-down signal LC1 or the pull-down signal LC2 is at a high potential, the potential of the gate drive signal G(5) and the potential of the control signal Q(5) are adjusted to the second reference. Voltage VSS. However, in another embodiment, when at least one of the pull-down signal LC1 or the pull-down signal LC2 is at a low potential, the potential of the gate drive signal G(5) and the potential of the control signal Q(5) are adjusted to the first Two reference voltage VSS. The pull-down circuit 104 is not limited to adjust the potential of the gate driving signal to the second reference voltage VSS when the pull-down signals LC1 and LC2 are at the voltage level.
上拉電路106依據控制信號Q(5)將閘極驅動信號G(5)的電位調整為時脈信號CK(5)的電位。在此實施例中，當控制信號Q(5)為高電位時，電晶體T21被導通，閘極驅動信號G(5)的電位被調整為時脈信號CK(5)的電位。The pull-up circuit 106 adjusts the potential of the gate drive signal G(5) to the potential of the clock signal CK(5) in accordance with the control signal Q(5). In this embodiment, when the control signal Q(5) is at a high potential, the transistor T21 is turned on, and the potential of the gate drive signal G(5) is adjusted to the potential of the clock signal CK(5).
箝制電路108依據箝制信號將控制信號Q(5)的電位與閘極驅動信號G(5)的電位調整至第二參考電壓VSS。在此實施例中係以啟動信號ST(9)作為箝制信號，且當啟動信號ST(9)為高電位時，閘極驅動信號G(5)與控制信號Q(5)被調整至第二參考電壓VSS。The clamp circuit 108 adjusts the potential of the control signal Q(5) and the potential of the gate drive signal G(5) to the second reference voltage VSS in accordance with the clamp signal. In this embodiment, the start signal ST(9) is used as the clamp signal, and when the start signal ST(9) is high, the gate drive signal G(5) and the control signal Q(5) are adjusted to the second. Reference voltage VSS.
開關電路102係依據啟動信號與重置信號選擇性地調整控制信號Q(5)的電位至第一參考電壓VDD_G。在此實施例中，係以啟動信號ST(3)與啟動信號ST(5)作為啟動信號與重置信號，但實際上啟動信號ST(3)與啟動信號ST(5)可分別被置換為閘極驅動信號G(3)、G(5)，所屬技術領域具有通常知識者應可理解，於後續行文出現之啟動信號亦可視情況與對應的閘極驅動信號互換之。The switch circuit 102 selectively adjusts the potential of the control signal Q(5) to the first reference voltage VDD_G according to the enable signal and the reset signal. In this embodiment, the enable signal ST(3) and the enable signal ST(5) are used as the enable signal and the reset signal, but in fact, the enable signal ST(3) and the enable signal ST(5) can be replaced with The gate drive signals G(3), G(5), as known to those skilled in the art, should be understood, and the start signal appearing in the subsequent texts may be interchanged with the corresponding gate drive signals as appropriate.
開關電路102具有第一電晶體T11、第二電晶體T71、第三電晶體T72與電容C1。第一電晶體T11的第一端接收第一參考電壓VDD_G，第一電晶體T11的第二端電性連接至下拉電路104與上拉電路106。第一電晶體T11的控制端接收重置信號K(5)。第二電晶體T71的第一端接收閘極驅動信號G(3)。第二電晶體T71的第二端耦接至第一電晶體T11的控制端，第二電晶體T71的控制端接收啟動信號ST(3)。第三電晶體T72的接收重置信號K(5)，第三電晶體T72的第二端接收第二參考電壓VSS。第三電晶體T72的控制端接收啟動信號ST(5)。電容C1的第一端接收第二參考電壓VSS，電容C1的第二端接收重置信號K(5)。The switch circuit 102 has a first transistor T11, a second transistor T71, a third transistor T72, and a capacitor C1. The first end of the first transistor T11 receives the first reference voltage VDD_G, and the second end of the first transistor T11 is electrically connected to the pull-down circuit 104 and the pull-up circuit 106. The control terminal of the first transistor T11 receives the reset signal K(5). The first end of the second transistor T71 receives the gate drive signal G(3). The second end of the second transistor T71 is coupled to the control end of the first transistor T11, and the control end of the second transistor T71 receives the enable signal ST(3). The third transistor T72 receives the reset signal K(5), and the second terminal of the third transistor T72 receives the second reference voltage VSS. The control terminal of the third transistor T72 receives the enable signal ST(5). The first end of the capacitor C1 receives the second reference voltage VSS, and the second end of the capacitor C1 receives the reset signal K(5).
於一實施例中，第一電晶體T11、第二電晶體T71與第三電晶體T72係為N型金屬氧化物半導體場效電晶體（Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET）。在此實施例中，第三電晶體T72的導通阻抗rds_ON3 大於第一電晶體T11的導通阻抗rds_ON1 ，且第三電晶體T72的導通阻抗rds_ON3 大於第二電晶體T71的導通阻抗rds_ON2 。於實務上，第一電晶體T11的導通阻抗rds_ON1 與第二電晶體T71的導通阻抗rds_ON2 被設計為實質上相等，但不以此為限。其中，導通阻抗rds_ON 係關聯於載子遷移率（carrier mobility）、金屬氧化物半導體場效電晶體的閘極寬度、金屬氧化物半導體場效電晶體的閘極長度，以及金氧半場效電晶體之閘極氧化層的單位電容大小。In one embodiment, the first transistor T11, the second transistor T71, and the third transistor T72 are Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). ON resistance r ds_ON1 embodiment, the third transistor ON resistance r ds_ON3 T72 is greater than the first transistor T11 in this embodiment, and the third transistor ON resistance r ds_ON3 T72 is greater than the second transistor T71 in the on-resistance r ds_ON2 . In practice, the on-resistance r ds_ON1 of the first transistor T11 and the on-resistance r ds_ON2 of the second transistor T71 are designed to be substantially equal, but not limited thereto . Wherein, the on-resistance r ds_ON is related to carrier mobility, the gate width of the metal oxide semiconductor field effect transistor, the gate length of the metal oxide semiconductor field effect transistor, and the gold oxide half field effect current. The unit capacitance of the gate oxide of the crystal.
於實務上，電容C1的第一端亦可接收第一參考電壓VDD_G，以於第一參考電壓VDD_G及重置信號K(5)間形成一耦合路徑。或者電容C1的第一端亦可耦接至上拉電路106，以於控制信號Q(5)及重置信號K(5)間形成一耦合路徑。須注意的是，在另一種的實施例中，開關電路102並不具有電容C1。在一實施例中，第一參考電壓VDD_G係大於第二參考電壓VSS，但並不以此為限。In practice, the first end of the capacitor C1 can also receive the first reference voltage VDD_G to form a coupling path between the first reference voltage VDD_G and the reset signal K(5). Alternatively, the first end of the capacitor C1 may be coupled to the pull-up circuit 106 to form a coupling path between the control signal Q(5) and the reset signal K(5). It should be noted that in another embodiment, the switch circuit 102 does not have a capacitor C1. In an embodiment, the first reference voltage VDD_G is greater than the second reference voltage VSS, but is not limited thereto.
開關電路102係用以選擇性調整控制信號Q(5)的電位，從而連動地調整閘極驅動信號G(5)的電位。於開關電路102中，第一電晶體T11依據第一電晶體T11的閘極上的重置信號K(5)的電位調整控制信號Q(5)的電位至第一參考電壓VDD_G。第二電晶體T71依據啟動信號ST(3)拉升重置信號K(5)的電位。第三電晶體T72依據重置信號ST(5)重置重置信號K(5)的電位至第二參考電壓VSS。The switch circuit 102 is for selectively adjusting the potential of the control signal Q(5) to adjust the potential of the gate drive signal G(5) in conjunction. In the switching circuit 102, the first transistor T11 adjusts the potential of the control signal Q(5) to the first reference voltage VDD_G according to the potential of the reset signal K(5) on the gate of the first transistor T11. The second transistor T71 pulls up the potential of the reset signal K(5) in accordance with the enable signal ST(3). The third transistor T72 resets the potential of the reset signal K(5) to the second reference voltage VSS in accordance with the reset signal ST(5).
此外，如圖2所繪示地，開關電路102還具有電晶體T73或電晶體T74。電晶體T73的第一端接收第二參考電壓VSS，電晶體T73的第二端接收控制信號Q(5)，且電晶體T73的控制端接收觸控致能信號TP_EN。電晶體T74的第一端接收第二參考電壓VSS，電晶體T74的第二端接收閘極驅動信號G(5)，且電晶體T74的控制端接收觸控致能信號TP_EN。在此實施例中，當觸控致能信號TP_EN為高電位時，閘極驅動信號G(5)與控制信號Q(5)被調整至第二參考電壓VSS。其中，觸控致能信號TP_EN係用以指示觸控電路是否在進行掃描，以令移位暫存電路10_5進行相應的作動。In addition, as shown in FIG. 2, the switch circuit 102 further has a transistor T73 or a transistor T74. The first end of the transistor T73 receives the second reference voltage VSS, the second end of the transistor T73 receives the control signal Q(5), and the control end of the transistor T73 receives the touch enable signal TP_EN. The first end of the transistor T74 receives the second reference voltage VSS, the second end of the transistor T74 receives the gate drive signal G(5), and the control end of the transistor T74 receives the touch enable signal TP_EN. In this embodiment, when the touch enable signal TP_EN is at a high potential, the gate drive signal G(5) and the control signal Q(5) are adjusted to the second reference voltage VSS. The touch enable signal TP_EN is used to indicate whether the touch circuit is scanning, so that the shift register circuit 10_5 performs corresponding operations.
請參照圖3，圖3係為根據本發明圖2所繪示之移位暫存電路的時序示意圖。圖3中係繪示有觸控致能信號TP_EN、第一參考電壓VDD_G、重置信號K(5)、控制信號Q(1)、控制信號Q(3)、控制信號Q(5) 、控制信號Q(7)、閘極驅動信號G(1)、閘極驅動信號G(3)、閘極驅動信號G(5) 與閘極驅動信號G(7)的相對時序。Please refer to FIG. 3. FIG. 3 is a timing diagram of the shift register circuit illustrated in FIG. 2 according to the present invention. 3 shows a touch enable signal TP_EN, a first reference voltage VDD_G, a reset signal K (5), a control signal Q (1), a control signal Q (3), a control signal Q (5), control The relative timing of the signal Q (7), the gate drive signal G (1), the gate drive signal G (3), the gate drive signal G (5) and the gate drive signal G (7).
如前述地，觸控致能信號TP_EN係用以指示觸控電路是否在進行掃描，而當觸控電路在進行掃描時，觸控致能信號TP_EN係被調整為高電位。如圖3所示，在觸控致能信號TP_EN係被調整為高電位前，第一參考電壓VDD_G會被先調整至低電位。此時，控制信號Q(5)會被連帶地被調整至低電位，閘極驅動信號G(5)因此未被拉高到高電位，因而可以減少電晶體T21受到偏壓壓力(stress)的時間。此外，移位暫存電路10_5的其他輸入輸出信號都被拉低至低電位。因此，當觸控電路在進行掃描的期間，移位暫存電路10_5中的各節點電位大致上維持原本的電位。其中，當觸控致能信號TP_EN為高電壓準位時，或者說當移位暫存電路10_5的各輸入輸出信號被調整至低電位時，重置信號K(5)的電位大致上維持為定值。在一實施例中，此時各輸入輸出信號係被調整至第二參考電壓VSS，但並不以此為限。As described above, the touch enable signal TP_EN is used to indicate whether the touch circuit is scanning, and when the touch circuit is scanning, the touch enable signal TP_EN is adjusted to a high potential. As shown in FIG. 3, before the touch enable signal TP_EN is adjusted to a high potential, the first reference voltage VDD_G is first adjusted to a low potential. At this time, the control signal Q(5) is collectively adjusted to a low potential, and the gate drive signal G(5) is thus not pulled high to a high potential, thereby reducing the stress of the transistor T21 by the bias voltage. time. In addition, other input and output signals of the shift register circuit 10_5 are pulled low to a low potential. Therefore, during the scanning of the touch circuit, the potential of each node in the shift register circuit 10_5 substantially maintains the original potential. Wherein, when the touch enable signal TP_EN is at a high voltage level, or when the input and output signals of the shift register circuit 10_5 are adjusted to a low potential, the potential of the reset signal K(5) is substantially maintained as Value. In an embodiment, each input and output signal is adjusted to the second reference voltage VSS, but is not limited thereto.
而當觸控電路結束掃描時，觸控致能信號TP_EN由高電位被拉低至低電位，且第一參考電壓VDD_G由低電位被調整至高電位。如圖3所示，此時重置信號K(5)重新被調整至高電位，並連帶地使控制信號Q(5)被調整至高電位，且閘極驅動信號G(5)也因此被調整至高電位。When the touch circuit ends the scanning, the touch enable signal TP_EN is pulled low to a low potential, and the first reference voltage VDD_G is adjusted to a high potential by the low potential. As shown in FIG. 3, at this time, the reset signal K(5) is again adjusted to a high potential, and the control signal Q(5) is adjusted to a high potential, and the gate drive signal G(5) is thus adjusted to be high. Potential.
在實際的電路中，重置信號K(5)的電位有可能因為電路的漏電問題而逐漸降低。因此，於實務上會依據實際所需調整電容C1的電容值大小以控制重置信號K(5)的電位因為電路漏電而下降的速度。請一併參照圖4以進行說明，圖4係為根據本發明一實施例所繪示之重置信號相對於不同電容值的電容C1的時序示意圖。在圖4中係繪示有當電容C1所具有的電容値改變時，重置信號K(5)相對於電容C1的電容之變化。如圖3、圖4所示，在觸控電路進行掃描期間，也就是觸控致能信號TP_EN為高準位的期間，雖然重置信號K(5)大致上維持不變，但由於電路漏電的影響，重置信號K(5)的電位還是隨著時間過去而逐漸下降。而對應於不同電容值的電容C1，當電容C1的電容值越大時，重置信號K(5)的電位下降地越慢。其中，電容C1的電容値為0皮法拉（picofarad，pF）所形成的曲線，即對應前述之移位暫存器10_5不具有電容C1的實施例。In an actual circuit, the potential of the reset signal K(5) may gradually decrease due to a leakage problem of the circuit. Therefore, in practice, the capacitance value of the capacitor C1 is adjusted according to actual needs to control the speed at which the potential of the reset signal K(5) drops due to leakage of the circuit. Please refer to FIG. 4 for illustration. FIG. 4 is a timing diagram of the capacitor C1 of the reset signal with respect to different capacitance values according to an embodiment of the invention. FIG. 4 shows a change in the capacitance of the reset signal K(5) relative to the capacitor C1 when the capacitance 値 of the capacitor C1 changes. As shown in FIG. 3 and FIG. 4, during the scanning process of the touch circuit, that is, during the period in which the touch enable signal TP_EN is at a high level, although the reset signal K(5) is substantially maintained, the circuit leakage occurs. The effect of the reset signal K(5) is gradually decreasing as time passes. On the other hand, for the capacitor C1 corresponding to different capacitance values, when the capacitance value of the capacitor C1 is larger, the potential of the reset signal K(5) drops more slowly. The capacitance 値 of the capacitor C1 is a curve formed by a picofarad (pF), that is, an embodiment in which the shift register 10_5 does not have the capacitor C1.
綜合以上所述，本發明揭露了一種移位暫存電路，藉由一開關電路適時地對移位暫存電路中的至少一個特定節點進行充放電，以在內嵌式觸控顯示面板為了因應觸控電路進行觸控掃描而拉低移位暫存電路的多個輸入信號或輸出信號時，也能讓移位暫存電路中的特定節點維持所欲的電壓。從而讓移位暫存電路在內嵌式觸控顯示面板致能觸控電路的此期間中，避免移位暫存電路中的各節點之電位有不適當的變化。而令移位暫存電路在此期間過後能快速地重新正常運作，並輸出正確的閘極驅動信號。In summary, the present invention discloses a shift temporary storage circuit in which a switch circuit timely and simultaneously charges and discharges at least one specific node in the shift register circuit to respond to the in-cell touch display panel. When the touch circuit performs touch scanning and pulls down multiple input signals or output signals of the shift register circuit, the specific node in the shift register circuit can also maintain the desired voltage. Therefore, in the period in which the shift register circuit enables the touch circuit in the in-cell touch display panel, the potential of each node in the shift register circuit is prevented from being inappropriately changed. The shift register circuit can quickly resume normal operation after this period and output the correct gate drive signal.
雖然本發明以前述之實施例揭露如上，然其並非用以限定本發明。在不脫離本發明之精神和範圍內，所為之更動與潤飾，均屬本發明之專利保護範圍。關於本發明所界定之保護範圍請參考所附之申請專利範圍。Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.
1‧‧‧閘極驅動電路
10_1~10_10‧‧‧移位暫存電路
102‧‧‧開關電路
104‧‧‧下拉電路
106‧‧‧上拉電路
108‧‧‧箝制電路
C1、C2‧‧‧電容
CK(1)~CK(10)‧‧‧時脈信號
G(1)~G(10)‧‧‧閘極驅動信號
K(5)‧‧‧重置信號
LC1、LC2‧‧‧下拉信號
Q(1)、Q(3)、Q(5)、Q(7)‧‧‧控制信號
ST(1)、ST(3)、ST(5)、ST(9)‧‧‧啟動信號
T11~T74‧‧‧電晶體
TP_EN‧‧‧觸控致能信號
VDD_G‧‧‧第一參考電壓
VSS‧‧‧第二參考電壓1‧‧ ‧ gate drive circuit
10_1~10_10‧‧‧Shift temporary storage circuit
102‧‧‧Switch circuit
104‧‧‧ Pulldown circuit
106‧‧‧ Pull-up circuit
108‧‧‧Clamping circuit
C1, C2‧‧‧ capacitor
CK(1)~CK(10)‧‧‧ clock signal
G(1)~G(10)‧‧‧ gate drive signal
K(5)‧‧‧Reset signal
LC1, LC2‧‧‧ pulldown signal
Q(1), Q(3), Q(5), Q(7)‧‧‧ control signals
ST(1), ST(3), ST(5), ST(9)‧‧‧ start signal
T11~T74‧‧‧O crystal
TP_EN‧‧‧Touch enable signal
VDD_G‧‧‧ first reference voltage
VSS‧‧‧second reference voltage
圖1係為根據本發明一實施例所繪示之閘極驅動電路的功能方塊示意圖。 圖2係為根據本發明圖1所繪示之其中一個移位暫存電路的電路示意圖。 圖3係為根據本發明圖2所繪示之移位暫存電路的時序示意圖。 圖4係為根據本發明一實施例所繪示之重置信號相對於不同電容值的電容C1的時序示意圖。FIG. 1 is a functional block diagram of a gate driving circuit according to an embodiment of the invention. FIG. 2 is a schematic circuit diagram of one of the shift register circuits illustrated in FIG. 1 according to the present invention. FIG. 3 is a timing diagram of the shift register circuit illustrated in FIG. 2 according to the present invention. FIG. 4 is a timing diagram of a capacitor C1 of a reset signal with respect to different capacitance values according to an embodiment of the invention.
10_5‧‧‧移位暫存電路 10_5‧‧‧Shift register circuit
102‧‧‧開關電路 102‧‧‧Switch circuit
104‧‧‧下拉電路 104‧‧‧ Pulldown circuit
106‧‧‧上拉電路 106‧‧‧ Pull-up circuit
108‧‧‧箝制電路 108‧‧‧Clamping circuit
C1、C2‧‧‧電容 C1, C2‧‧‧ capacitor
CK(5)‧‧‧時脈信號 CK(5)‧‧‧ clock signal
G(3)、G(5)‧‧‧閘極驅動信號 G(3), G(5)‧‧‧ gate drive signals
K(5)‧‧‧重置信號 K(5)‧‧‧Reset signal
LC1、LC2‧‧‧下拉信號 LC1, LC2‧‧‧ pulldown signal
Q(5)‧‧‧控制信號 Q(5)‧‧‧ control signal
ST(3)、ST(5)、ST(9)‧‧‧啟動信號 ST(3), ST(5), ST(9)‧‧‧ start signal
T11~T74‧‧‧電晶體 T11~T74‧‧‧O crystal
TP_EN‧‧‧觸控致能信號 TP_EN‧‧‧Touch enable signal
VDD_G‧‧‧第一參考電壓 VDD_G‧‧‧ first reference voltage
VSS‧‧‧第二參考電壓 VSS‧‧‧second reference voltage
Claims (10)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104136684A TWI562041B (en) | 2015-11-06 | 2015-11-06 | Shift register circuit |
| CN201511019032.7A CN105630242B (en) | 2015-11-06 | 2015-12-30 | shift register circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104136684A TWI562041B (en) | 2015-11-06 | 2015-11-06 | Shift register circuit |
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| TWI562041B TWI562041B (en) | 2016-12-11 |
| TW201716947A true TW201716947A (en) | 2017-05-16 |
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| TW104136684A TWI562041B (en) | 2015-11-06 | 2015-11-06 | Shift register circuit |
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| CN (1) | CN105630242B (en) |
| TW (1) | TWI562041B (en) |
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| TWI578297B (en) * | 2016-07-06 | 2017-04-11 | 友達光電股份有限公司 | Shift register |
| TWI602168B (en) * | 2016-11-28 | 2017-10-11 | 友達光電股份有限公司 | Shift register and timimg control method thereof |
| KR102348667B1 (en) * | 2017-06-15 | 2022-01-06 | 엘지디스플레이 주식회사 | Shift register and display apparatus comprising the same |
| TWI631568B (en) * | 2017-09-30 | 2018-08-01 | 友達光電股份有限公司 | Shift register circuit and operation method thereof |
| KR102435943B1 (en) * | 2017-11-08 | 2022-08-23 | 엘지디스플레이 주식회사 | Gate driving circuit and display device comprising the same |
| TWI690837B (en) * | 2019-01-07 | 2020-04-11 | 友達光電股份有限公司 | Shift register |
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| KR101840185B1 (en) * | 2010-03-12 | 2018-03-20 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Method for driving circuit and method for driving display device |
| TWI413972B (en) * | 2010-09-01 | 2013-11-01 | Au Optronics Corp | Shift register circuit |
| CN103198783B (en) * | 2013-04-01 | 2015-04-29 | 京东方科技集团股份有限公司 | Shifting register unit, shifting register and display device |
| TWI473059B (en) * | 2013-05-28 | 2015-02-11 | Au Optronics Corp | Shift register circuit |
| CN103943055B (en) * | 2014-03-27 | 2016-05-11 | 京东方科技集团股份有限公司 | A kind of gate driver circuit and driving method thereof, display unit |
| CN103943083B (en) * | 2014-03-27 | 2017-02-15 | 京东方科技集团股份有限公司 | Gate drive circuit and method and display device |
| CN103996370B (en) * | 2014-05-30 | 2017-01-25 | 京东方科技集团股份有限公司 | Shifting register unit, grid drive circuit, display device and drive method |
| CN104217763B (en) * | 2014-08-28 | 2018-01-02 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit, display device |
| CN104900211B (en) * | 2015-06-30 | 2017-04-05 | 京东方科技集团股份有限公司 | A kind of gate driver circuit and its driving method, display device |
-
2015
- 2015-11-06 TW TW104136684A patent/TWI562041B/en not_active IP Right Cessation
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| TWI562041B (en) | 2016-12-11 |
| CN105630242B (en) | 2018-11-02 |
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