CN105630067A

CN105630067A - High-precision clock detecting method based on FPGA

Info

Publication number: CN105630067A
Application number: CN201510994485.5A
Authority: CN
Inventors: 于华; 安丰军; 李晓倩; 张家琦; 邹昕; 李政; 周立; 闫攀
Original assignee: BEIJING HAOHAN DATA INFORMATION TECHNOLOGY Co Ltd
Current assignee: BEIJING HAOHAN DATA INFORMATION TECHNOLOGY Co Ltd
Priority date: 2015-12-25
Filing date: 2015-12-25
Publication date: 2016-06-01

Abstract

The invention discloses a high-precision clock detecting method based on an FPGA and relates to a clock detection method. A plurality of clock signals at different phase positions are generated in one clock period, and generating time of measured signals are determined by judging the phase position relation between the measured signals and the clock signals. The time control precision of the 1588 function can be remarkably improved in the FPGA.

Description

A kind of high-precision clock detecting method based on FPGA

Technical field

The present invention relates to a kind of clock detection method, particularly relate to a kind of high-precision clock detecting method based on FPGA.

Background technology

1588 have other tolerance range of nanosecond, and information is short, it is few to occupy bandwidth resources, and comprehensive cost is low, reliability height, and therefore society is actively promoting development and the application of 1588 agreements at present.

At present, 1588 clock solutions based on FPGA mainly contain following feature:

1, local clock direct-detection event clock (message arrives or leaves) is directly used;

2, clock (Timer) adopts simple counter logic to safeguard;

The shortcoming of prior art:

1, the precision detecting clock time (message arrives or leaves) is low, directly accuracy during impact pair;

2, clock adopts simple technology device logic to safeguard, control accuracy is low, and error is big.

Summary of the invention

Because the above-mentioned defect of prior art, technical problem to be solved by this invention is to provide a kind of method of accuracy of detection improving event clock.

For achieving the above object, the present invention provides a kind of high-precision clock detecting method based on FPGA, the different clocksignal of multiple phase place is produced, by judging the phase relationship of measured signal and each clocksignal, it is determined that measured signal time of origin within a clock period;

System master clock produces n phase clock signal, and n is positive integer; The arrival of event clock, represents with a rising edge pulse; The clock input of d type flip flop is to the data input signal of clocksignal as d type flip flop; A system clock cycle is divided into n region by described clocksignal, then judges the generation area of event clock.

Preferably, the generation area of described judgement event clock carries out according to the following steps: when event clock signal arrives, latch is exported each phase clock signal by d type flip flop, exports 4 bits of encoded values; According to decoding mapping table, it is determined that event generation area.

The invention has the beneficial effects as follows: the present invention can significantly improve the time controling precision realizing 1588 functions in FPGA.

Accompanying drawing explanation

Fig. 1 is the structure block diagram of leggy of the present invention detection;

Fig. 2 is the schematic diagram of leggy detection.

Embodiment

Below in conjunction with drawings and Examples, the invention will be further described:

As depicted in figs. 1 and 2, a kind of high-precision clock detecting method based on FPGA, it is characterized in that: within a clock period, produce the different clocksignal of multiple phase place, by judging the phase relationship of measured signal and each clocksignal, it is determined that measured signal time of origin;

System master clock produces n phase clock signal, and n is positive integer. In the present embodiment, producing four phase clock signals, phase intervals is 90 degree. The arrival of time-event, represents (representing with the SOF signal rising edge signal of message, this signal is using the clocksignal as d type flip flop) with a rising edge pulse, it will be sent to the input end of clock of d type flip flop; The clocksignal of 4 phase places is as the data input signal of d type flip flop. The clocksignal of four phase places, is divided into 4 regions by a system clock cycle, and owing to the present invention can judge the generation area of event, so the accuracy of event detection will improve four times in theory.

The generation area of described judgement event clock carries out according to the following steps: when event clock signal arrives (SOF), latch is exported each phase clock signal by d type flip flop, exports 4 bits of encoded values to demoder; According to decoding mapping table, it is determined that event generation area. For setting forth the present embodiment, initialization system clock 125MHz (cycle 8ns), from table 1 it can be seen that under not considering the prerequisite that other factors affects, the judgement precision of event time of arrival can bring up to 2ns from 8ns.

Table 1. event decode time mapping table

Below the preferred embodiment of the present invention is described in detail. It is to be understood that the those of ordinary skill of this area just can make many modifications and variations according to the design of the present invention without the need to creative work. Therefore, the technical scheme that all technician in the art can be obtained by logical analysis, reasoning, or a limited experiment under this invention's idea on the basis of existing technology, all should by the determined protection domain of claim book.

Claims

1. the high-precision clock detecting method based on FPGA, it is characterised in that: within a clock period, produce the different clocksignal of multiple phase place, by judging the phase relationship of measured signal and each clocksignal, it is determined that measured signal time of origin;

2. a kind of high-precision clock detecting method based on FPGA as claimed in claim 1, is characterized in that:

The generation area of described judgement event clock carries out according to the following steps: when event clock signal arrives, latch is exported each phase clock signal by d type flip flop, exports 4 bits of encoded values; According to decoding mapping table, it is determined that event generation area.