CN103634263A - Continuous-phase frequency-shift keying digital demodulation device and demodulation method implemented by same - Google Patents
Continuous-phase frequency-shift keying digital demodulation device and demodulation method implemented by same Download PDFInfo
- Publication number
- CN103634263A CN103634263A CN201310667947.3A CN201310667947A CN103634263A CN 103634263 A CN103634263 A CN 103634263A CN 201310667947 A CN201310667947 A CN 201310667947A CN 103634263 A CN103634263 A CN 103634263A
- Authority
- CN
- China
- Prior art keywords
- unit
- high level
- count value
- clock
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
The invention relates to a digital demodulation device, in particular to a continuous-phase frequency-shift keying digital demodulation device and a demodulation method implemented by the same. The continuous-phase frequency-shift keying digital demodulation device comprises a comparator device and a field-programmable gate array device. An internal circuit of the field-programmable gate array device comprises a clock unit, a sampling unit, a counting unit, a buffer unit and a reconstruction unit, and the clock unit is connected with the sampling unit, the counting unit, the buffer unit and the reconstruction unit; the comparator device is connected with the sampling unit; the sampling unit is connected with the counting unit; the counting unit is connected with the buffer unit; the buffer unit is connected with the reconstruction unit. The continuous-phase frequency-shift keying digital demodulation device and the demodulation method have the advantages that the demodulation device has the simple circuit and is easy to implement, low in programmable logic resource consumption and high in signal adaptability; the demodulation method can replace the traditional continuous-phase frequency-shift keying digital demodulation method, so that shortcomings of complexity in implementation, high resource consumption and inadaptability to proximity of data rates and carrier frequencies can be overcome, and the like.
Description
Technical field
The present invention relates to digital demodulating apparatus, relate in particular to a kind of Continuous phase frequency shift keying digital demodulating apparatus and demodulation method thereof.
Background technology
Tradition Continuous phase frequency shift keying digital demodulation method generally has coherent demodulation method, frequency-discrimination method, zero passage detection method, matched filtering method etc.Wherein coherent demodulation method realizes complicated, and frequency-discrimination method, matched filtering method consumption of natural resource are many, and zero passage detection method can not adapt to data rate and the approaching situation of carrier frequency.
Summary of the invention
Deficiency in view of prior art exists, the invention provides a kind of Continuous phase frequency shift keying digital demodulating apparatus and demodulation method thereof.
The technical scheme that the present invention taked is for achieving the above object: a kind of Continuous phase frequency shift keying digital demodulating apparatus, it is characterized in that: comprise comparator device and Field Programmable Gate Array, Field Programmable Gate Array internal circuit comprises clock unit, sampling unit, counting unit, buffer cell and reconstruction unit, and described clock unit is connected with sampling unit, counting unit, buffer cell and reconstruction unit; Described comparator device connects sampling unit; Sampling unit connection count unit; Counting unit connects buffer cell; Buffer cell connection reconstruction unit.
Demodulation method of the present invention is: clock unit is determined system works clock frequency value according to Continuous phase frequency shift keying signal(-) carrier frequency and modulation degree, by external clock frequency source frequency division, produce system works clock, if external clock source frequency and working clock frequency ratio are n, maximum frequency division counter value is (n/2)-1, clock unit initial condition work clock signal is low level, frequency division counter value is 0, clock unit is in each external clock reference rising edge judgement frequency division counter value, if be less than maximum frequency division counter value, frequency division counter value adds 1, otherwise work clock signal upset, and frequency division counter value zero clearing.
Sampling unit of the present invention is at each work clock rising edge judgement binary signal level continuous time, if continuous two signal levels be all high level or be all low level, be output as low level; If continuous two signal levels are not identical, be output as high level; The signal of exporting is zero-crossing pulse signal.
Counting unit of the present invention judges at each work clock rising edge whether zero-crossing pulse signal is high level, if zero-crossing pulse signal is high level, since 0 counting process, if there is no zero-crossing pulse signal, even if or have a zero-crossing pulse signal, but count value is less than least count limits value, count value adds 1, counting process is until count value exceeds first zero-crossing pulse signal arrival afterwards of least count limits value, or count value finishes while exceeding maximum count limits value, when finishing, counting process exports count value, and output counting complement mark position high level, counting complement mark position high level continues a work clock cycle, count afterwards complement mark bit recovery low level.
Whether buffer cell of the present invention is high level in each work clock rising edge judgement counting complement mark position, high level if, read in count value, by sequence of addresses, store count value in loop-around data storage area one, and upgrade current memory space and take situation, when system just brings into operation, buffer cell accumulation count value data are to the occupied half in loop-around data storage area, data effective marker position output high level is continued to a work clock cycle, and by sequence of addresses, extract a count value output from loop-around data storage area, after this system continuous service, at each work clock rising edge, judges and rebuilds whether complement mark position is high level, and high level extracts a count value output by sequence of addresses from loop-around data storage area if.
Reconstruction unit of the present invention judges at each work clock rising edge whether data effective marker position is high level, high level if, enter reconstruction state, read a count value, count value is compared with predetermined threshold value, if count value is greater than threshold value, demodulated output signal is high level, otherwise demodulated output signal is low level; After this count value of take counts down as maximum, if each work clock rising edge countdown amount is not 0, demodulated output signal is constant, countdown amount subtracts 1, otherwise rebuild complement mark position output high level, continues a work clock cycle, enters next process of reconstruction, again read new count value, with threshold value comparison, export new restituted signal, again count down.
The features such as feature of the present invention and beneficial effect are: it is simple that this demodulating equipment has circuit, are easy to realize, and programmable logic resource consumption less and signal adaptive is strong.The alternative traditional Continuous phase frequency shift keying digital demodulation method of this demodulation method, thereby the realization of having avoided adopting traditional Continuous phase frequency shift keying digital demodulation method to exist is complicated, consumption of natural resource mainly with and can not adapt to data rate and the approaching defect of carrier frequency.
Accompanying drawing explanation
Fig. 1 is that circuit of the present invention connects block diagram.
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described: as shown in Figure 1, clock unit is determined system works clock frequency value according to Continuous phase frequency shift keying signal(-) carrier frequency and modulation degree, by external clock frequency source frequency division, produce system works clock, offer sampling unit, counting unit, buffer cell and reconstruction unit, if external clock source frequency and working clock frequency ratio are n, maximum frequency division counter value is (n/2)-1, clock unit initial condition work clock signal is low level, frequency division counter value is 0, clock unit is in each external clock reference rising edge judgement frequency division counter value, if be less than maximum frequency division counter value, frequency division counter value adds 1, otherwise work clock signal upset, and frequency division counter value zero clearing.
Simulation Continuous phase frequency shift keying modulation signal produces binary signal continuous time by comparator device.
Continuous time, binary signal produced zero-crossing pulse signal by sampling unit.Sampling unit of the present invention is at each work clock rising edge judgement binary signal level continuous time, if continuous two signal levels be all high level or be all low level, be output as low level; If continuous two signal levels are not identical, be output as high level; The signal of exporting is zero-crossing pulse signal.
Zero-crossing pulse signal produces count value and counting complement mark position by counting unit.Counting unit of the present invention judges at each work clock rising edge whether zero-crossing pulse signal is high level, if zero-crossing pulse signal is high level, since 0 counting process, if there is no zero-crossing pulse signal, even if or have a zero-crossing pulse signal, but count value is less than least count limits value, count value adds 1, counting process is until count value exceeds first zero-crossing pulse signal arrival afterwards of least count limits value, or count value finishes while exceeding maximum count limits value, when finishing, counting process exports count value, and output counting complement mark position high level, counting complement mark position high level continues a work clock cycle, count afterwards complement mark bit recovery low level.
Buffer cell of the present invention according to counting, read in, stored count numerical value by complement mark position, and produce data effective marker position.Whether buffer cell is high level in each work clock rising edge judgement counting complement mark position, high level if, read in count value, by sequence of addresses, store count value in loop-around data storage area one, and upgrade current memory space and take situation, when system just brings into operation, buffer cell accumulation count value data are to the occupied half in loop-around data storage area, data effective marker position output high level is continued to a work clock cycle, and by sequence of addresses, extract a count value output from loop-around data storage area, after this system continuous service, at each work clock rising edge, judges and rebuilds whether complement mark position is high level, and high level extracts a count value output by sequence of addresses from loop-around data storage area if.
Reconstruction unit of the present invention enters reconstruction state according to data effective marker position by idle condition.At reconstruction state, produce demodulated output signal and rebuild complement mark position, and reading the reconstruction numerical value that buffer cell provides, demodulated output signal is exported to subsequent conditioning circuit and is processed.Reconstruction unit judges at each work clock rising edge whether data effective marker position is high level, high level if, enter reconstruction state, read a count value, count value is compared with predetermined threshold value, if count value is greater than threshold value, demodulated output signal is high level, otherwise demodulated output signal is low level; After this count value of take counts down as maximum, if each work clock rising edge countdown amount is not 0, demodulated output signal is constant, countdown amount subtracts 1, otherwise rebuild complement mark position output high level, continues a work clock cycle, enters next process of reconstruction, again read new count value, with threshold value comparison, export new restituted signal, again count down.
The flexibility of this device is, by analyzing Continuous phase frequency shift keying modulation signal carrier frequency and modulation degree, simple working clock frequency, loop-around data storage area size, least count restriction and maximum count restriction and the count value threshold value adjusted, just can adapt to the demodulation of various signals.
This demodulating equipment has external clock interface, modulation signal input interface and restituted signal output interface.
Claims (6)
1. a Continuous phase frequency shift keying digital demodulating apparatus, it is characterized in that: comprise comparator device and Field Programmable Gate Array, Field Programmable Gate Array internal circuit comprises clock unit, sampling unit, counting unit, buffer cell and reconstruction unit, and described clock unit is connected with sampling unit, counting unit, buffer cell and reconstruction unit; Described comparator device connects sampling unit; Sampling unit connection count unit; Counting unit connects buffer cell; Buffer cell connection reconstruction unit.
2. the demodulation method of a Continuous phase frequency shift keying digital demodulating apparatus according to claim 1, it is characterized in that: clock unit is determined system works clock frequency value according to Continuous phase frequency shift keying signal(-) carrier frequency and modulation degree, by external clock frequency source frequency division, produce system works clock, if external clock source frequency and working clock frequency ratio are n, maximum frequency division counter value is (n/2)-1, clock unit initial condition work clock signal is low level, frequency division counter value is 0, clock unit is in each external clock reference rising edge judgement frequency division counter value, if be less than maximum frequency division counter value, frequency division counter value adds 1, otherwise work clock signal upset, and frequency division counter value zero clearing.
3. the demodulation method of a kind of Continuous phase frequency shift keying digital demodulating apparatus according to claim 1, it is characterized in that: sampling unit is at each work clock rising edge judgement binary signal level continuous time, if continuous two signal levels are all high level or are all low level, are output as low level; If continuous two signal levels are not identical, be output as high level; The signal of exporting is zero-crossing pulse signal.
4. the demodulation method of a kind of Continuous phase frequency shift keying digital demodulating apparatus according to claim 1, it is characterized in that: counting unit judges at each work clock rising edge whether zero-crossing pulse signal is high level, if zero-crossing pulse signal is high level, since 0 counting process, if there is no zero-crossing pulse signal, even if or have a zero-crossing pulse signal, but count value is less than least count limits value, count value adds 1, counting process is until count value exceeds first zero-crossing pulse signal arrival afterwards of least count limits value, or count value finishes while exceeding maximum count limits value, when finishing, counting process exports count value, and output counting complement mark position high level, counting complement mark position high level continues a work clock cycle, count afterwards complement mark bit recovery low level.
5. the demodulation method of a kind of Continuous phase frequency shift keying digital demodulating apparatus according to claim 1, it is characterized in that: whether buffer cell is high level in each work clock rising edge judgement counting complement mark position, high level if, read in count value, by sequence of addresses, store count value in loop-around data storage area one, and upgrade current memory space and take situation, when system just brings into operation, buffer cell accumulation count value data are to the occupied half in loop-around data storage area, data effective marker position output high level is continued to a work clock cycle, and by sequence of addresses, extract a count value output from loop-around data storage area, after this system continuous service, at each work clock rising edge, judges and rebuilds whether complement mark position is high level, and high level extracts a count value output by sequence of addresses from loop-around data storage area if.
6. the demodulation method of a kind of Continuous phase frequency shift keying digital demodulating apparatus according to claim 1, it is characterized in that: reconstruction unit judges at each work clock rising edge whether data effective marker position is high level, high level if, enter reconstruction state, read a count value, count value is compared with predetermined threshold value, if count value is greater than threshold value, demodulated output signal is high level, otherwise demodulated output signal is low level; After this count value of take counts down as maximum, if each work clock rising edge countdown amount is not 0, demodulated output signal is constant, countdown amount subtracts 1, otherwise rebuild complement mark position output high level, continues a work clock cycle, enters next process of reconstruction, again read new count value, with threshold value comparison, export new restituted signal, again count down.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310667947.3A CN103634263A (en) | 2013-12-07 | 2013-12-07 | Continuous-phase frequency-shift keying digital demodulation device and demodulation method implemented by same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310667947.3A CN103634263A (en) | 2013-12-07 | 2013-12-07 | Continuous-phase frequency-shift keying digital demodulation device and demodulation method implemented by same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103634263A true CN103634263A (en) | 2014-03-12 |
Family
ID=50214896
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310667947.3A Pending CN103634263A (en) | 2013-12-07 | 2013-12-07 | Continuous-phase frequency-shift keying digital demodulation device and demodulation method implemented by same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103634263A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105072069A (en) * | 2015-08-07 | 2015-11-18 | 株洲南车时代电气股份有限公司 | FSK modulator circuit |
| CN105897639A (en) * | 2014-12-09 | 2016-08-24 | 飞思卡尔半导体公司 | FSK (frequency-shift keying) demodulator |
| CN106464624A (en) * | 2016-07-12 | 2017-02-22 | 深圳市汇顶科技股份有限公司 | A signal demodulating device for an enclosed communications system and a method thereof |
| CN109639396A (en) * | 2018-12-19 | 2019-04-16 | 惠科股份有限公司 | Transmission method, device and the computer readable storage medium of data |
| CN110336547A (en) * | 2019-06-21 | 2019-10-15 | 华中科技大学 | A kind of wide range anti-saturation digital signal amplitude demodulation method and demodulator |
| CN111865853A (en) * | 2020-06-30 | 2020-10-30 | 中国人民解放军军事科学院国防科技创新研究院 | Demodulation method and device for small modulation index continuous phase signal |
| CN111953629A (en) * | 2020-08-21 | 2020-11-17 | 上海南芯半导体科技有限公司 | Qi standard-based FSK demodulator of wireless charging equipment and demodulation method thereof |
| CN112444673A (en) * | 2020-11-10 | 2021-03-05 | 青岛鼎信通讯股份有限公司 | Frequency measurement method applied to standard meter of electric energy meter calibrating device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102043090A (en) * | 2009-10-23 | 2011-05-04 | 西安费斯达自动化工程有限公司 | Measurement system for frequency-shift signal parameter of track circuit |
| CN103346988A (en) * | 2013-06-13 | 2013-10-09 | 电子科技大学 | FSK digital demodulator |
-
2013
- 2013-12-07 CN CN201310667947.3A patent/CN103634263A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102043090A (en) * | 2009-10-23 | 2011-05-04 | 西安费斯达自动化工程有限公司 | Measurement system for frequency-shift signal parameter of track circuit |
| CN103346988A (en) * | 2013-06-13 | 2013-10-09 | 电子科技大学 | FSK digital demodulator |
Non-Patent Citations (1)
| Title |
|---|
| 孙玉梅: "基于FPGA的FSK调制解调器的设计及实现", 《电子科技》 * |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105897639A (en) * | 2014-12-09 | 2016-08-24 | 飞思卡尔半导体公司 | FSK (frequency-shift keying) demodulator |
| CN105897639B (en) * | 2014-12-09 | 2020-06-16 | 恩智浦美国有限公司 | FSK demodulator |
| CN105072069B (en) * | 2015-08-07 | 2018-07-31 | 株洲南车时代电气股份有限公司 | A kind of FSK modulation circuit |
| CN105072069A (en) * | 2015-08-07 | 2015-11-18 | 株洲南车时代电气股份有限公司 | FSK modulator circuit |
| US10291388B2 (en) | 2016-07-12 | 2019-05-14 | Shenzhen GOODIX Technology Co., Ltd. | Signal demodulation apparatus and method in closed communication system |
| WO2018010082A1 (en) * | 2016-07-12 | 2018-01-18 | 深圳市汇顶科技股份有限公司 | Signal demodulating device and method applying to closed communication system |
| CN106464624A (en) * | 2016-07-12 | 2017-02-22 | 深圳市汇顶科技股份有限公司 | A signal demodulating device for an enclosed communications system and a method thereof |
| CN109639396A (en) * | 2018-12-19 | 2019-04-16 | 惠科股份有限公司 | Transmission method, device and the computer readable storage medium of data |
| CN109639396B (en) * | 2018-12-19 | 2021-03-16 | 惠科股份有限公司 | Data transmission method and device and computer readable storage medium |
| US11088817B2 (en) | 2018-12-19 | 2021-08-10 | HKC Corporation Limited | Data transmission method, data transmission device, and computer readable storage medium |
| CN110336547A (en) * | 2019-06-21 | 2019-10-15 | 华中科技大学 | A kind of wide range anti-saturation digital signal amplitude demodulation method and demodulator |
| CN110336547B (en) * | 2019-06-21 | 2020-11-24 | 华中科技大学 | Wide-range anti-saturation digital signal amplitude demodulation method and demodulator |
| CN111865853A (en) * | 2020-06-30 | 2020-10-30 | 中国人民解放军军事科学院国防科技创新研究院 | Demodulation method and device for small modulation index continuous phase signal |
| CN111953629A (en) * | 2020-08-21 | 2020-11-17 | 上海南芯半导体科技有限公司 | Qi standard-based FSK demodulator of wireless charging equipment and demodulation method thereof |
| CN112444673A (en) * | 2020-11-10 | 2021-03-05 | 青岛鼎信通讯股份有限公司 | Frequency measurement method applied to standard meter of electric energy meter calibrating device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103634263A (en) | Continuous-phase frequency-shift keying digital demodulation device and demodulation method implemented by same | |
| CN105897639A (en) | FSK (frequency-shift keying) demodulator | |
| EP2144071A2 (en) | Method and system for detecting the phase wiring of an unknown phase voltage relative to a reference phase voltage | |
| CN105281776A (en) | Manchester decoding device capable of carrying out error correction and method thereof | |
| CN105516040B (en) | The low consumption demodulation method of fsk signal in wireless charging device | |
| CN102611447B (en) | Noise adding signal synchronization clock extraction device based on FPGA (field programmable gate array) | |
| EP3512170A1 (en) | Circuit structure for efficiently demodulating fsk signal in wireless charging device | |
| CN104155678A (en) | Single channel pulse height analyzer realized by applying peak position detecting method | |
| CN102325109B (en) | Rapid FSK (Frequency Shift Keying) demodulation method and full-digital low-power-consumption device for realizing same | |
| CN103297060A (en) | Decoding circuit suitable for correcting miller code signal at high speed | |
| CN105262489A (en) | Time delay circuit and time delay method for differential Manchester decoding | |
| CN108023846A (en) | Detect method, circuit, equipment and the computer program product of fsk modulated signal | |
| CN102496055B (en) | RFID demodulation mode automatic identification method and automatic identification circuit thereof | |
| CN106487477B (en) | Receiving end signal processing method based on zero passage detection | |
| CN106921463B (en) | Anti-interference decoding method and system | |
| CN104639176B (en) | The asynchronous decoder and method of BMC signals | |
| CN105471437B (en) | Data regenerator | |
| CN103595421A (en) | A decoder for TYPE A basic data rate signals transmitted by a decoding card | |
| CN204255495U (en) | A kind of fault diagnosis system based on wireless vibration sensor | |
| CN104202097A (en) | High-speed scan method used for digital monitoring receiver | |
| CN204028371U (en) | The single channel pulse height analyzer that application peak position detection method realizes | |
| CN104518755A (en) | Digital circuit noise filter and digital filtering method | |
| CN202586998U (en) | Synchronous clock extraction device for noise-added signal based on FPGA (field programmable gate array) | |
| CN104639483B (en) | Based on 14443 BPSK subcarrier digital correlation demodulation circuits | |
| CN103427803B (en) | Based on the method for the filtering burr of synchronous circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20140312 |
|
| WD01 | Invention patent application deemed withdrawn after publication |