CN105590851A - 一种GaN HEMT器件制作方法 - Google Patents

一种GaN HEMT器件制作方法 Download PDF

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CN105590851A
CN105590851A CN201610158915.4A CN201610158915A CN105590851A CN 105590851 A CN105590851 A CN 105590851A CN 201610158915 A CN201610158915 A CN 201610158915A CN 105590851 A CN105590851 A CN 105590851A
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陈一峰
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66431Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

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Abstract

本发明提供一种GaN?HEMT器件制作方法,提供衬底,包括以下步骤:S1、在衬底上沉积一层VLS生长用的催化剂;S2、在催化剂上形成周期性的压印胶;S3、按照压印胶的分布刻蚀催化剂,形成周期性的图形化的催化剂;S4、采用VLS生长机理,在图形化的催化剂上生长GaN纳米柱;S5、去除图形化的催化剂,形成图形化衬底;S6、在图形化衬底上生长外延层,在外延层上完成源极、漏极、栅极的制作。本发明采用图形化衬底进行GaN外延,不仅具有图形化衬底外延横向生长缺陷较少的优点,同时避免了生长过程中,由于图形尺寸较大,横向生长易形成孔洞,影响后续器件制作与使用;VLS的引入有利于提高过渡层的外延质量,提高GaN?HEMT器件性能。

Description

一种GaN HEMT器件制作方法
技术领域
本发明属于半导体器件技术领域,具体涉及一种GaNHEMT器件制作方法。
背景技术
作为宽禁带半导体的典型代表,GaN具有更宽的禁带宽度、更高的饱和电子漂移速度、更大的临界击穿电场强度、更好的导热性能等特点,更重要的是它与AlGaN能够形成AlGaN/GaN异质结,便于制作HEMT器件。
目前,大面积的GaN衬底材料还不成熟,GaN器件多生长在Si衬底、蓝宝石衬底和SiC衬底上,异质外延由于晶格常数、热膨胀系数等差异,在界面处易形成缺陷,从而影响外延质量,导致器件性能下降。以常用的SiC衬底为例,虽然SiC和GaN均为六方晶系,且晶格常数差异仅有3%,但外延过程中,SiC与GaN生长界面处仍有较多的位错出现,影响GaN器件性能。一般来说,同质外延的结晶质量好于异质外延。
2000年以后,图形化衬底逐渐应用于外延中,传统的图形化衬底,尺寸较大,一般在数百纳米到数微米之间,形成的外延下方多有孔洞或部分悬空,不方便芯片背面工艺制作和器件的特殊环境使用。
发明内容
本发明的目的在于针对现有技术的不足,提供一种GaNHEMT器件制作方法,该GaNHEMT器件制作方法可以很好地解决现有半导体器件采用普通衬底外延横向生长缺陷较多的问题。
为达到上述要求,本发明采取的技术方案是:提供一种GaNHEMT器件制
作方法,提供衬底,包括以下步骤:
S1、在衬底上沉积一层VLS生长用的催化剂;
S2、在催化剂上形成周期性的压印胶;
S3、按照压印胶的分布刻蚀催化剂,形成周期性的图形化的催化剂;
S4、采用VLS生长机理,在图形化的催化剂上生长GaN纳米柱;
S5、去除图形化的催化剂,形成图形化衬底;
S6、在图形化衬底上生长外延层,在外延层上完成源极、漏极、栅极的制作。
与现有技术相比,该GaNHEMT器件制作方法具有的优点如下:
(1)采用该图形化衬底进行GaN外延,不仅具有图形化衬底外延横向生长缺陷较少的优点,同时避免了生长过程中,由于图形尺寸较大,横向生长易形成孔洞,影响后续器件制作与使用;
(2)VLS的引入有利于提高过渡层的外延质量,提高GaNHEMT器件性能。
(3)与传统的SiC衬底相比,利用VLS生长出GaN纳米柱高结晶质量,进一步减少由于晶格常数、热膨胀系数等差异引入的缺陷,利于GaN器件外延生长,提高GaN器件性能。
附图说明
此处所说明的附图用来提供对本申请的进一步理解,构成本申请的一部分,在这些附图中使用相同的参考标号来表示相同或相似的部分,本申请的示意性实施例及其说明用于解释本申请,并不构成对本申请的不当限定。在附图中:
图1示出了本申请的流程示意图;
图2示出了根据本申请步骤S1形成的结构示意图;
图3示出了根据本申请步骤S2形成的结构示意图;
图4示出了根据本申请步骤S3形成的结构示意图;
图5示出了根据本申请步骤S4形成的结构示意图;
图6示出了根据本申请步骤S5形成的结构示意图;
图7示出了根据本申请步骤S6形成的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚,以下结合附图及具体实施例,对本申请作进一步地详细说明。为简单起见,以下描述中省略了本领域技术人员公知的某些技术特征。
根据本发明的一个实施例,提供一种GaNHEMT器件制作方法,提供衬底10,衬底10的材料为Si、SiC、蓝宝石或金刚石,包括以下步骤:
S1、在衬底10上沉积一层VLS生长用的催化剂20,该催化剂20的材料为Al、Ni或Au,厚度为50~100nm;
S2、利用纳米压印技术,在催化剂20上形成周期性的压印胶30;纳米压印技术主要包括两大步,第一,制作纳米压印模板40,模板是纳米压印最关键的技术,其质量的好坏直接决定压印的效果;最早的压印模板材料选用的是硅,因为硅的加工技术比较成熟,其制作方法是通过电子束光刻结合反应离子刻蚀,StephenY.Chou教授的模板是在Si衬底10上制作的Si02结构,深度约为250nm,线宽为25nm;第二,压印图形,首先在基底上旋涂一定厚度的压印胶30,接着加热压印胶30和纳米压印模板40至其玻璃化温度以上,加压把纳米压印模板40压入压印胶30中,压力和温度都保持在适当的水平,通过紫外线曝光或改变温度使压印胶30上的结构成型固化,之后在一定温度下分离纳米压印模板40和压印胶30,待压印胶30完全固化后其表面上就出现了与纳米压印模板40上的图形相反的结构,压印胶30纳米结构图形可以直接作为器件结构使用,也可以作为图形结构进一步转移的掩模层。
S3、按照压印胶30的分布刻蚀催化剂20,形成周期性的图形化的催化剂20;
S4、采用VLS生长机理,以Ga源和N源有机气体作为反应气体,以H2气或Ar气作为载气,在图形化的催化剂20上生长GaN纳米柱50,GaN纳米柱50的高度不超过100nm;VLS生长机理兼具液相外延和气相外延的优点:催化剂20生长发生在生长催化剂20熔融液体和衬底10固体的交界面处,外延质量较高,而气体分子逐渐溶解于熔融状态的催化剂20中,条件控制较为容易,且生长速率较快。
S5、采用刻蚀技术去除图形化的催化剂20,形成图形化衬底10,该图形化衬底10的宽度和间隔距离均小于100nm;
S6、在图形化衬底10上生长外延层,在外延层上完成源极100、漏极80、栅极90的制作,该步骤具体为:在图形化衬底10上依次生长GaN过渡层60和AlxGa1-xN势垒层70,在AlxGa1-xN势垒层70上完成源极100、漏极80、栅极90的制作,且源级和漏极80为欧姆接触,栅极90为肖特基接触,该AlxGa1-xN势垒层70中Al组分x=0.1~0.3。
以上所述实施例仅表示本发明的几种实施方式,其描述较为具体和详细,但并不能理解为对本发明范围的限制。应当指出的是,对于本领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干变形和改进,这些都属于本发明保护范围。因此本发明的保护范围应该以所述权利要求为准。

Claims (10)

1.一种GaNHEMT器件制作方法,提供衬底,其特征在于,包括以下步骤:
S1、在所述衬底上沉积一层VLS生长用的催化剂;
S2、在所述催化剂上形成周期性的压印胶;
S3、按照所述压印胶的分布刻蚀所述催化剂,形成周期性的图形化的催化剂;
S4、采用VLS生长机理,在图形化的催化剂上生长GaN纳米柱;
S5、去除所述图形化的催化剂,形成图形化衬底;
S6、在所述图形化衬底上生长外延层,在所述外延层上完成源极、漏极、栅极的制作。
2.根据权利要求1所述的GaNHEMT器件制作方法,其特征在于,所述衬底的材料为Si、SiC、蓝宝石或金刚石。
3.根据权利要求1所述的GaNHEMT器件制作方法,其特征在于,所述步骤S2利用纳米压印技术,在所述催化剂上形成周期性的压印胶。
4.根据权利要求1所述的GaNHEMT器件制作方法,其特征在于,所述步骤S4具体为:采用VLS生长机理,以Ga源和N源有机气体作为反应气体,以H2气或Ar气作为载气,在所述图形化的催化剂上生长GaN纳米柱。
5.根据权利要求1所述的GaNHEMT器件制作方法,其特征在于,所述步骤S5采用刻蚀技术去除所述图形化的催化剂。
6.根据权利要求1所述的GaNHEMT器件制作方法,其特征在于,所述催化剂的材料为Al、Ni或Au。
7.根据权利要求6所述的GaNHEMT器件制作方法,其特征在于,所述催化剂的厚度为50~100nm。
8.根据权利要求1所述的GaNHEMT器件制作方法,其特征在于,所述步骤S6具体为在所述图形化衬底上依次生长GaN过渡层和AlxGa1-xN势垒层,在所述AlxGa1-xN势垒层上完成源极、漏极、栅极的制作,且源级和漏极为欧姆接触,栅极为肖特基接触。
9.根据权利要求8所述的GaNHEMT器件制作方法,其特征在于,所述AlxGa1-xN势垒层中Al组分x=0.1~0.3。
10.根据权利要求1所述的GaNHEMT器件制作方法,其特征在于,所述步骤S5中图形化衬底的宽度和间隔距离均小于100nm。
CN201610158915.4A 2016-03-18 2016-03-18 一种GaN HEMT器件制作方法 Pending CN105590851A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106067478A (zh) * 2016-08-08 2016-11-02 深圳市华星光电技术有限公司 像素界定层的制作方法与oled器件的制作方法

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US20100276665A1 (en) * 2007-02-09 2010-11-04 Wang Nang Wang Production of semiconductor devices
CN101891145A (zh) * 2009-05-22 2010-11-24 熊长宏 气-液-固相法制备硅纳米线
US20120141799A1 (en) * 2010-12-03 2012-06-07 Francis Kub Film on Graphene on a Substrate and Method and Devices Therefor

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Publication number Priority date Publication date Assignee Title
US20100276665A1 (en) * 2007-02-09 2010-11-04 Wang Nang Wang Production of semiconductor devices
CN101689484A (zh) * 2007-07-10 2010-03-31 Nxp股份有限公司 失配衬底上的单晶生长
CN101891145A (zh) * 2009-05-22 2010-11-24 熊长宏 气-液-固相法制备硅纳米线
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106067478A (zh) * 2016-08-08 2016-11-02 深圳市华星光电技术有限公司 像素界定层的制作方法与oled器件的制作方法

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