CN105486922B

CN105486922B - A kind of phase-detection implementation method based on time delay chain framework

Info

Publication number: CN105486922B
Application number: CN201410538977.9A
Authority: CN
Inventors: 赵振涌; 王宁; 何杰; 张伟彬; 李婷婷; 汪辉; 袁寰; 李晓庆; 陈昭; 吴英攀
Original assignee: Beijing Automation Control Equipment Institute BACEI
Current assignee: Beijing Automation Control Equipment Institute BACEI
Priority date: 2014-10-13
Filing date: 2014-10-13
Publication date: 2019-11-15
Anticipated expiration: 2034-10-13
Also published as: CN105486922A

Abstract

The invention belongs to frequency measurement fields, and in particular to a kind of phase-detection implementation method based on novel time-lapse chain framework.It includes the following steps: step 1: delay, three times by input signal delay, postpones a cycle every time；Step 2: triggering uses the signal in two periods of delay as the start trigger of error signal, and the termination for using the signal in three periods of delay as error signal triggers, and obtains the delay length of error signal.Remarkable result of the invention is: the present invention can effectively extract the error introduced in sampling process by non-positive period, and at an arbitrary position export error, effectively avoid error influence caused by system.

Description

A kind of phase-detection implementation method based on time delay chain framework

Technical field

The invention belongs to frequency measurement fields, and in particular to a kind of phase-detection realization side based on novel time-lapse chain framework Method.

Background technique

In digital frequency measuring field, digital interpolation Measuring Frequency Method is on the basis of synchronizing continuous Measuring Frequency Method, using relative measurement Technology is further segmented by time delay chain and synchronizes ± 1 quantization error part in continuous Measuring Frequency Method (Fig. 1), and completion is believed by measured frequency Number with high frequency filling frequency phase information detect, to reduce the quantization error for synchronizing continuous Measuring Frequency Method, improve frequency measurement Precision.Method for detecting phases based on time delay chain is the key technology of digital interpolation Measuring Frequency Method (Fig. 2).

Method for detecting phases based on common time delay chain framework at present during FPGA or ASIC design are realized, due to Untreated measured signal and high frequency fill clock asynchronous clock domain problem, and there are the feelings that signal metastable state and phase information mistake are clapped Condition, so that digital interpolation Measuring Frequency Method can not be realized reliably.

Summary of the invention

The present invention is directed to the defect of traditional technology, provides a kind of phase-detection realization side based on novel time-lapse chain framework Method.

The present invention is implemented as follows: a kind of phase-detection implementation method based on novel time-lapse chain framework, including it is following Step:

Step 1: delay

Three times by input signal delay, postpone a cycle every time；

Step 2: triggering

The signal in two periods of delay is used to use the signal in three periods of delay as mistake as the start trigger of error signal The termination of difference signal triggers, and obtains the delay length of error signal.

A kind of phase-detection implementation method based on novel time-lapse chain framework as described above, wherein the delay passes through Delay cell is realized.

A kind of phase-detection implementation method based on novel time-lapse chain framework as described above, wherein delay n Period can be realized by delay chain.

Remarkable result of the invention is: the present invention can effectively extract the mistake introduced in sampling process by non-positive period Difference, and at an arbitrary position export error, effectively avoid error influence caused by system.

Detailed description of the invention

Fig. 1 is the schematic diagram of high frequency sampling；

Fig. 2 is the schematic diagram that high frequency sampling generates error position；

Fig. 3 is device of the application using detection compensation；

Fig. 4 is level logic relation schematic diagram.

Specific embodiment

As shown in Fig. 2, a kind of phase-detection implementation method based on novel time-lapse chain framework, includes the following steps:

Step 1: delay

Three times by input signal delay, postpone a cycle every time.

Step 2: triggering

The delay by delay cell realization, due to delay cell can picosecond level work again, speed is fast, will not Introduce error.

Above three signal can postpone n period again, so that it may extract error signal on point at any time.

The n period of delay can be realized by delay chain.

As shown in Fig. 3, a kind of novel time-lapse chain framework includes trigger (FFD1, FFD2 and FFD3), register (REGA1, REGA2, REGA3, REGB1, REGB2 and REGB3), NOT gate U1 and door U2 and delay cell (DLA and DLB).

The time delay chain framework is measured signal or sampling gate (IN) and high-frequency impulse (CLK) letter there are two signal input Number.The partial circuit works under CLK clock domain.IN signal belongs to different clock-domains signal relative to CLK signal.Trigger FFD1 and FFD2 completes two-stage trigger delay of the IN signal under CLK clock domain, carries out clock domain and synchronizes, eliminates metastable State.The output signal FFD3O of trigger FFD3, output signal U 1O after NOT gate U1 with the output signal of FFD2 pass through with Latch enable signal of the output signal U 2O of door U2 as REGA3 and REGB3 register.The output signal of FFD2 introduces simultaneously Interpolation Measuring Frequency Method logical circuit of counter U3 completes the tally control of high-frequency impulse in measured signal complete cycle and non-integer-period.DLA and DLB is that delay unit chain is used to carry out ns grades (FPGA realizations) or ps grades of (ASIC realization) timing to IN signal and CLK signal Delay.REGA1 and REGB1 register is respectively used to latch DLA and DLB delay unit chain timing information.REGA2 and The delay unit chain timing information that REGB2 register is respectively used to the output of REGA1 and REGB1 register, which synchronizes, to postpone and disappears Except metastable state.REGA3 and REGB3 register root according to the significant instant (' 1 ') with the output signal U 2O of door U2 to REGA2 and The delay unit chain timing information of REGB2 register output is latched.The delay unit of REGA3 and REGB3 registers latch Chain timing information DeAo has sufficiently reacted the phase information between IN and CLK with DeBo.DeAo and DeBo are due to through oversampling clock CLK clock synchronization process guarantees that timing stabilization can directly be used by phase information extraction logic, and the phase information is IN letter Number rising edge time is synchronous to latch, and eliminates under limiting case that phase information and IN signal mistake clap problem in asynchronous latching process.

Input IN signal and CLK signal；CLK signal is connected as work clock with all sequential logic devices, while with DLB is connected；IN signal is connected with the end FFD1D, while being connected with DLA；FFD1Q is connected with the end FFD2D；The end FFD2Q and FFD3D End is connected, while being connected with U2；The end FFD3Q is connected with U1；U1 is connected with U2；The EN at the end EN and REGB3 of the end U2O and REGA3 End is connected；DLA is connected with REGA1；REGA1 is connected with REGA2；REGA2 is connected with REGA3；REGB1 is connected with REGB2； REGB2 is connected with REGB3.

Claims

1. a kind of phase-detection implementation method based on time delay chain framework, which is characterized in that include the following steps:

Step 1: delay

Three times by input signal delay, postpone a cycle every time；

Step 2: delay unit chain timing information is latched and is postponed

Delay unit chain timing information is latched, and carries out a cycle delay,

Step 3: triggering and the latch of delay unit chain timing information

When input signal rising edge arrives, use the signal in two periods of delay as start trigger, with three periods of being delayed Signal locks the delay unit chain timing information after step 2 delay as triggering is terminated, according to trigger signal significant instant It deposits, obtains the phase information of input signal relative time clock signal；

The delay realizes that the delay is realized by delay unit chain by trigger.

2. a kind of phase-detection implementation method based on time delay chain framework as described in claim 1, it is characterised in that: input letter Number delay unit chain timing information is latched with clock signal delay unit chain timing information in trigger signal significant instant simultaneously, is locked It deposits content and sufficiently reflects phase information between input signal and clock signal.