CN105427795A - 像素驱动电路、方法、像素结构及显示器件 - Google Patents

像素驱动电路、方法、像素结构及显示器件 Download PDF

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CN105427795A
CN105427795A CN201610015162.1A CN201610015162A CN105427795A CN 105427795 A CN105427795 A CN 105427795A CN 201610015162 A CN201610015162 A CN 201610015162A CN 105427795 A CN105427795 A CN 105427795A
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write
film transistor
driving
driving transistors
capacitance structure
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廖峰
商广良
张玉婷
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BOE Technology Group Co Ltd
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Priority to CN201610015162.1A priority Critical patent/CN105427795A/zh
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Priority to PCT/CN2016/102950 priority patent/WO2017121162A1/zh
Priority to US15/523,849 priority patent/US20180047343A1/en
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
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Abstract

本发明公开了一种像素驱动电路、方法、像素结构及显示器件，该像素驱动电路，用于驱动像素结构中的发光器件，包括：驱动晶体管，源极与发光器件连接；电容结构，第一端和所述驱动晶体管的栅极连接；第一写入控制单元，用于在写入阶段将所述驱动晶体管的阈值电压写入所述电容结构的第一端；第二写入控制单元，用于在写入阶段将数据信号写入所述电容结构的第二端；电源输出控制单元，用于在发光阶段输出电源信号到所述驱动晶体管的漏极；电压跟随控制单元，用于通过所述电容结构控制所述驱动晶体管的栅极的电压跟随所述驱动晶体管的源极的电压的变化。本发明消除了发光器件本身的电容特性对显示的影响。

Description

像素驱动电路、方法、像素结构及显示器件
技术领域
本发明涉及像素驱动技术，特别是一种像素驱动电路、方法、像素结构及显示器件，在阈值补偿的基础上，消除发光器件本身的电容特性对显示的影响。
背景技术
在如图1所示的传统的由电流或电压驱动的发光器件像素结构中，由数据信号输入驱动晶体管的控制端并对电容进行充电，之后利用存储在电容中的电量来控制驱动晶体管的导通程度，实现对发光器件的电流的控制。
如图1所示的像素结构中，流过发光器件的电流I为：0.5*μn*Cox*W/L*(Vdata-V工作-Vth)2，其中：μn为载流子迁移率，Cox为驱动晶体管的等效电容，W/L为晶体管宽长比，Vdata为数据信号的电压，V工作为发光器件的工作电压，Vth为驱动晶体管的阈值电压。
由于不同驱动晶体管的Vth以及发光器件的V工作并不相同，当流过发光器件的电流I受到V工作和Vth的影响时，显示器件会出现显示不均匀现象，即：在相同的数据信号的驱动下，不同的像素单元会呈现出不同的亮度。
为了避免上述显示不均匀现象的发生，针对驱动晶体管的Vth漂移，现有技术中已经有如图2所示的解决方案。
然而，现有技术的解决方案并不能保证发光阶段发光的恒定性，解释如下。
由电流或电压驱动的发光器件，如有机发光二极管(OrganicLightEmittingDiode，OLED)或者电致变色显示器件(ElectroChromicDisplays，ECD)等，其自身都具有电容的性质，且其电容会随电压变化而变化。
也就是说，在具备阈值电压补偿的像素结构中，从写入阶段转变到发光阶段时，如图2所示的N4节点的电压会发生跳变。而如图2所示的具备阈值电压补偿的像素结构并不具备使得N2节点的电压跟随N4节点的电压的变化的能力，这就导致驱动晶体管T5的Vgs会在发光阶段发生改变，而Vgs的变化会引起流过发光器件的电流发生变化，导致发光器件在发光阶段亮度不统一。
发明内容
本发明实施例的目的在于提供一种像素驱动电路、方法、像素结构及显示器件，在阈值补偿的基础上，消除发光器件本身的电容特性对显示的影响。
为实现上述目的，本发明实施例提供了一种像素驱动电路，用于驱动像素结构中的发光器件，所述像素驱动电路包括：
驱动晶体管T5，源极与发光器件连接；
电容结构Cst，第一端和所述驱动晶体管T5的栅极连接；
第一写入控制单元，用于在写入阶段将所述驱动晶体管T5的阈值电压写入所述电容结构Cst的第一端；
第二写入控制单元，用于在写入阶段将数据信号写入所述电容结构Cst的第二端；
电源输出控制单元，用于在发光阶段输出电源信号到所述驱动晶体管T5的漏极；
电压跟随控制单元，用于在发光阶段通过所述电容结构Cst控制所述驱动晶体管T5的栅极的电压跟随所述驱动晶体管T5的源极的电压的变化。
上述的像素驱动电路，其中，所述电压跟随控制单元为：第三薄膜晶体管T3，用于在发光阶段导通所述驱动晶体管的源极和所述电容结构的第二端，以将所述驱动晶体管的源极电压写入所述驱动晶体管T5的栅极。
上述的像素驱动电路，其中，所述第一写入控制单元为：第二薄膜晶体管T2，用于在写入阶段导通所述驱动晶体管的漏极和栅极，以将所述驱动晶体管T5的阈值电压写入所述电容结构Cst的第一端。
上述的像素驱动电路，其中，所述第二写入控制单元为：第一薄膜晶体管(T1)，用于在写入阶段导通所述数据信号输入端子和所述电容结构的第二端，以在写入阶段将数据信号写入所述电容结构Cst的第二端。
上述的像素驱动电路，其中，所述第一写入控制单元为：第二薄膜晶体管T2，用于在写入阶段导通所述驱动晶体管的漏极和栅极，以将所述驱动晶体管T5的阈值电压写入所述电容结构Cst的第一端；
所述第二写入控制单元为：第一薄膜晶体管T1，用于在写入阶段导通所述数据信号输入端子和所述电容结构的第二端，以在写入阶段将数据信号写入所述电容结构Cst的第二端；
所述第一薄膜晶体管T1、第二薄膜晶体管T2和第四薄膜晶体管T4还在复位阶段导通，以利用所述电源信号和所述数据信号对所述电容结构进行充电。
上述的像素驱动电路，其中，所述第一写入控制单元为：第二薄膜晶体管T2，用于在写入阶段导通所述驱动晶体管的漏极和栅极，以将所述驱动晶体管T5的阈值电压写入所述电容结构Cst的第一端；
所述第二写入控制单元为：第一薄膜晶体管T1，用于在写入阶段导通所述数据信号输入端子和所述电容结构的第二端，以在写入阶段将数据信号写入所述电容结构Cst的第二端；
所述第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3和第四薄膜晶体管T4还在位于写入阶段和发光阶段之间的缓冲阶段截止。
上述的像素驱动电路，其中，所述发光器件为电致变色显示器件。
为了更好地实现上述目的，本发明实施例还提供了一种像素结构，包括发光器件，还包括用于驱动所述发光器件的上述任意的像素驱动电路。
为了更好地实现上述目的，本发明实施例还提供了一种显示器件，包括上述的像素结构。
为了更好地实现上述目的，本发明实施例还提供了一种像素驱动方法，用于驱动像素结构中的发光器件，所述像素驱动方法包括：
电压跟随控制步骤，在发光阶段通过像素驱动电路中的电容结构控制像素驱动电路中的驱动晶体管的栅极的电压跟随所述驱动晶体管的源极的电压的变化。
上述的像素驱动方法，所述电压跟随控制步骤具体为：在发光阶段导通所述驱动晶体管的源极和所述电容结构的第二端。
上述的像素驱动方法，还包括：在写入阶段和发光阶段之间，断开所述电容结构与外部的电路连接。
在像素结构从写入阶段转变到发光阶段时，由于发光器件的电容特性，将会导致驱动晶体管的源极电压发生变化，在本发明实施例的像素驱动电路、像素结构及显示器件中，利用电容结构的维持两端电压差的能力，将驱动晶体管的源极电压的跳变写入到驱动晶体管的栅极，使得驱动晶体管的栅极电压能够跟随其源极电压的变化而变化，从而保证驱动晶体管的Vgs保持不变，消除了发光器件本身的电容特性对显示的影响。
附图说明
图1表示传统的由电流或电压驱动的发光器件形成的像素结构；
图2表示传统的具备阈值电压补偿的像素结构；
图3表示本发明实施例的像素驱动电路的结构示意图；
图4表示本发明实施例的电压跟随控制单元采用薄膜晶体管实现的像素驱动电路的结构示意图；
图5表示本发明实施例的像素驱动电路写入阈值电压的示意图；
图6表示本发明实施例的第二写入控制单元采用薄膜晶体管实现的像素驱动电路的结构示意图；
图7表示本发明实施例的复用薄膜晶体管的像素驱动电路的结构示意图；
图8表示图7所示的像素驱动电路的时序示意图；
图9-图12为图7所示的像素驱动电路在不同阶段的等效电路示意图。
具体实施方式
本发明实施例的像素驱动电路、方法、像素结构及显示器件中，在阈值补偿的基础上，增加驱动晶体管的栅极跟随其源极电压变化的能力，消除发光器件本身的电容特性对显示的影响。
本发明实施例提供了一种像素驱动电路，用于驱动像素结构中的发光器件，所述像素驱动电路如图3所示包括：
驱动晶体管T5，源极与发光器件连接；
电容结构Cst，第一端和所述驱动晶体管T5的栅极连接；
第一写入控制单元，用于在写入阶段将所述驱动晶体管T5的阈值电压写入所述电容结构Cst的第一端；
第二写入控制单元，用于在写入阶段将数据信号写入所述电容结构Cst的第二端；
电源输出控制单元，用于在发光阶段输出电源信号到所述驱动晶体管T5的漏极；
电压跟随控制单元，用于在发光阶段通过所述电容结构Cst控制所述驱动晶体管T5的栅极的电压跟随所述驱动晶体管T5的源极的电压的变化。
本发明具体实施例中，在像素结构从写入阶段转变到发光阶段时，由于发光器件的电容特性，将会导致驱动晶体管的源极电压发生变化，在本发明实施例的像素驱动电路、像素结构及显示器件中，利用电容结构的维持两端电压差的能力，将驱动晶体管的源极电压的跳变写入到驱动晶体管的栅极，使得驱动晶体管的栅极电压能够跟随其源极电压的变化而变化，从而保证驱动晶体管的Vgs保持不变，消除了发光器件本身的电容特性对显示的影响。
由于ECD的电容特性远大于OLED的电容特性，因此本发明实施例的像素驱动电路用于ECD时，能够大大提高显示效果。
在本发明的具体实施例中，如图4所示，所述电压跟随控制单元为：第三薄膜晶体管T3，用于在发光阶段导通所述驱动晶体管T5的源极和所述电容结构Cst的第二端，以将所述驱动晶体管T5的源极电压写入所述驱动晶体管T5的栅极。
如图4所示，假定在T3导通之前N1节点的电压为V1，而N2节点的电压为V2，则当T3导通之后，N1节点的电压会变化为N4节点的电压V3(驱动晶体管T5的源极电压或者说是发光器件的工作电压)，即N1节点电压的电压变化量为：V3-V1。
由于电容结构Cst维持电压两端电压差的能力，因此当N1节点的电压从V1变化为V3时，N2节点的电压会变化为V2+(V3-V1)，则驱动晶体管的Vgs＝V2+(V3-V1)-V3＝V2-V1。
即，像素结构从写入阶段转变到发光阶段后，驱动晶体管T5的栅源电压与其源极电压(或者说发光器件的工作电压)无关，因此消除了发光器件本身的电容特性对显示的影响。
在本发明的具体实施例中，为了实现阈值补偿，需要将驱动晶体管T5的阈值电压写入电容结构Cst，以在发光阶段利用该写入的阈值电压去抵消驱动晶体管本身的阈值电压，以在发光阶段维持所述驱动晶体管的栅极电压，使得流过所述发光器件的电流与所述驱动晶体管的阈值电压Vth无关。
第一写入控制单元的实现方式多种多样，如图5所示，该第一写入控制单元可以为：第二薄膜晶体管T2，用于在写入阶段导通所述驱动晶体管的漏极和栅极，以将所述驱动晶体管T5的阈值电压写入所述电容结构Cst的第一端。
如图5所示，在写入阶段，当第二薄膜晶体管T2导通时，电容会沿着图5中虚线所示的路径放电，直至N2节点的电压变为驱动晶体管T5的阈值电压和发光器件的阈值电压之和，停止放电。稳定后，N2节点的电压为驱动晶体管T5的阈值电压和发光器件的阈值电压之和，实现了驱动晶体管T5的阈值电压到所述电容结构Cst的写入。
在本发明具体实施例中，像素驱动电路需要利用数据信号来控制驱动晶体管的导通程度，进而控制流过发光器件的电流。上述的像素驱动电路的第二写入控制单元的一种实现方式如图6所示，采用第一薄膜晶体管(T1)来实现，第一薄膜晶体管(T1)用于在写入阶段导通所述数据信号输入端子和所述电容结构的第二端，以在写入阶段将数据信号写入所述电容结构Cst的第二端。
当数据信号在写入阶段写入到N1节点之后，当像素结构从写入阶段转变到发光阶段时，由于电容结构Cst维持电压差的能力，则当N1节点的电压变化时，该数据信号则会进一步写入到N2节点，实现对驱动晶体管T5的导通程度的控制，在此不再详细描述。
应当理解的是，在写入数据信号和驱动晶体管的阈值电压之前，先要对电容结构进行充电(或者也可称之为复位)，在本发明的具体实施例中，充电控制结构和第一写入控制单元以及第二写入控制单元可以各自独立，如充电结构可以采用如图2所示的采用参考信号Vref和VDD信号的方式实现。
为了减少薄膜晶体管(如图2中的T6)的数量，简化驱动电路，在本发明的具体实施例中，可以复用之前的T1、T2和T4来实现对电容结构的充电。如图7所示，本发明具体实施例中，
所述电源输出控制单元为：第二薄膜晶体管T4；
所述第一写入控制单元为：第二薄膜晶体管T2，用于在写入阶段导通所述驱动晶体管的漏极和栅极，以将所述驱动晶体管T5的阈值电压写入所述电容结构Cst的第一端；
所述第二写入控制单元为：第一薄膜晶体管T1，用于在写入阶段导通所述数据信号输入端子和所述电容结构的第二端，以在写入阶段将数据信号写入所述电容结构Cst的第二端；
所述第一薄膜晶体管T1、第二薄膜晶体管T2和第四薄膜晶体管T4还在复位阶段导通，以利用所述电源信号和所述数据信号对所述电容结构进行充电。
当处于复位阶段时，所述第一薄膜晶体管T1、第二薄膜晶体管T2和第四薄膜晶体管T4导通，则数据信号会施加到N1节点，而VDD信号会施加到N2节点，由于数据信号和VDD信号之间的电压差，电容结构Cst在该阶段会被充电到一定程度。
相比于图2所示的结构，本发明具体实施例中减少了额外的信号(参考信号Vref)输入，简化了电路的实现。
当本发明具体实施例的驱动电路用于ECD时，上述的电容结构Cst相对于OLED驱动电路中的电容结构的电容要大很多。当电容结构的电容较大时，放电后需要一定的时间才能达到稳定状态，如果电容结构放电之后立即进入发光阶段，则由于电容结构还没有稳定，在发光阶段的初期会导致N2节点的电压变化，而这种变化也会导致驱动晶体管的Vgs发生变化，进而导致发光阶段的发光不稳定。
因此，为了消除电容结构在发光阶段对显示的影响，在本发明的具体实施例中，
所述电源输出控制单元为：第二薄膜晶体管T4；
所述电压跟随控制单元为：第三薄膜晶体管T3，用于在发光阶段导通所述驱动晶体管T5的源极和所述电容结构Cst的第二端，以将所述驱动晶体管T5的源极电压写入所述驱动晶体管T5的栅极。
所述第一写入控制单元为：第二薄膜晶体管T2，用于在写入阶段导通所述驱动晶体管的漏极和栅极，以将所述驱动晶体管T5的阈值电压写入所述电容结构Cst的第一端；
所述第二写入控制单元为：第一薄膜晶体管T1，用于在写入阶段导通所述数据信号输入端子和所述电容结构的第二端，以在写入阶段将数据信号写入所述电容结构Cst的第二端；
所述第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3和第四薄膜晶体管T4还在位于写入阶段和发光阶段之间的缓冲阶段截止。
通过该缓冲阶段的设置，使得电容结构在放电之后有一段时间可以回复到稳定状态，避免了电容结构自身的变化在发光阶段对驱动晶体管的栅极电压产生影响，进一步保证了发光器件在发光阶段的亮度一致性。
以下对本发明具体实施例的驱动电路详细说明如下。
结合图7所示，本发明具体实施例的驱动电路包括：
驱动晶体管T5，源极与发光器件连接；
电容结构Cst，第一端和所述驱动晶体管T5的栅极连接；
第一薄膜晶体管T1，源极连接数据信号输入端子DATA和电容结构Cst的第二端中的一个，漏极连接数据信号输入端子DATA和电容结构Cst的第二端中的另一个，栅极连接第一控制信号输入端子SCAN1；
第二薄膜晶体管T2，源极连接所述驱动晶体管T5的漏极和栅极中的一个，漏极连接所述驱动晶体管T5的漏极和栅极中的另一个，栅极连接第二控制信号输入端子SCAN2；
第三薄膜晶体管T3，源极连接所述驱动晶体管T5的源极和所述电容结构Cst的第二端中的一个，漏极连接所述驱动晶体管T5的源极和所述电容结构Cst的第二端中的另一个，栅极连接第三控制信号输入端子SCAN3；
第四薄膜晶体管T4，源极连接电源信号输入端子VDD和驱动晶体管T5的漏极中的一个，漏极连接电源信号输入端子VDD和驱动晶体管T5的漏极中的另一个，栅极连接第四控制信号输入端子SCAN4。
上述的第一、二、三、四控制信号以及数据信号的时序如图8所示。
以下结合图7和图8对本发明实施例的驱动电路的工作过程描述如下。
在复位阶段，此阶段，第一、二、四控制信号为高电平，第三控制信号为低电平；此时T1、T2、T4、T5导通，T3截止，其等效电路图如图9所示，此时数据信号施加到N1节点，而电源信号施加到N2节点，利用N1和N2节点的电压差为Cst充电。
充电结束后进入写入阶段，包括写入数据信号和T5的阈值电压。在此阶段，第一、二控制信号为高电平，第三、四控制信号为低电平，T1、T2和T5导通，T3和T4截止，其等效电路图如图10所示。
此时，N1节点的电压维持不变，而N2节点的电压会通过N2、N3、T5、发光器件这条通路放电至驱动晶体管T5的阈值电压Vth(T5)和发光器件的阈值电压Vth(发光器件)之和，实现了数据电压和驱动晶体管T5的阈值电压Vth(T5)的写入。
写入阶段结束后，进入缓冲阶段，所有的控制信号全处于低电平，所有的薄膜晶体管全部截止，其等效电路图如图11所示，结束后电容结构进入稳定状态。
缓冲结束后进入发光阶段，此阶段，第一、二控制信号为低电平，第三、四控制信号为高电平，T3、T4和T5导通，T1和T2截止，其等效电路图如图12所示。
其中，N1点的电压会从Vdata跳变为V工作，由于Cst的耦合效应，电荷总量不变的时候，N2点的电压会从Vth(发光器件)+Vth(T5)跳变为：
V工作-Vdata+Vth(发光器件)+Vth(T5)
因此驱动晶体管在发光阶段的Vgs为N2点的电压和N4点的电压之差，即：
V工作-Vdata+Vth(发光器件)+Vth(T5)-V工作＝Vth(发光器件)+Vth(T5)-Vdata
则流过发光器件的电流为：
0.5*μn*Cox*W/L*(Vgs-Vth(T5))2
即流过发光器件的电流为：
0.5*μn*Cox*W/L*(Vth(发光器件)-Vdata)2
可以发现，流过发光器件的电流不但与驱动晶体管的阈值电压无关，也和发光器件自身的工作电压无关，在实现阈值补偿的同时，消除了发光器件本身的电容特性对显示的影响。
为了更好地实现上述目的，本发明实施例还提供了一种像素结构，包括发光器件，还包括用于驱动所述发光器件的上述任意的像素驱动电路。
为了更好地实现上述目的，本发明实施例还提供了一种显示器件，包括上述的像素结构。
本发明实施例中的所采用的晶体管可以为薄膜晶体管或场效应管或其他特性的相同二极管，由于采用的晶体管的源极和漏极是对称的，所以其源极、漏极是没有区别的。
以上实施例中是以N型晶体管进行说明的，栅极输入高电平时，源漏极导通，P型晶体管相反。可以想到的是采用P型晶体管实现是本领域技术人员可以在不付出创造性劳动前提下轻易想到的，因此也是在本发明实施例的保护范围内的。
本发明实施例还提供了一种像素驱动方法，用于驱动像素结构中的发光器件，所述像素驱动方法包括：
电压跟随控制步骤，在发光阶段通过像素驱动电路中的电容结构控制像素驱动电路中的驱动晶体管的栅极的电压跟随所述驱动晶体管的源极的电压的变化。
上述的像素驱动方法，所述电压跟随控制步骤具体为：在发光阶段导通所述驱动晶体管的源极和所述电容结构的第二端。
上述的像素驱动方法，其特征在于，还包括：在写入阶段和发光阶段之间，断开所述电容结构与外部的电路连接，使得电容结构在放电之后有一段时间可以回复到稳定状态，避免了电容结构自身的变化在发光阶段对驱动晶体管的栅极电压产生影响，进一步保证了发光器件在发光阶段的亮度一致性。以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (12)

1.一种像素驱动电路，用于驱动像素结构中的发光器件，其特征在于，所述像素驱动电路包括：
驱动晶体管(T5)，源极与发光器件连接；
电容结构(Cst)，第一端和所述驱动晶体管(T5)的栅极连接；
第一写入控制单元，用于在写入阶段将所述驱动晶体管(T5)的阈值电压写入所述电容结构(Cst)的第一端；
第二写入控制单元，用于在写入阶段将数据信号写入所述电容结构(Cst)的第二端；
电源输出控制单元，用于在发光阶段输出电源信号到所述驱动晶体管(T5)的漏极；
电压跟随控制单元，用于通过所述电容结构(Cst)控制所述驱动晶体管(T5)的栅极的电压跟随所述驱动晶体管(T5)的源极的电压的变化。
2.根据权利要求1所述的像素驱动电路，其特征在于，所述电压跟随控制单元为：第三薄膜晶体管(T3)，用于在发光阶段导通所述驱动晶体管(T5)的源极和所述电容结构(Cst)的第二端。
3.根据权利要求1或2所述的像素驱动电路，其特征在于，所述第一写入控制单元为：第二薄膜晶体管(T2)，用于在写入阶段导通所述驱动晶体管(T5)的漏极和栅极，以将所述驱动晶体管(T5)的阈值电压写入所述电容结构(Cst)的第一端。
4.根据权利要求1或2所述的像素驱动电路，其特征在于，所述第二写入控制单元为：第一薄膜晶体管(T1)，用于在写入阶段导通所述数据信号输入端子和所述电容结构(Cst)的第二端，以将在写入阶段将数据信号写入所述电容结构(Cst)的第二端。
5.根据权利要求1或2所述的像素驱动电路，其特征在于：
所述电源输出控制单元为：第二薄膜晶体管(T4)；
所述第一写入控制单元为：第二薄膜晶体管(T2)，用于在写入阶段导通所述驱动晶体管(T5)的漏极和栅极，以将所述驱动晶体管(T5)的阈值电压写入所述电容结构(Cst)的第一端；
所述第二写入控制单元为：第一薄膜晶体管(T1)，用于在写入阶段导通所述数据信号输入端子和所述电容结构(Cst)的第二端，以将在写入阶段将数据信号写入所述电容结构(Cst)的第二端；
所述第一薄膜晶体管(T1)、第二薄膜晶体管(T2)和第四薄膜晶体管(T4)还在复位阶段导通，以利用所述电源信号和所述数据信号对所述电容结构(Cst)进行充电。
6.根据权利要求2所述的像素驱动电路，其特征在于：
所述电源输出控制单元为：第二薄膜晶体管(T4)；
所述第一写入控制单元为：第二薄膜晶体管(T2)，用于在写入阶段导通所述驱动晶体管(T5)的漏极和栅极，以将所述驱动晶体管(T5)的阈值电压写入所述电容结构(Cst)的第一端；
所述第二写入控制单元为：第一薄膜晶体管(T1)，用于在写入阶段导通所述数据信号输入端子和所述电容结构(Cst)的第二端，以将在写入阶段将数据信号写入所述电容结构(Cst)的第二端；
所述第一薄膜晶体管(T1)、第二薄膜晶体管(T2)、第三薄膜晶体管(T3)和第四薄膜晶体管(T4)还在位于写入阶段和发光阶段之间的缓冲阶段截止。
7.根据权利要求1或2所述的像素驱动电路，其特征在于，所述发光器件为电致变色显示器件。
8.一种像素结构，包括发光器件，其特征在于，还包括如权利要求1-7中任意一项所述的用于驱动所述发光器件的所述像素驱动电路。
9.一种显示器件，包括如权利要求8所述的像素结构。
10.一种像素驱动方法，用于驱动像素结构中的发光器件，其特征在于，所述像素驱动方法包括：
电压跟随控制步骤，在发光阶段通过像素驱动电路中的电容结构控制像素驱动电路中的驱动晶体管的栅极的电压跟随所述驱动晶体管的源极的电压的变化。
11.根据权利要求10所述的像素驱动方法，其特征在于，所述电压跟随控制步骤具体为：在发光阶段导通所述驱动晶体管的源极和所述电容结构的第二端。
12.根据权利要求11所述的像素驱动方法，其特征在于，还包括：
在写入阶段和发光阶段之间，断开所述电容结构与外部的电路连接。
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