CN105355617A - 一种裸芯片技术中增强焊线牢靠度的结构及其方法 - Google Patents

一种裸芯片技术中增强焊线牢靠度的结构及其方法 Download PDF

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CN105355617A
CN105355617A CN201510836141.1A CN201510836141A CN105355617A CN 105355617 A CN105355617 A CN 105355617A CN 201510836141 A CN201510836141 A CN 201510836141A CN 105355617 A CN105355617 A CN 105355617A
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wiring board
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盛梅
蔡志嘉
陶燕兵
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JIANGSU AMICC OPTOELECTRONICS TECHNOLOGY Co Ltd
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    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/48996Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
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Abstract

本发明公开了一种裸芯片技术中增强焊线牢靠度的结构及其方法,属于COB封装裸片绑定领域,将一根辅助金属丝线的一端焊接在所述焊接主节点上,另外一端焊接在所述PCB印制线路板的焊接辅助节点上;解决了COB封装的电子元件长期的运用过程中内部引线容易发生断开脱落的问题,使COB内部引线更加牢固、防震,并且使加工过以后的PCB印制线路板能适应更大的温差变化和户外一些极端环境,增加了电子产品的寿命,并且由于本发明带有辅助金属丝线,所以加工的PCB印制线路板其焊接节点的接触性好,防干扰能力强,使电子产品具有更好了性能和经济效益。

Description

一种裸芯片技术中增强焊线牢靠度的结构及其方法
技术领域
本发明属于COB封装裸片绑定领域。
背景技术
板上芯片(ChipOnBoard,COB)工艺过程首先是在基底表面用导热环氧树脂(一般用掺银颗粒的环氧树脂)覆盖硅片安放点,然后将硅片直接安放在基底表面,热处理至硅片牢固地固定在基底为止,随后再用丝焊的方法在硅片和基底之间直接建立电气连接。
在COB和LED封装过程中,需要焊接导线将芯片进行连接导通,但是焊接的导线在长期的运用过程中最容易发生断开脱落现象,导致芯片不再导通,从而使整个线路板失去作用。就目前状况而已,最主要的失效就是导线的断裂和脱落,导致电子产品功能的丧失,特别是在户外等极端环境下的电子产品,这样的问题尤其突出。
发明内容
本发明的目的是提供一种裸芯片技术中增强焊线牢靠度的结构及其方法,通过在主节点上增加辅助金属线的方法来加固焊接的牢靠性。
为实现上述目的,本发明采用一下技术方案:一种裸芯片技术中增强焊线牢靠度的方法,包括如下步骤:
步骤1:用点胶机在PCB印制线路板上的COB封装裸片的预留位置上点上胶水;
步骤2:用防静电设备将COB封装裸片放在胶水上;
步骤3:将粘好COB封装裸片的PCB印制线路板放在烘箱中恒温静置一段时间固化;
步骤4:将固化好的所述PCB印制线路板取出,并采用金属丝线焊接机进行COB封装裸片的绑定,在绑定时按照如下步骤:
A.将主金属丝线的一端焊接在所述COB封装裸片的电极上,再将所述主金属丝线的另外一端焊接在所述PCB印制线路板的焊接主节点上;
B.将一根辅助金属丝线的一端焊接在所述焊接主节点上、另外一端焊接在所述PCB印制线路板的焊接辅助节点上。
所述焊接辅助节点设在所述焊接主节点的旁边。
一种裸芯片技术中增强焊线牢靠度的结构,包括COB封装裸片、PCB印制线路板、主金属丝线和辅助金属丝线;PCB印制线路板上设有焊接主节点和焊接辅助节点,COB封装裸片用胶水粘接在PCB印制线路板上,主金属丝线的一端焊接在所述COB封装裸片的电极上、另外一端焊接在焊接主节点上;辅助金属丝线的一端焊接在所述焊接主节点上、另外一端焊接在焊接辅助节点上。
所述焊接辅助节点设在所述焊接主节点的旁边。
本发明所述的一种裸芯片技术中增强焊线牢靠度的结构及其方法,解决了COB封装的电子元件长期的运用过程中内部引线容易发生断开脱落的问题,使COB内部引线更加牢固、防震,并且使加工过以后的PCB印制线路板能适应更大的温差变化和户外一些极端环境,增加了电子产品的寿命,并且通过本发明所加工的PCB印制线路板其焊接节点的接触性好,防干扰能力强,使电子产品具有更好了性能和经济效益。
附图说明
图1是本发明的芯片固定示意图;
图2是本发明的芯片绑定示意图;
图3是本发明的焊线固定示意图;
图中:COB封装裸片1、PCB印制线路板2、主金属丝线3、辅助金属丝线4、焊接主节点5、焊接辅助节点6。
具体实施方式
一种裸芯片技术中增强焊线牢靠度的方法,包括如下步骤:
如图1所示,步骤1:用点胶机在PCB印制线路板2上的对应COB封装裸片1的预留位置上适量的点上胶水;
步骤2:用防静电设备将COB封装裸片1正确的放在胶水上;
步骤3:将粘好COB封装裸片1的PCB印制线路板2放在烘箱中恒温静置一段时间固化;为下边COB封装裸片1的绑定创造条件。
步骤4:如图2所示:将固化好的所述PCB印制线路板2取出,并采用金属丝线焊接机进行COB封装裸片1绑定,在绑定时按照如下步骤:
A.将主金属丝线3的一端焊接在所述COB封装裸片1的电极上,再将所述主金属丝线3的另外一端焊接在所述PCB印制线路板2的焊接主节点5上;
B.如图3所示:将一根辅助金属丝线4的一端焊接在所述焊接主节点5上、另外一端焊接在所述PCB印制线路板2的焊接辅助节点6上,所述焊接辅助节点6间隔设在所述焊接主节点5的旁边。这样就解决了COB封装的电子元件长期的运用过程中内部引线容易发生断开脱落的问题,使COB内部引线更加牢固、防震,并且使加工过以后的PCB印制线路板能适应更大的温差变化和户外一些极端环境,增加了电子产品的寿命,并且由于本发明带有辅助金属丝线,所以加工的PCB印制线路板其焊接节点的接触性好,防干扰能力强,使电子产品具有更好了性能和经济效益。
由图1-图3所示的一种裸芯片技术中增强焊线牢靠度的结构,是通过一种裸芯片技术中增强焊线牢靠度的方法实现的结构,其包括COB封装裸片1、PCB印制线路板2、主金属丝线3和辅助金属丝线4;PCB印制线路板2上设有焊接主节点5和焊接辅助节点6,COB封装裸片1用胶水粘接在PCB印制线路板2上,主金属丝线3的一端焊接在所述COB封装裸片1的电极上、另外一端焊接在焊接主节点5上;辅助金属丝线4的一端焊接在所述焊接主节点5上、另外一端焊接在焊接辅助节点6上。所述焊接辅助节点6间隔设在所述焊接主节点5的旁边。

Claims (4)

1.一种裸芯片技术中增强焊线牢靠度的方法,其特征在于:包括如下步骤:
步骤1:用点胶机在PCB印制线路板(2)上的COB封装裸片(1)的预留位置上点上胶水;
步骤2:用防静电设备将COB封装裸片(1)放在胶水上;
步骤3:将粘好COB封装裸片(1)的PCB印制线路板(2)放在烘箱中恒温静置一段时间固化;
步骤4:将固化好的所述PCB印制线路板(2)取出,并采用金属丝线焊接机进行COB封装裸片(1)的绑定,在绑定时按照如下步骤:
A.将主金属丝线(3)的一端焊接在所述COB封装裸片(1)的电极上,再将所述主金属丝线(3)的另外一端焊接在所述PCB印制线路板(2)的焊接主节点(5)上;
B.将一根辅助金属丝线(4)的一端焊接在所述焊接主节点(5)上、另外一端焊接在所述PCB印制线路板(2)的焊接辅助节点(6)上。
2.如权利要求1所述的一种裸芯片技术中增强焊线牢靠度的方法,其特征在于:所述焊接辅助节点(6)设在所述焊接主节点(5)的旁边。
3.一种裸芯片技术中增强焊线牢靠度的结构,其特征在于:包括COB封装裸片(1)、PCB印制线路板(2)、主金属丝线(3)和辅助金属丝线(4);PCB印制线路板(2)上设有焊接主节点(5)和焊接辅助节点(6),COB封装裸片(1)用胶水粘接在PCB印制线路板(2)上,主金属丝线(3)的一端焊接在所述COB封装裸片(1)的电极上、另外一端焊接在焊接主节点(5)上;辅助金属丝线(4)的一端焊接在所述焊接主节点(5)上、另外一端焊接在焊接辅助节点(6)上。
4.如权利要求3所述的一种裸芯片技术中增强焊线牢靠度的结构,其特征在于:所述焊接辅助节点(6)设在所述焊接主节点(5)的旁边。
CN201510836141.1A 2015-11-25 2015-11-25 一种裸芯片技术中增强焊线牢靠度的结构及其方法 Pending CN105355617A (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106784242A (zh) * 2016-12-27 2017-05-31 佛山市国星光电股份有限公司 Led器件、led灯及加工led器件导电焊线的方法
CN113035817A (zh) * 2019-12-25 2021-06-25 上海凯虹科技电子有限公司 一种封装体

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54142066A (en) * 1978-04-27 1979-11-05 Toshiba Corp Wire bonding method for semiconductor device
JPS6310535A (ja) * 1986-06-30 1988-01-18 ロ−ベルト・ボツシユ・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング 半導体構造要素内の電気的接続の製作方法
CN101160649A (zh) * 2005-04-15 2008-04-09 罗姆股份有限公司 半导体装置及半导体装置的制造方法
JP2009188236A (ja) * 2008-02-07 2009-08-20 Panasonic Corp ワイヤボンディング接続構造およびワイヤボンディング方法
CN103311142A (zh) * 2013-06-21 2013-09-18 深圳市振华微电子有限公司 封装结构及其封装工艺

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54142066A (en) * 1978-04-27 1979-11-05 Toshiba Corp Wire bonding method for semiconductor device
JPS6310535A (ja) * 1986-06-30 1988-01-18 ロ−ベルト・ボツシユ・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング 半導体構造要素内の電気的接続の製作方法
CN101160649A (zh) * 2005-04-15 2008-04-09 罗姆股份有限公司 半导体装置及半导体装置的制造方法
JP2009188236A (ja) * 2008-02-07 2009-08-20 Panasonic Corp ワイヤボンディング接続構造およびワイヤボンディング方法
CN103311142A (zh) * 2013-06-21 2013-09-18 深圳市振华微电子有限公司 封装结构及其封装工艺

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106784242A (zh) * 2016-12-27 2017-05-31 佛山市国星光电股份有限公司 Led器件、led灯及加工led器件导电焊线的方法
CN113035817A (zh) * 2019-12-25 2021-06-25 上海凯虹科技电子有限公司 一种封装体

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