CN105304746A - Heterojunction solar cell and preparation method thereof - Google Patents
Heterojunction solar cell and preparation method thereof Download PDFInfo
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- CN105304746A CN105304746A CN201510622094.0A CN201510622094A CN105304746A CN 105304746 A CN105304746 A CN 105304746A CN 201510622094 A CN201510622094 A CN 201510622094A CN 105304746 A CN105304746 A CN 105304746A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 42
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 315
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 315
- 239000010703 silicon Substances 0.000 claims abstract description 315
- 230000008021 deposition Effects 0.000 claims abstract description 62
- 239000013078 crystal Substances 0.000 claims description 185
- 239000012528 membrane Substances 0.000 claims description 120
- 238000000151 deposition Methods 0.000 claims description 72
- 238000004140 cleaning Methods 0.000 claims description 67
- 238000000034 method Methods 0.000 claims description 56
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 24
- 239000012530 fluid Substances 0.000 claims description 21
- 235000008216 herbs Nutrition 0.000 claims description 15
- 210000002268 wool Anatomy 0.000 claims description 15
- 239000011248 coating agent Substances 0.000 claims description 14
- 238000000576 coating method Methods 0.000 claims description 14
- 238000007650 screen-printing Methods 0.000 claims description 13
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 10
- 238000002161 passivation Methods 0.000 abstract description 17
- 238000011109 contamination Methods 0.000 abstract description 12
- 229910021419 crystalline silicon Inorganic materials 0.000 abstract description 12
- 238000006243 chemical reaction Methods 0.000 abstract description 11
- 239000010409 thin film Substances 0.000 abstract description 9
- 230000005540 biological transmission Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 25
- 239000002019 doping agent Substances 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 13
- 230000002000 scavenging effect Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000000427 thin-film deposition Methods 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003344 environmental pollutant Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 231100000719 pollutant Toxicity 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
- H01L31/074—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a heterojunction with an element of Group IV of the Periodic System, e.g. ITO/Si, GaAs/Si or CdTe/Si solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02096—Cleaning only mechanical cleaning
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a heterojunction solar cell and a preparation method thereof, and aims at removing contamination and the oxide layer on the surface of a crystalline silicon wafer and silicon thin film layers in the transmission process so that passivation quality of the surface of the crystalline silicon wafer is enhanced and the fill factor and conversion efficiency of the cell are enhanced. The preparation method of the heterojunction solar cell comprises the steps that a first silicon thin film layer is deposited on the surface of the first side of the crystalline silicon wafer, and a second silicon thin film layer is deposited on the surface of the second side of the crystalline silicon wafer; and the first silicon thin film layer and the surface of the second side of the crystalline silicon wafer are cleaned before deposition of the second silicon thin film layer on the surface of the second side of the crystalline silicon wafer, and/or the first silicon thin film layer and the second silicon thin film layer are cleaned after deposition of the second silicon thin film layer on the surface of the second side of the crystalline silicon wafer.
Description
Technical field
The present invention relates to heterojunction solar battery technical field, particularly relate to a kind of heterojunction solar battery and preparation method thereof.
Background technology
Along with the development in photovoltaic industry and market thereof, the heterojunction solar cell of exploitation high efficiency, low cost becomes main direction of studying.Amorphous silicon hydride (a-Si:H)/crystalline silicon (c-Si) heterojunction solar battery combines the advantage of crystalline silicon and thin film silicon technology, both make use of the thin film deposition processes of low temperature, play again the advantage of crystalline silicon high mobility, there is the characteristics such as preparation technology is simple, conversion efficiency is high simultaneously.
Existing heterojunction solar battery preparation technology flow process as shown in Figure 1, comprise: crystal silicon chip making herbs into wool cleaning 102, first intrinsic layer I layer deposition 104, doped layer P (or N) layer deposition 106, second intrinsic layer I layer deposition 108, doped layer N (or P) layer deposition 110, nesa coating deposition 112, silk screen printing 114, annealing 116, wherein, in depositing operation, crystal silicon chip needs to be sent in dissimilar thin film deposition chamber, in transport process, crystalline silicon sector-meeting contacts with pallet or substrate, impurity on pallet or substrate or pollutant easily adhere on crystal silicon chip, thus contamination is produced to crystal silicon chip, reduce the passivation quality on crystal silicon chip surface, meanwhile, in transport process, crystal silicon chip is exposed in air, is easy to oxidized and produces oxide layer on crystal silicon chip surface, reducing the passivation quality on crystal silicon chip surface, thus reducing the fill factor, curve factor of battery, also making the decrease in yield of battery.
In sum, in existing silicon based hetero-junction solar cell preparation technology flow process, in depositing operation, when crystal silicon chip transmits between multiple deposition chambers, contact with pallet or substrate, easily stain, and be exposed to easy oxidized formation oxide layer in air, reduce the passivation quality on crystal silicon chip surface, thus reduce the fill factor, curve factor of battery, cause the decrease in yield of battery.
Summary of the invention
Embodiments provide a kind of heterojunction solar battery and preparation method thereof, in order to remove contamination on the surface of crystal silicon chip in transport process and silicon membrane layer and oxide layer, improve the passivation quality on crystal silicon chip surface, promote fill factor, curve factor and the conversion efficiency of battery.
The preparation method of a kind of heterojunction solar battery that the embodiment of the present invention provides, comprising: deposit the first silicon membrane layer at crystal silicon chip first side surface, deposits the second silicon membrane layer at crystal silicon chip second side surface; Before described crystal silicon chip second side surface deposits the second silicon membrane layer, described first silicon membrane layer and described crystal silicon chip second side surface are cleaned, and/or after described crystal silicon chip second side surface deposits the second silicon membrane layer, described first silicon membrane layer and described second silicon membrane layer are cleaned, wherein, the first side surface of described crystal silicon chip is relative with the second side surface.
In the said method that the embodiment of the present invention provides, before crystal silicon chip second side surface deposits the second silicon membrane layer, first silicon membrane layer and crystal silicon chip second side surface are cleaned, and/or after crystal silicon chip second side surface deposits the second silicon membrane layer, first silicon membrane layer and the second silicon membrane layer are cleaned, contamination and the oxide layer on the first silicon membrane layer surface and crystal silicon chip second side surface and/or the second silicon membrane layer surface in transport process can be removed, and when in prior art, crystal silicon chip transmits between multiple deposition chambers, compare because not causing the surface passivation quality of crystal silicon chip to reduce to crystal silicon chip cleaning, improve the passivation quality on crystal silicon chip surface, simultaneously for subsequent technique provides a surface more cleaned, improve transparent conductive film layer and the first silicon membrane layer, interface performance between transparent conductive film layer and the second silicon membrane layer, thus promote fill factor, curve factor and the conversion efficiency of battery.
In a kind of possible execution mode, in the said method that the embodiment of the present invention provides, the cleaning fluid used during cleaning comprises: hydrofluoric acid solution and hydrogen peroxide solution.
In a kind of possible execution mode, in the said method that the embodiment of the present invention provides, in described cleaning fluid, the concentration of hydrofluoric acid solution is more than or equal to 0.5% and is less than or equal to 5%.
In a kind of possible execution mode, in the said method that the embodiment of the present invention provides, in described cleaning fluid, the concentration of hydrofluoric acid solution is more than or equal to 1% and is less than or equal to 2%.
In a kind of possible execution mode, in the said method that the embodiment of the present invention provides, in described cleaning fluid, the concentration of hydrogen peroxide solution is more than or equal to 0.5% and is less than or equal to 5%.
In a kind of possible execution mode, in the said method that the embodiment of the present invention provides, in described cleaning fluid, the concentration of hydrogen peroxide solution is more than or equal to 1% and is less than or equal to 2%.
In a kind of possible execution mode, in the said method that the embodiment of the present invention provides, the time of cleaning is more than or equal to 1 minute and is less than or equal to 10 minutes.
In a kind of possible execution mode, in the said method that the embodiment of the present invention provides, the time of described cleaning is more than or equal to 2 minutes and is less than or equal to 8 minutes.
In a kind of possible execution mode, in the said method that the embodiment of the present invention provides, the time of described cleaning is more than or equal to 3 minutes and is less than or equal to 6 minutes.
In a kind of possible execution mode, in the said method that the embodiment of the present invention provides, before crystal silicon chip first side surface deposits the first silicon membrane layer, the method also comprises: carry out making herbs into wool cleaning to described crystal silicon chip; After crystal silicon chip second side surface deposits the second silicon membrane layer or after described first silicon membrane layer and described second silicon membrane layer are cleaned, the method also comprises: at described first silicon membrane layer surface and described second silicon membrane layer surface deposition nesa coating, and carry out silk screen printing and annealing in process to the crystal silicon chip after deposition of transparent conductive film.
In a kind of possible execution mode, in the said method that the embodiment of the present invention provides, describedly deposit the first silicon membrane layer at crystal silicon chip first side surface, comprise: deposit the first intrinsic layer I layer and doped layer P layer successively at crystal silicon chip first side surface, or deposit the first intrinsic layer I layer and doped layer N layer successively at crystal silicon chip first side surface.
In a kind of possible execution mode, in the said method that the embodiment of the present invention provides, when depositing the first intrinsic layer I layer and doped layer P layer successively at crystal silicon chip first side surface, describedly deposit the second silicon membrane layer at crystal silicon chip second side surface, comprising: deposit the second intrinsic layer I layer and doped layer N layer successively at crystal silicon chip second side surface; And when depositing the first intrinsic layer I layer and doped layer N layer successively at crystal silicon chip first side surface, describedly deposit the second silicon membrane layer at crystal silicon chip second side surface, comprising: deposit the second intrinsic layer I layer and doped layer P layer successively at crystal silicon chip second side surface.
A kind of heterojunction solar battery that the embodiment of the present invention provides, comprising: described heterojunction solar battery adopts the preparation method described in the above embodiment of the present invention to be prepared from.
The heterojunction solar battery that the embodiment of the present invention provides, the preparation method adopting the above embodiment of the present invention to provide is prepared from, also namely before crystal silicon chip second side surface deposits the second silicon membrane layer, first silicon membrane layer and crystal silicon chip second side surface are cleaned, and/or after crystal silicon chip second side surface deposits the second silicon membrane layer, first silicon membrane layer and the second silicon membrane layer are cleaned, contamination and the oxide layer on the first silicon membrane layer surface and crystal silicon chip second side surface and/or the second silicon membrane layer surface in transport process can be removed, and when in prior art, crystal silicon chip transmits between multiple deposition chambers, compare because not causing the surface passivation quality of crystal silicon chip to reduce to crystal silicon chip cleaning, improve the passivation quality on crystal silicon chip surface, simultaneously for subsequent technique provides a surface more cleaned, improve transparent conductive film layer and the first silicon membrane layer, interface performance between transparent conductive film layer and the second silicon membrane layer, thus promote fill factor, curve factor and the conversion efficiency of battery.
Accompanying drawing explanation
Fig. 1 is the schematic flow diagram of heterojunction solar battery preparation technology in prior art;
The schematic flow diagram of the preparation method of a kind of heterojunction solar battery that Fig. 2 provides for the embodiment of the present invention;
The schematic flow diagram of a kind of execution mode of the preparation method of the heterojunction solar battery that Fig. 3 provides for the embodiment of the present invention;
The schematic flow diagram of the another kind of execution mode of the preparation method of the heterojunction solar battery that Fig. 4 provides for the embodiment of the present invention;
Another execution mode schematic flow diagram of the preparation method of the heterojunction solar battery that Fig. 5 provides for the embodiment of the present invention;
The structural representation of a kind of heterojunction solar battery that Fig. 6 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the embodiment of a kind of heterojunction solar battery that the embodiment of the present invention provides and preparation method thereof is described in detail.
It should be noted that, to the cleaning that the first silicon membrane layer and crystal silicon chip second side surface carry out in the embodiment of the present invention, and/or the cleaning cleaning that the first silicon membrane layer and the second silicon membrane layer carry out is different from crystal silicon chip making herbs into wool cleaning, cleaning in crystal silicon chip making herbs into wool cleaning mainly adopts different cleaning fluid point multistep to remove organic substance on crystal silicon chip surface, metallic pollution and oxide, and the cleaning that the first silicon membrane layer and crystal silicon chip second side surface are carried out mentioned in the embodiment of the present invention, and/or the cleaning that the first silicon membrane layer and the second silicon membrane layer carry out only is adopted to a kind of cleaning fluid and only has a step, clean by surface deposition have the crystal silicon chip of the first silicon membrane layer and/or the second silicon membrane layer to be immersed in cleaning fluid that the embodiment of the present invention provides, its object is to remove contamination and the oxide layer on the first silicon membrane layer surface and crystal silicon chip second side surface and/or the second silicon membrane layer surface in transport process.
The preparation method of a kind of heterojunction solar battery that the embodiment of the present invention provides, as shown in Figure 2, comprising:
Step 202, deposits the first silicon membrane layer at crystal silicon chip first side surface, deposits the second silicon membrane layer at crystal silicon chip second side surface;
Step 204, before crystal silicon chip second side surface deposits the second silicon membrane layer, first silicon membrane layer and crystal silicon chip second side surface are cleaned, and/or after crystal silicon chip second side surface deposits the second silicon membrane layer, first silicon membrane layer and the second silicon membrane layer are cleaned, wherein, the first side surface of crystal silicon chip is relative with the second side surface.
In the method that the embodiment of the present invention provides, before crystal silicon chip second side surface deposits the second silicon membrane layer, first silicon membrane layer and crystal silicon chip second side surface are cleaned, and/or after crystal silicon chip second side surface deposits the second silicon membrane layer, first silicon membrane layer and the second silicon membrane layer are cleaned, contamination and the oxide layer on the first silicon membrane layer surface and crystal silicon chip second side surface and/or the second silicon membrane layer surface in transport process can be removed, and when in prior art, crystal silicon chip transmits between multiple deposition chambers, compare because not causing the surface passivation quality of crystal silicon chip to reduce to crystal silicon chip cleaning, improve the passivation quality on crystal silicon chip surface, simultaneously for subsequent technique provides a surface more cleaned, improve transparent conductive film layer and the first silicon membrane layer, interface performance between transparent conductive film layer and the second silicon membrane layer, thus promote fill factor, curve factor and the conversion efficiency of battery.
What deserves to be explained is, silicon membrane layer comprises intrinsic layer I layer and doped layer P (or N) layer, first silicon membrane layer can be the first intrinsic layer I layer and doped layer P layer that deposit successively, then the second silicon membrane layer is the second intrinsic layer I layer and doped layer N layer that deposit successively, certainly, those skilled in the art should be understood that, first silicon membrane layer also can be the first intrinsic layer I layer and doped layer N layer that deposit successively, then the second silicon membrane layer is the second intrinsic layer I layer and doped layer P layer that deposit successively.Wherein, the first intrinsic layer I is deposited upon crystal silicon chip first side surface, and the second intrinsic layer I is deposited upon crystal silicon chip second side surface, and the first intrinsic layer I layer and the second intrinsic layer I layer are only used to the intrinsic layer I layer distinguishing crystal silicon chip both side surface.
During concrete enforcement, the preparation method of the heterojunction solar battery that the embodiment of the present invention provides can be divided into following three kinds of concrete execution modes.
Execution mode one, before crystal silicon chip second side surface deposits the second silicon membrane layer, the first silicon membrane layer and crystal silicon chip second side surface to be cleaned.Below in conjunction with the preparation technology of heterojunction solar battery, this execution mode is described in detail.As shown in Figure 3, the preparation technology of heterojunction solar battery, comprising:
Step 302, crystal silicon chip making herbs into wool is cleaned, and also namely carries out making herbs into wool cleaning to crystal silicon chip, removes organic substance, metallic pollution and oxide on crystal silicon chip surface;
Step 304, the first intrinsic layer I layer deposition, crystal silicon chip first side surface also namely after making herbs into wool cleaning deposits the first intrinsic layer I layer;
Step 306, doped layer P (or N) layer deposits, also i.e. dopant deposition layer P (or N) layer on the first intrinsic layer I layer;
Step 308, cleaning, also namely the first intrinsic layer I layer and doped layer P (or N) layer is deposited successively at crystal silicon chip first side surface, after crystal silicon chip being sent to the deposition chambers for depositing the second intrinsic layer I layer, before crystal silicon chip second side surface deposits the second intrinsic layer I layer, doped layer P (or N) layer and crystal silicon chip second side surface are cleaned;
Step 310, the second intrinsic layer I layer deposition, also namely after cleaning doped layer P (or N) layer and crystal silicon chip second side surface, deposits the second intrinsic layer I layer at crystal silicon chip second side surface;
Step 312, doped layer N (or P) layer deposits, also i.e. dopant deposition layer N (or P) layer on the second intrinsic layer I layer;
Step 314, nesa coating deposits, also namely at doped layer P layer surface and doped layer N layer surface deposition nesa coating;
Step 316, silk screen printing, the crystal silicon chip that also namely effects on surface deposits nesa coating carries out silk screen printing;
Step 318, namely annealing, also carry out annealing in process to the crystal silicon chip after silk screen printing.
Wherein, clean doped layer P (or N) layer and crystal silicon chip second side surface in step 308, carry out under normal temperature condition, the cleaning fluid of employing comprises: hydrofluoric acid solution (HF solution) and hydrogen peroxide solution (H
2o
2solution), the concentration of HF solution is 0.5%-5%, and comparatively preferably, the concentration of HF solution is the concentration of 1%-2%, HF solution can also be 1.0%, 2.0%, 3.0%, 4.0%, 4.5%; H
2o
2the concentration of solution is 0.5%-5%, comparatively preferably, and H
2o
2the concentration of solution is 1%-2%, H
2o
2the concentration of solution can also be 1.0%, 2.0%, 3.0%, 4.0%, 4.5%, the time of cleaning can be 1 minute-10 minutes (min), comparatively preferably, scavenging period is 2min-8min, more preferably, scavenging period is 3min-6min, and scavenging period can also be 2min, 4min, 5min, 6min, 7min, 9min.
The first intrinsic layer I layer and doped layer P (or N) layer is deposited successively at crystal silicon chip first side surface, after crystal silicon chip being sent to the deposition chambers for depositing the second intrinsic layer I layer, before crystal silicon chip second side surface deposits the second intrinsic layer I layer, use HF solution and H
2o
2solution cleans doped layer P (or N) layer and crystal silicon chip second side surface, and HF solution effectively can remove the oxide layer of doped layer P (or N) layer surface and crystal silicon chip second side surface, H
2o
2solution effectively can remove the contamination of doped layer P (or N) layer surface and crystal silicon chip second side surface, thus improve the passivation quality of doped layer P (or N) layer surface and crystal silicon chip second side surface, simultaneously for subsequent technique provides a surface more cleaned, promote the interface performance improved between transparent conductive film layer and doped layer P (or N) layer, promote open circuit voltage and the fill factor, curve factor of solar cell, promote battery performance.Experiment shows, uses HF solution and H
2o
2solution cleans doped layer P (or N) layer and crystal silicon chip second side surface, the open circuit voltage Voc of solar cell can be made to rise to 720mV from 715mV, fill factor, curve factor FF rises to 74.5% from 73.3%, and conversion efficiency Eff rises to 20.5% from 20.2.
Execution mode two, after crystal silicon chip second side surface deposits the second silicon membrane layer, the first silicon membrane layer and the second silicon membrane layer to be cleaned.Below in conjunction with the preparation technology of heterojunction solar battery, this execution mode is described in detail.As shown in Figure 4, the preparation technology of heterojunction solar battery, comprising:
Step 402, crystal silicon chip making herbs into wool is cleaned, and also namely carries out making herbs into wool cleaning to crystal silicon chip, removes organic substance, metallic pollution and oxide on crystal silicon chip surface;
Step 404, the first intrinsic layer I layer deposition, crystal silicon chip first side surface also namely after making herbs into wool cleaning deposits the first intrinsic layer I layer;
Step 406, doped layer P (or N) layer deposits, also i.e. dopant deposition layer P (or N) layer on the first intrinsic layer I layer;
Step 408, namely the second intrinsic layer I layer deposition, also deposit the second intrinsic layer I layer at crystal silicon chip second side surface;
Step 410, doped layer N (or P) layer deposits, also i.e. dopant deposition layer N (or P) layer on the second intrinsic layer I layer;
Step 412, cleaning, also namely at crystal silicon chip first side surface dopant deposition layer P layer, crystal silicon chip second side surface dopant deposition layer N layer, surface deposition had after the crystal silicon chip of doped layer P layer and doped layer N layer is sent to the deposition chambers for deposition of transparent conductive film layer, before doped layer P layer surface and doped layer N layer surface deposition transparent conductive film layer, doped layer P layer and doped layer N layer are cleaned;
Step 414, nesa coating deposits, also namely after cleaning doped layer P layer and doped layer N layer, at doped layer P layer surface and doped layer N layer surface deposition nesa coating;
Step 416, silk screen printing, the crystal silicon chip that also namely effects on surface deposits nesa coating carries out silk screen printing;
Step 418, namely annealing, also carry out annealing in process to the crystal silicon chip after silk screen printing.
Wherein, clean doped layer P layer and doped layer N layer in step 412, carry out under normal temperature condition, the cleaning fluid of employing comprises: hydrofluoric acid solution (HF solution) and hydrogen peroxide solution (H
2o
2solution), the concentration of HF solution is 0.5%-5%, and comparatively preferably, the concentration of HF solution is the concentration of 1%-2%, HF solution can also be 1.0%, 2.0%, 3.0%, 4.0%, 4.5%; H
2o
2the concentration of solution is 0.5%-5%, comparatively preferably, and H
2o
2the concentration of solution is 1%-2%, H
2o
2the concentration of solution can also be 1.0%, 2.0%, 3.0%, 4.0%, 4.5%, the time of cleaning can be 1 minute-10 minutes (min), comparatively preferably, scavenging period is 2min-8min, more preferably, scavenging period is 3min-6min, and scavenging period can also be 2min, 4min, 5min, 6min, 7min, 9min.
At crystal silicon chip first side surface dopant deposition layer P layer, crystal silicon chip second side surface dopant deposition layer N layer, surface deposition had after the crystal silicon chip of doped layer P layer and doped layer N layer is sent to the deposition chambers for deposition of transparent conductive film layer, before doped layer P layer surface and doped layer N layer surface deposition transparent conductive film layer, use HF solution and H
2o
2solution cleans doped layer P layer and doped layer N layer, and HF solution effectively can remove the oxide layer on doped layer P layer surface and doped layer N layer surface, H
2o
2solution effectively can remove the contamination on doped layer P layer surface and doped layer N layer surface, thus improve the passivation quality of doped layer P layer surface and doped layer N layer, simultaneously for subsequent technique provides a surface more cleaned, promote to improve transparent conductive film layer and doped layer P layer surface, interface performance between transparent conductive film layer and doped layer N layer surface, promote open circuit voltage and the fill factor, curve factor of solar cell, promote battery performance.Experiment shows, uses HF solution and H
2o
2solution cleans doped layer P layer and doped layer N layer, and the open circuit voltage Voc of solar cell can be made to rise to 720mV from 715mV, and fill factor, curve factor FF rises to 74.5% from 73.3%, and conversion efficiency Eff rises to 20.5% from 20.2.
Execution mode three, before crystal silicon chip second side surface deposits the second silicon membrane layer, first silicon membrane layer and crystal silicon chip second side surface are cleaned, then the second silicon membrane layer is deposited at crystal silicon chip second side surface, after crystal silicon chip second side surface deposits the second silicon membrane layer, secondary cleaning is carried out to the first silicon membrane layer and the second silicon membrane layer.Below in conjunction with the preparation technology of heterojunction solar battery, this execution mode is described in detail.As shown in Figure 5, the preparation technology of heterojunction solar battery, comprising:
Step 502, crystal silicon chip making herbs into wool is cleaned, and also namely carries out making herbs into wool cleaning to crystal silicon chip, removes organic substance, metallic pollution and oxide on crystal silicon chip surface;
Step 504, the first intrinsic layer I layer deposition, crystal silicon chip first side surface also namely after making herbs into wool cleaning deposits the first intrinsic layer I layer;
Step 506, doped layer P (or N) layer deposits, also i.e. dopant deposition layer P (or N) layer on the first intrinsic layer I layer;
Step 508, cleaning, also namely the first intrinsic layer I layer and doped layer P (or N) layer is deposited successively at crystal silicon chip first side surface, after crystal silicon chip being sent to the deposition chambers for depositing the second intrinsic layer I layer, before crystal silicon chip second side surface deposits the second intrinsic layer I layer, doped layer P (or N) layer and crystal silicon chip second side surface are cleaned;
Step 510, the second intrinsic layer I layer deposition, also namely after cleaning doped layer P (or N) layer and crystal silicon chip second side surface, deposits the second intrinsic layer I layer at crystal silicon chip second side surface;
Step 512, doped layer N (or P) layer deposits, also i.e. dopant deposition layer N (or P) layer on the second intrinsic layer I layer;
Step 514, secondary cleaning, also namely at crystal silicon chip first side surface dopant deposition layer P layer, crystal silicon chip second side surface dopant deposition layer N layer, surface deposition had after the crystal silicon chip of doped layer P layer and doped layer N layer is sent to the deposition chambers for deposition of transparent conductive film layer, before doped layer P layer surface and doped layer N layer surface deposition transparent conductive film layer, doped layer P layer and doped layer N layer are cleaned;
Step 516, nesa coating deposits, also namely after cleaning doped layer P layer and doped layer N layer, at doped layer P layer surface and doped layer N layer surface deposition nesa coating;
Step 518, silk screen printing, the crystal silicon chip that also namely effects on surface deposits nesa coating carries out silk screen printing;
Step 520, namely annealing, also carry out annealing in process to the crystal silicon chip after silk screen printing.
Wherein, in step 508, doped layer P (or N) layer and crystal silicon chip second side surface are cleaned, and in step 514, doped layer P layer and doped layer N layer are cleaned, all carry out under normal temperature condition, the cleaning fluid of employing comprises: hydrofluoric acid solution (HF solution) and hydrogen peroxide solution (H
2o
2solution), the concentration of HF solution is 0.5%-5%, and comparatively preferably, the concentration of HF solution is the concentration of 1%-2%, HF solution can also be 1.0%, 2.0%, 3.0%, 4.0%, 4.5%; H
2o
2the concentration of solution is 0.5%-5%, comparatively preferably, and H
2o
2the concentration of solution is 1%-2%, H
2o
2the concentration of solution can also be 1.0%, 2.0%, 3.0%, 4.0%, 4.5%, the time of cleaning can be 1 minute-10 minutes (min), comparatively preferably, scavenging period is 2min-8min, more preferably, scavenging period is 3min-6min, and scavenging period can also be 2min, 4min, 5min, 6min, 7min, 9min.
The first intrinsic layer I layer and doped layer P (or N) layer is deposited successively at crystal silicon chip first side surface, after crystal silicon chip being sent to the deposition chambers for depositing the second intrinsic layer I layer, before crystal silicon chip second side surface deposits the second intrinsic layer I layer, use HF solution and H
2o
2solution cleans doped layer P (or N) layer and crystal silicon chip second side surface, and at crystal silicon chip first side surface dopant deposition layer P layer, crystal silicon chip second side surface dopant deposition layer N layer, surface deposition had after the crystal silicon chip of doped layer P layer and doped layer N layer is sent to the deposition chambers for deposition of transparent conductive film layer, before doped layer P layer surface and doped layer N layer surface deposition transparent conductive film layer, use HF solution and H
2o
2solution cleans doped layer P layer and doped layer N layer, and HF solution effectively can remove crystal silicon chip second side surface, doped layer P layer surface and the oxide layer on doped layer N layer surface, H
2o
2solution effectively can remove crystal silicon chip second side surface, doped layer P layer surface and the contamination on doped layer N layer surface, thus improve crystal silicon chip second side surface, doped layer P layer surface and the passivation quality on doped layer N layer surface, simultaneously for subsequent technique provides a surface more cleaned, promote to improve transparent conductive film layer and doped layer P layer surface, interface performance between transparent conductive film layer and doped layer N layer surface, promote open circuit voltage and the fill factor, curve factor of solar cell, promote battery performance.Experiment shows, uses HF solution and H
2o
2solution cleans doped layer P (or N) layer and crystal silicon chip second side surface, and uses HF solution and H
2o
2solution cleans doped layer P layer and doped layer N layer, and the open circuit voltage Voc of solar cell can be made to rise to 720mV from 715mV, and fill factor, curve factor FF rises to 74.5% from 73.3%, and conversion efficiency Eff rises to 20.5% from 20.2.
In a kind of possible execution mode, in the method that the embodiment of the present invention provides, the cleaning fluid used during cleaning comprises: hydrofluoric acid solution and hydrogen peroxide solution.
In a kind of possible execution mode, in the method that the embodiment of the present invention provides, in cleaning fluid, the concentration of hydrofluoric acid solution is more than or equal to 0.5% and is less than or equal to 5%.
In a kind of possible execution mode, in the method that the embodiment of the present invention provides, in cleaning fluid, the concentration of hydrofluoric acid solution is more than or equal to 1% and is less than or equal to 2%.
In a kind of possible execution mode, in the method that the embodiment of the present invention provides, in cleaning fluid, the concentration of hydrogen peroxide solution is more than or equal to 0.5% and is less than or equal to 5%.
In a kind of possible execution mode, in the method that the embodiment of the present invention provides, in cleaning fluid, the concentration of hydrogen peroxide solution is more than or equal to 1% and is less than or equal to 2%.
In a kind of possible execution mode, in the method that the embodiment of the present invention provides, the time of cleaning is more than or equal to 1 minute and is less than or equal to 10 minutes.
In a kind of possible execution mode, in the method that the embodiment of the present invention provides, the time of cleaning is more than or equal to 2 minutes and is less than or equal to 8 minutes.
In a kind of possible execution mode, in the method that the embodiment of the present invention provides, the time of cleaning is more than or equal to 3 minutes and is less than or equal to 6 minutes.
In a kind of possible execution mode, in the method that the embodiment of the present invention provides, before crystal silicon chip first side surface deposits the first silicon membrane layer, the method also comprises: carry out making herbs into wool cleaning to crystal silicon chip; After crystal silicon chip second side surface deposits the second silicon membrane layer or after the first silicon membrane layer and the second silicon membrane layer are cleaned, the method also comprises: at the first silicon membrane layer surface and the second silicon membrane layer surface deposition nesa coating, and carry out silk screen printing and annealing in process to the crystal silicon chip after deposition of transparent conductive film.
In a kind of possible execution mode, in the method that the embodiment of the present invention provides, the first silicon membrane layer is deposited at crystal silicon chip first side surface, comprise: deposit the first intrinsic layer I layer and doped layer P layer successively at crystal silicon chip first side surface, or deposit the first intrinsic layer I layer and doped layer N layer successively at crystal silicon chip first side surface.
In a kind of possible execution mode, in the method that the embodiment of the present invention provides, when depositing the first intrinsic layer I layer and doped layer P layer successively at crystal silicon chip first side surface, deposit the second silicon membrane layer at crystal silicon chip second side surface, comprising: deposit the second intrinsic layer I layer and doped layer N layer successively at crystal silicon chip second side surface; And when depositing the first intrinsic layer I layer and doped layer N layer successively at crystal silicon chip first side surface, deposit the second silicon membrane layer at crystal silicon chip second side surface, comprising: deposit the second intrinsic layer I layer and doped layer P layer successively at crystal silicon chip second side surface.
A kind of heterojunction solar battery that the embodiment of the present invention provides, comprise: the preparation method adopting the embodiment of the present invention to provide is prepared, as shown in Figure 6, comprising: crystal silicon chip 61, first intrinsic layer I layer 62, second intrinsic layer I layer 63, doped layer P layer 64, doped layer N layer 65, nesa coating 66 and electrode 67.
The heterojunction solar battery that the embodiment of the present invention provides, the preparation method adopting the embodiment of the present invention to provide is prepared from, also namely before crystal silicon chip second side surface deposits the second silicon membrane layer, first silicon membrane layer and crystal silicon chip second side surface are cleaned, and/or after crystal silicon chip second side surface deposits the second silicon membrane layer, first silicon membrane layer and the second silicon membrane layer are cleaned, contamination and the oxide layer on the first silicon membrane layer surface and crystal silicon chip second side surface and/or the second silicon membrane layer surface in transport process can be removed, and when in prior art, crystal silicon chip transmits between multiple deposition chambers, compare because not causing the surface passivation quality of crystal silicon chip to reduce to crystal silicon chip cleaning, improve the passivation quality on crystal silicon chip surface, simultaneously for subsequent technique provides a surface more cleaned, improve transparent conductive film layer and the first silicon membrane layer, interface performance between transparent conductive film layer and the second silicon membrane layer, thus promote fill factor, curve factor and the conversion efficiency of battery.
In sum, a kind of heterojunction solar battery that the embodiment of the present invention provides and preparation method thereof, before crystal silicon chip second side surface deposits the second silicon membrane layer, first silicon membrane layer and crystal silicon chip second side surface are cleaned, and/or after crystal silicon chip second side surface deposits the second silicon membrane layer, first silicon membrane layer and the second silicon membrane layer are cleaned, contamination and the oxide layer on the first silicon membrane layer surface and crystal silicon chip second side surface and/or the second silicon membrane layer surface in transport process can be removed, improve the passivation quality on crystal silicon chip surface, simultaneously for subsequent technique provides a surface more cleaned, improve transparent conductive film layer and the first silicon membrane layer, interface performance between transparent conductive film layer and the second silicon membrane layer, thus promote fill factor, curve factor and the conversion efficiency of battery.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (13)
1. a preparation method for heterojunction solar battery, is characterized in that, comprising:
Deposit the first silicon membrane layer at crystal silicon chip first side surface, deposit the second silicon membrane layer at crystal silicon chip second side surface;
Before described crystal silicon chip second side surface deposits the second silicon membrane layer, described first silicon membrane layer and described crystal silicon chip second side surface are cleaned, and/or after described crystal silicon chip second side surface deposits the second silicon membrane layer, described first silicon membrane layer and described second silicon membrane layer are cleaned, wherein, the first side surface of described crystal silicon chip is relative with the second side surface.
2. preparation method according to claim 1, is characterized in that, the cleaning fluid used during cleaning comprises: hydrofluoric acid solution and hydrogen peroxide solution.
3. preparation method according to claim 2, is characterized in that, in described cleaning fluid, the concentration of hydrofluoric acid solution is more than or equal to 0.5% and is less than or equal to 5%.
4. preparation method according to claim 3, is characterized in that, in described cleaning fluid, the concentration of hydrofluoric acid solution is more than or equal to 1% and is less than or equal to 2%.
5. the preparation method according to any one of claim 2-4, is characterized in that, in described cleaning fluid, the concentration of hydrogen peroxide solution is more than or equal to 0.5% and is less than or equal to 5%.
6. preparation method according to claim 5, is characterized in that, in described cleaning fluid, the concentration of hydrogen peroxide solution is more than or equal to 1% and is less than or equal to 2%.
7. preparation method according to claim 6, is characterized in that, the time of cleaning is more than or equal to 1 minute and is less than or equal to 10 minutes.
8. preparation method according to claim 7, is characterized in that, the time of described cleaning is more than or equal to 2 minutes and is less than or equal to 8 minutes.
9. the preparation method according to any one of claim 7-8, is characterized in that, the time of described cleaning is more than or equal to 3 minutes and is less than or equal to 6 minutes.
10. preparation method according to claim 1, is characterized in that, before crystal silicon chip first side surface deposits the first silicon membrane layer, the method also comprises: carry out making herbs into wool cleaning to described crystal silicon chip;
After crystal silicon chip second side surface deposits the second silicon membrane layer or after described first silicon membrane layer and described second silicon membrane layer are cleaned, the method also comprises: at described first silicon membrane layer surface and described second silicon membrane layer surface deposition nesa coating, and carry out silk screen printing and annealing in process to the crystal silicon chip after deposition of transparent conductive film.
11. preparation methods according to claim 1 or 10, is characterized in that, describedly deposit the first silicon membrane layer at crystal silicon chip first side surface, comprising:
The first intrinsic layer I layer and doped layer P layer is deposited successively at crystal silicon chip first side surface, or
The first intrinsic layer I layer and doped layer N layer is deposited successively at crystal silicon chip first side surface.
12. preparation methods according to claim 11, is characterized in that,
When depositing the first intrinsic layer I layer and doped layer P layer successively at crystal silicon chip first side surface, describedly deposit the second silicon membrane layer at crystal silicon chip second side surface, comprising: deposit the second intrinsic layer I layer and doped layer N layer successively at crystal silicon chip second side surface; And
When depositing the first intrinsic layer I layer and doped layer N layer successively at crystal silicon chip first side surface, describedly deposit the second silicon membrane layer at crystal silicon chip second side surface, comprising: deposit the second intrinsic layer I layer and doped layer P layer successively at crystal silicon chip second side surface.
13. 1 kinds of heterojunction solar batteries, is characterized in that, comprising: described heterojunction solar battery adopts the preparation method according to any one of claim 1-12 to be prepared from.
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