CN117762190A - Signal phase alignment method in digital domain - Google Patents
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Abstract
The invention relates to the field of signal simulation and communication, in particular to a signal phase alignment method in a digital domain. The invention solves the problem that the phase continuity solution in the prior art cannot cover all signals. The invention is applicable to any waveform generator with a DUC mode and a system thereof, and calculates the optimal signal file length for enabling the signal file to be continuous in phase in the process of generating an analog modulation signal file or a digital modulation signal file. The method has simple steps and small calculated amount, and can well realize the alignment of the tail phase and the initial phase of the signal file under the condition of any initial phase; the invention also discloses a parameter configuration method of analog modulation and digital modulation, which has universality for various modulation signals, and realizes the alignment of the tail phase of a signal file with an initial phase under the condition of using any initial phase by correcting the length of the signal file; the method has the advantages of simple integral structure and high flexibility, and is easy to be embedded into various signal generation algorithms.
Description
Technical Field
The invention relates to the field of signal simulation and communication, in particular to a signal phase alignment method in a digital domain.
Background
The arbitrary waveform generator has the advantages of large bandwidth and flexible use, is gradually applied to the fields of conventional testing, signal simulation, multichannel coherent testing and the like, has a wide application range, and is specifically applied to the following fields: collecting recorded broadband signal playback, design verification of a MIMO system, simulation of complex electromagnetic signals and the like; therefore, the method is widely applied to scenes such as laboratory research and development, outfield test, production line, technical guarantee and the like; as a signal source, the arbitrary waveform generator can output signals generated in a signal library or signals customized by a user to excite a test object.
The signal playing mode of the arbitrary waveform generator is as follows:
DUC mode: generating a baseband signal file by using a computer in the system or other computers, storing the baseband signal file into DDR4, reading the signal file from DDR4 through a control module to a field programmable gate array FPGA, performing digital domain processing and completing primary up-sampling, connecting the digital domain processing and completing primary up-sampling to a high-speed digital-to-analog converter DAC through a high-speed interface, up-sampling the final sampling rate in the high-speed digital-to-analog converter DAC, and performing IQ modulation to output corresponding signal waveforms; in the analog processing part, the direct connection or amplification processing is carried out, and the output power is regulated;
DAC mode: generating a radio frequency signal file by using a computer in the system or other computers, storing the radio frequency signal file into the DDR4, reading the signal file from the DDR4 through a control module to a Field Programmable Gate Array (FPGA), performing digital domain processing and completing primary up-sampling, connecting the digital domain processing and completing primary up-sampling to a high-speed digital-to-analog converter (DAC) through a high-speed interface, up-sampling the final sampling rate in the DAC, and directly outputting corresponding signal waveforms; in the analog processing part, the direct connection or amplification processing is carried out, and the output power is regulated;
the above processes all need to repeatedly play the unified signal file, so the phase continuity of the signal file will affect the signal quality to a great extent, and in the signal generation process, the phase of the head and tail of the signal file needs to be strictly controlled, otherwise, the phase jump will cause serious spurious problems.
The traditional method is that in the signal generation process, the initial phase of the signal is changed so as to obtain the same phase of the tail part of the signal file, but the method has two defects, firstly, the initial phase meeting the requirements cannot be obtained under the partial configuration of the method, and then the signal generation is finished by sacrificing partial signal quality; secondly, the method for obtaining the primary phase meeting the requirements for different signals has no universality, and the realization methods of various signals have large difference and cannot be unified.
The patent number CN201610431946.2 discloses a method for generating digital modulation signal waveform data by AWG, which selects parameters such as sampling total time, sampling rate, fine-tuned waveform center frequency parameter and the like through cyclic search and optimally designs, obtains a signal waveform file with complete waveform file information data and end-to-end waveform file, is used for continuity and integrity, and does not generate phase jump in the cyclic reading process. However, the existence of the method can only solve the problem of digital modulation signals, and the optimal signal waveform cannot be efficiently selected due to improper selection of the cyclic search parameters.
There is a need for a new phase alignment method that solves the above problems.
Disclosure of Invention
The invention provides a signal phase alignment method in a digital domain, which solves the problem that all signals cannot be covered by a phase continuity solution in the prior art.
The technical scheme of the invention is realized as follows: the signal phase alignment method under the digital domain is suitable for any waveform generator with DUC mode and a system thereof, and is used for reading a signal file from DDR4 through a control module after the computer for generating a baseband signal file and storing the baseband signal file into DDR4, performing digital domain processing on the signal file to a field programmable gate array FPGA, completing one-stage up-sampling, connecting the signal file to a high-speed digital-to-analog converter DAC through a high-speed interface, up-sampling the final sampling rate in the high-speed digital-to-analog converter DAC, and performing IQ modulation to output corresponding signal waveforms; in the analog processing part, the direct connection or amplification processing is carried out, and the output power is regulated;
after the final sampling rate of the up-sampling of the radio frequency signal file in the high-speed digital-to-analog converter DAC, directly outputting corresponding signal waveforms;
in generating an analog modulated signal file or a digital modulated signal file, an optimal signal file length is calculated such that the signal file phases are continuous.
Further, in the process of generating the analog modulation signal file, an optimal signal file length for making the signal file phase continuous is calculated, and the method comprises the following steps:
the known configuration parameters of the analog modulation signal file are signal type sig_type, granularity, sampling rate fsample, signal modulation frequency amodu_freq and signal modulation frequency offset amodu_fshift;
step A1: initializing:
initializing a signal bandwidth parameter loc_sig_bw, a final symbol rate parameter final_fsymbol and a cyclic block size loc_cyc_thr according to the following table and signal file configuration parameters;
step A2: initializing iteration parameters:
using the signal configuration parameters and the initialization signals, carrying out iterative parameter initialization according to the following calculation method: base fs ＝fsample
fsymbol＝final fsymbol
fsymbol vec ＝fsymbol
stp pt ＝granulatity
max fs ＝fsample
delt fs ＝ceil(max fs *0.01*0.1)*10
fsample＝max fs -delt fs
min fs ＝max fs -delt fs *2
fsymbol min ＝fsymbol vec
ram vec ＝ram min
err thr ＝1e-8
fc 2 ＝max fs ；
Step A3: calculation of error rate:
according to the obtained iteration parameters, calculating an error rate;
firstly, carrying out assignment of a current sampling rate;
fs＝ram min
then calculating the current symbol rate according to the following formula;
cyc symbolint ＝round(cyc symbol )
calculating a current subcarrier according to the following formula;
then, the error rate calculation is completed according to the following formula;
step A4: judging an error rate:
judging whether the data meets the requirements, and setting the threshold value as err thr ；
If the error rate is smaller than the threshold value, performing step 5;
if the error rate is greater than or equal to the threshold value, updating iteration parameters according to the following formula;
min temp ＝err2 array
repeating the step 3 again, and calculating the error rate again;
step A5: calculating the length of a signal file:
after obtaining the error rate meeting the requirements, the calculation of the signal file length is completed according to the following formula;
symbol numtemp ＝round(symbol num )
symbol numint ＝symbol numtemp
judgment of symbol numint Whether greater than loc cyc thr,whether or not it is greater than ram_max 0.75;
if not, the following calculation is performed:
completed by final iterationThe optimal signal file length with continuous signal phase is obtained.
Further, in the process of generating the digital modulation signal file, calculating an optimal signal file length for making the signal file phase continuous, comprising the following steps:
the known digital modulation signal file configuration parameters are signal type sig_type, granularity, sampling rate fsample, signal modulation code rate sig_fsymb and signal modulation frequency offset amodu_fshift;
step B1: initializing:
initializing a signal bandwidth parameter loc_sig_bw, a final symbol rate parameter final_fsymbol and a cyclic block size loc_cyc_thr according to the following table and signal file configuration parameters;
wherein a= 1.4426950408889634;
step B2: initializing iteration parameters:
and initializing iteration parameters according to the following calculation method by using the signal configuration parameters and the initialization signals:
base fs ＝fsample
fsymbol＝final fsymbol
fsymbol vec ＝fsymbol
stp pt ＝granulatity
max fs ＝fsample
delt fs ＝ceil(max fs *0.01*0.1)*10
fsample＝max fs -delt fs
min fs ＝max fs -delt fs *2
fsymbol min ＝fsymbol vec
ram vec ＝ram min
err thr ＝1e-8
fc 2 ＝max fs ；
step B3: calculation of error rate:
according to the obtained iteration parameters, calculating an error rate;
firstly, carrying out assignment of a current sampling rate;
fs＝ram min
then calculating the current symbol rate according to the following formula;
calculating a current subcarrier according to the following formula;
then, the error rate calculation is completed according to the following formula;
step B4: judging whether the error rate meets the requirement, and setting the threshold value as err thr ；
If the error rate is smaller than the threshold value, performing step 5; if the error rate is greater than or equal to the threshold value, updating iteration parameters according to the following formula;
min temp ＝err2 array
repeating the step 3 again, and calculating the error rate again;
step B5: after obtaining the error rate meeting the requirements, the calculation of the signal file length is completed according to the following formula;
symbol numtemp ＝round(symbol num )
symbol numint ＝symbol numtemp
need to judge symbol numint Whether greater than loc cyc thr,whether or not it is greater than ram_max 0.75;
if not, the following calculation is performed:
dis with final iteration completed ramfs The optimal signal file length with continuous signal phase is obtained.
Further, in the process of initializing the iteration parameters, the step is thatStep A2 or B2 as ram min If the calculated value is smaller than 1920, correction is required:
wherein fc is 2 Where the modulation type is FM or PM, a value of fshift is required.
Preferably, in the process of calculating the length of the signal file in the DAC mode, the following correction is performed, specifically, in the process of calculating the error rate, carrier period verification is added, that is, fc and fc_curr are introduced to correct the error rate, and the error rate calculation formula is corrected as follows:
the signal phase alignment method under the digital domain has the advantages of simple steps and small calculated amount, and can well realize the alignment of the tail phase and the initial phase of the signal file under the condition of any initial phase; the invention has universality for various modulation signals, and can realize the alignment of the tail phase of the signal file with the initial phase under the condition of using any initial phase by correcting the length of the signal file when the signal file is generated by an arbitrary waveform generator and related systems thereof; the method has the advantages of simple integral structure and high flexibility, and is easy to be embedded into various signal generation algorithms.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
FIG. 1 is a schematic flow chart of a method for calculating an optimal signal file length in the technical scheme of the invention;
FIG. 2 is a system block diagram of an arbitrary waveform generator and its associated system applicable in the present solution;
FIG. 3 is a graph showing the relationship between error rate and signal file length variation in a signal generation scheme provided by the present invention;
fig. 4 is a diagram of a iterative process.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention discloses a signal phase alignment method under a digital domain, which is applicable to an arbitrary waveform generator with a DUC mode and a system thereof, and is used for reading a signal file from the DDR4 through a control module after the computer for generating a baseband signal file is stored in the DDR4, performing digital domain processing on the signal file to a field programmable gate array FPGA, completing primary up-sampling, connecting the signal file to a high-speed digital-to-analog converter DAC through a high-speed interface, up-sampling a final sampling rate in the high-speed digital-to-analog converter DAC, and performing IQ modulation to output corresponding signal waveforms; in the analog processing part, the direct connection or amplification processing is carried out, and the output power is regulated;
after the final sampling rate of the up-sampling of the radio frequency signal file in the high-speed digital-to-analog converter DAC, directly outputting corresponding signal waveforms;
in generating an analog modulated signal file or a digital modulated signal file, an optimal signal file length is calculated such that the signal file phases are continuous.
Further, in the process of generating the analog modulation signal file, an optimal signal file length for making the signal file phase continuous is calculated, and the method comprises the following steps:
the known configuration parameters of the analog modulation signal file are signal type sig_type, granularity, sampling rate fsample, signal modulation frequency amodu_freq and signal modulation frequency offset amodu_fshift;
step A1: initializing:
initializing a signal bandwidth parameter loc_sig_bw, a final symbol rate parameter final_fsymbol and a cyclic block size loc_cyc_thr according to the following table and signal file configuration parameters;
step A2: initializing iteration parameters:
using the signal configuration parameters and the initialization signals, carrying out iterative parameter initialization according to the following calculation method: base fs ＝fsample
fsymbol＝final fsymbol
fsymbol vec ＝fsymbol
stp pt ＝granulatity
max fs ＝fsample
delt fs ＝ceil(max fs *0.01*0.1)*10
fsample＝max fs -delt fs
min fs ＝max fs -delt fs *2
fsymbol min ＝fsymbol vec
ram vec ＝ram min
err thr ＝1e-8
fc 2 ＝max fs ；
Step A3: calculation of error rate:
according to the obtained iteration parameters, calculating an error rate;
firstly, carrying out assignment of a current sampling rate;
fs＝ram min
then calculating the current symbol rate according to the following formula;
calculating a current subcarrier according to the following formula;
then, the error rate calculation is completed according to the following formula;
step A4: judging an error rate:
judging whether the data meets the requirements, and setting the threshold value as err thr ；
If the error rate is smaller than the threshold value, performing step 5;
if the error rate is greater than or equal to the threshold value, updating iteration parameters according to the following formula;
min temp ＝err2 array
/>
repeating the step 3 again, and calculating the error rate again;
step A5: calculating the length of a signal file:
after obtaining the error rate meeting the requirements, the calculation of the signal file length is completed according to the following formula;
symbol numtemp ＝round(symbol num )
symbol numint ＝symbol numtemp
judgment of symbol numint Whether greater than loc cyc thr,whether or not it is greater than ram_max 0.75;
if not, the following calculation is performed:
completed by final iterationThe optimal signal file length with continuous signal phase is obtained.
Further, in the process of generating the digital modulation signal file, calculating an optimal signal file length for making the signal file phase continuous, comprising the following steps:
the known digital modulation signal file configuration parameters are signal type sig_type, granularity, sampling rate fsample, signal modulation code rate sig_fsymb and signal modulation frequency offset amodu_fshift;
step B1: initializing:
initializing a signal bandwidth parameter loc_sig_bw, a final symbol rate parameter final_fsymbol and a cyclic block size loc_cyc_thr according to the following table and signal file configuration parameters;
/>
/>
wherein a= 1.4426950408889634;
step B2: initializing iteration parameters:
and initializing iteration parameters according to the following calculation method by using the signal configuration parameters and the initialization signals: base fs ＝fsample
fsymbol＝final fsymbol
fsymbol vec ＝fsymbol
stp pt ＝granulatity
max fs ＝fsample
delt fs ＝ceil(max fs *0.01*0.1)*10
fsample＝max fs -delt fs
min fs ＝max fs -delt fs *2
fsymbol min ＝fsymbol vec
ram vec ＝ram min
err thr ＝1e-8
fc 2 ＝max fs ；
Step B3: calculation of error rate:
according to the obtained iteration parameters, calculating an error rate;
firstly, carrying out assignment of a current sampling rate;
fs＝ram min
then calculating the current symbol rate according to the following formula;
/>
calculating a current subcarrier according to the following formula;
then, the error rate calculation is completed according to the following formula;
step B4: judging whether the error rate meets the requirement, and setting the threshold value as err thr ；
If the error rate is smaller than the threshold value, performing step 5; if the error rate is greater than or equal to the threshold value, updating iteration parameters according to the following formula;
min temp ＝err2 array
repeating the step 3 again, and calculating the error rate again;
step B5: after obtaining the error rate meeting the requirements, the calculation of the signal file length is completed according to the following formula;
symbol numtemp ＝round(symbol num )
symbol numint ＝symbol numtemp
need to judge symbol numint Whether greater than loc cyc thr,whether or not it is greater than ram_max 0.75;
if not, the following calculation is performed:
/>
completed by final iterationThe optimal signal file length with continuous signal phase is obtained.
Further, in the process of initializing the iteration parameters, namely, step A2 or B2 is used as ram min If the calculated value is smaller than 1920, correction is required:
wherein fc is 2 Where the modulation type is FM or PM, a value of fshift is required.
Preferably, in the process of calculating the length of the signal file in the DAC mode, the following correction is performed, specifically, in the process of calculating the error rate, carrier period verification is added, that is, fc and fc_curr are introduced to correct the error rate, and the error rate calculation formula is corrected as follows:
the first embodiment is as follows: generating AM modulated signal files in DUC mode
The signal configuration is known, the signal modulation mode is AM modulation, the waveform generator mode is DUC mode, the signal file sampling rate is 2.5Gsps, the granularity is 32, and the modulation frequency is 1.93MHz.
Step A1: according to the table in the summary of the invention, the initialization is completed for the signal bandwidth parameter loc_sig_bw, the final symbol rate parameter final_fsymbol and the cyclic block size loc_cyc_thr;
i.e. loc_sig_bw=100×1.93e6=1.93e8; final_fsymbol=1.93e6; loc_cyc_thr=4;
step A2: and initializing iteration parameters according to the following calculation method by using the signal configuration parameters and the initialization signals:
base_fs＝2.5e9；
fsymbol＝1.93e6；
fsymbol_vec＝1.93e6；
stp_pt＝32；
max_fs＝2.5e9；
delt_fs＝2.5e7；
fsample＝2.475e9；
min_fs＝2.45e9；
fsymbol_min＝1.93e6；
R＝1.2824e4；
ram_min＝3200；
len_ram_vec＝23437401；
ram_vec＝3200；
err_thr＝1e-8；
step A3: according to the obtained iteration parameters, calculating an error rate;
err2_array＝0.1346
step A4: if the error rate is judged to be not in accordance with the requirement, the length of the signal file is increased, the calculation is carried out again, and the iteration process is repeated, wherein the specific iteration process is shown in figure 3;
step A5: after obtaining the error rate meeting the requirements, finishing the calculation of the length of the signal file;
dis_ram_fs＝500000
finally, under the configuration, the first phase alignment of the file under any initial phase can be realized only by generating a signal file with the length of 500000.
The second embodiment is as follows: generating QPSK modulated signal files in DUC mode
The signal configuration is known, the signal modulation mode is QPSK modulation, the waveform generator mode is DUC mode, the signal file sampling rate is 78.125Msps, the granularity is 1, and the modulation frequency is 1Msps.
Step B1: according to the table in the summary of the invention, the initialization is completed for the signal bandwidth parameter loc_sig_bw, the final symbol rate parameter final_fsymbol and the cyclic fast size loc_cyc_thr;
i.e. loc_sig_bw=3.2×1e6=3.2e6; final_fsymbol=1e6; loc_cyc_thr=4096;
step B2: using the signal configuration parameters and the initialization signals, the iteration parameters Shu Chushi are initialized according to the following calculation method:
base_fs＝78.125e6
fsymbol＝1e6
fsymbol_vec＝1e6
stp_pt＝1
max_fs＝78.125e6
delt_fs＝781250
fsample＝77343750
min_fs＝76562500
fsymbol_min＝1e6
R＝77.34375
ram_min＝78
ram_vec＝78
err_thr＝1e-8
fc_2＝78.125e6
step B3: and according to the obtained iteration parameters, calculating an error rate:
err2_array＝0.011767
step B4: if the error rate is judged to be not in accordance with the requirement, the length of the signal file is increased, the calculation is carried out again, and the iteration process is repeated, wherein the specific iteration process is shown in fig. 4;
step B5: after obtaining the error rate meeting the requirements, finishing the calculation of the length of the signal file;
dis_ram_fs＝160000
finally, under the configuration, the first phase alignment of the file under any initial phase can be realized only by generating a signal file with the length of 160000.
The signal phase alignment method under the digital domain has the advantages of simple steps and small calculated amount, and can well realize the alignment of the tail phase and the initial phase of the signal file under the condition of any initial phase; the invention has universality for various modulation signals, and can realize the alignment of the tail phase of the signal file with the initial phase under the condition of using any initial phase by correcting the length of the signal file when the signal file is generated by an arbitrary waveform generator and related systems thereof; the method has the advantages of simple integral structure and high flexibility, and is easy to be embedded into various signal generation algorithms.
Of course, a person skilled in the art shall make various corresponding changes and modifications according to the present invention without departing from the spirit and the essence of the invention, but these corresponding changes and modifications shall fall within the protection scope of the appended claims.
Claims (5)
1. A signal phase alignment method in digital domain is applicable to any waveform generator with DUC mode and system thereof, which is characterized in that: the method comprises the following steps:
after the computer for generating the baseband signal file is stored in the DDR4, the signal file is read from the DDR4 through a control module and is subjected to digital domain processing to a field programmable gate array FPGA, primary up-sampling is completed, the digital domain processing is connected to a high-speed digital-to-analog converter DAC through a high-speed interface, the final sampling rate is up-sampled in the high-speed digital-to-analog converter DAC, and IQ modulation is carried out to output corresponding signal waveforms; in the analog processing part, the direct connection or amplification processing is carried out, and the output power is regulated;
after the final sampling rate of the up-sampling of the radio frequency signal file in the high-speed digital-to-analog converter DAC, directly outputting corresponding signal waveforms;
in generating an analog modulated signal file or a digital modulated signal file, an optimal signal file length is calculated such that the signal file phases are continuous.
2. A method for signal phase alignment in the digital domain as claimed in claim 1, wherein: in the process of generating an analog modulation signal file, calculating an optimal signal file length for enabling the signal file to be continuous in phase, comprising the following steps of:
the known configuration parameters of the analog modulation signal file are signal type sig_type, granularity, sampling rate fsample, signal modulation frequency amodu_freq and signal modulation frequency offset amodu_fshift;
step A1: initializing:
initializing a signal bandwidth parameter loc_sig_bw, a final symbol rate parameter final_fsymbol and a cyclic block size loc_cyc_thr according to the following table and signal file configuration parameters;
step A2: initializing iteration parameters:
using the signal configuration parameters and the initialization signals, carrying out iterative parameter initialization according to the following calculation method:
base fs ＝fsample
fsymbol＝final fsymbol
fsymbol vec ＝fsymbol
stp pt ＝granulatity
max fs ＝fsample
delt fs ＝ceil(max fs *0.01*0.1)*10
fsample＝max fs -delt fs
min fs ＝max fs -delt fs *2
fsymbol min ＝fsymbol vec
ram vec ＝ram min
err thr ＝1e-8
fc 2 ＝max fs ；
step A3: calculation of error rate:
according to the obtained iteration parameters, calculating an error rate;
firstly, carrying out assignment of a current sampling rate;
fs＝ram min
then calculating the current symbol rate according to the following formula;
calculating a current subcarrier according to the following formula;
then, the error rate calculation is completed according to the following formula;
step A4: judging an error rate:
judging whether the data meets the requirements, and setting the threshold value as err thr ；
If the error rate is smaller than the threshold value, performing step 5;
if the error rate is greater than or equal to the threshold value, updating iteration parameters according to the following formula;
min temp ＝err2 array
repeating the step 3 again, and calculating the error rate again;
step A5: calculating the length of a signal file:
after obtaining the error rate meeting the requirements, the calculation of the signal file length is completed according to the following formula;
symbol numtemp ＝round(symbol num )
symbol numint ＝symbol numtemp
judgment of symbol numint Whether greater than loc cyc thr,whether or not it is greater than ram_max 0.75;
if not, the following calculation is performed:
completed by final iterationThe optimal signal file length with continuous signal phase is obtained.
3. A method for signal phase alignment in the digital domain as claimed in claim 2, wherein: in the process of generating a digital modulation signal file, calculating an optimal signal file length for making the signal file phase continuous, comprising the steps of:
the known digital modulation signal file configuration parameters are signal type sig_type, granularity, sampling rate fsample, signal modulation code rate sig_fsymb and signal modulation frequency offset amodu_fshift;
step B1: initializing:
initializing a signal bandwidth parameter loc_sig_bw, a final symbol rate parameter final_fsymbol and a cyclic block size loc_cyc_thr according to the following table and signal file configuration parameters;
wherein a= 1.4426950408889634;
step B2: initializing iteration parameters:
and initializing iteration parameters according to the following calculation method by using the signal configuration parameters and the initialization signals:
base fs ＝fsample
fsymbol＝final fsymbol
fsymbol vec ＝fsymbol
stp pt ＝granulatity
max fs ＝fsample
delt fs ＝ceil(max fs *0.01*0.1)*10
fsample＝max fs -delt fs
min fs ＝max fs -delt fs *2
fsymbol min ＝fsymbol vec
ram vec ＝ram min
err thr ＝1e-8
fc 2 ＝max fs ；
step B3: calculation of error rate:
according to the obtained iteration parameters, calculating an error rate; firstly, carrying out assignment of a current sampling rate;
fs＝ram min
then calculating the current symbol rate according to the following formula;
calculating a current subcarrier according to the following formula;
then, the error rate calculation is completed according to the following formula;
step B4: judging whether the error rate meets the requirement, and setting the threshold value as err thr ；
If the error rate is smaller than the threshold value, performing step 5; if the error rate is greater than or equal to the threshold value, updating iteration parameters according to the following formula;
min temp ＝err2 array
repeating the step 3 again, and calculating the error rate again;
step B5: after obtaining the error rate meeting the requirements, the calculation of the signal file length is completed according to the following formula;
symbol numtemp ＝round(symbol num )
symbol numint ＝symbol numtemp
need to judge symbol numint Whether greater than loc cyc thr,whether or not it is greater than ram_max 0.75;
if not, the following calculation is performed:
completed by final iterationThe optimal signal file length with continuous signal phase is obtained.
4. A method of signal phase alignment in the digital domain according to claim 3, wherein: in the process of initializing the iteration parameters, namely, using step A2 or B2 as ram min If the calculated value is smaller than 1920, correction is required:
wherein fc is 2 Where the modulation type is FM or PM, a value of fshift is required.
5. The method for signal phase alignment in the digital domain of claim 4, wherein: in the process of calculating the length of a signal file in the DAC mode, the following correction is carried out, specifically, in the process of calculating the error rate, carrier period verification is added, namely, fc and fc_curr are introduced to correct the error rate, and an error rate calculation formula is corrected as follows:
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