CN114124341A - Synchronization method suitable for high-bit-rate frequency modulation signal - Google Patents
Synchronization method suitable for high-bit-rate frequency modulation signal Download PDFInfo
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- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
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Abstract
The invention provides a synchronization method suitable for a high-code-rate frequency modulation signal, which comprises the following steps: the input signal is subjected to signal resampling through an interpolation filter; performing multi-symbol detection (MSD) detection on the resampled signal to obtain an output signal; performing cross product frequency discrimination and Automatic Gain Control (AGC) on the resampled signals, respectively performing leading accumulation and lagging accumulation, then performing timing error calculation on the leading accumulated value and the lagging accumulated value to obtain a timing error, and sending the timing error to a loop filter to obtain a loop control error; the loop control error is sent to a numerical control oscillator, the numerical control oscillator generates interpolation time and interpolation phase, and the interpolation time and the interpolation phase are sent to an interpolation filter; the numerical control oscillator sends the generated interpolation time to the leading bit clock generation module and the lagging bit clock generation module to generate a leading accumulation reset signal and a lagging accumulation reset signal which are used for resetting the leading accumulation module and the lagging accumulation module.
Description
Technical Field
The invention relates to the technical field of wireless communication, in particular to a synchronization method suitable for high-code-rate frequency modulation signals.
Background
In the field of missile and arrow telemetering, telemetering signals of a frequency modulation system have high reliability and good anti-interference capability, and are widely applied. The rate of the frequency modulation telemetry baseband which is mainstream in China at present is between 10Kbps and 20 Mbps. The development trend of remote measurement products in the future mainly develops towards the directions of strong environmental adaptability, high code rate, high-efficiency spectrum utilization rate, product miniaturization and the like so as to adapt to different transmitting tasks.
In a common fm signal synchronization scheme, an integration method is used in a symbol loop to reduce the speed of an oversampled signal to a symbol rate, and the signal-to-noise ratio of the signal is improved by integration. To achieve better performance, a larger number of integration points is required, and thus a higher sampling rate is required. Under the limiting conditions of hardware sampling rate and processing clock, the common frequency modulation signal synchronization scheme has limited applicable code rate and cannot be applicable to higher code rate.
In the prior art of frequency modulation signal synchronization, a patent 'PCM/FM signal early-late loop frequency synchronization method based on multi-symbol detection' discloses an early-late gate frequency synchronization method for fast capturing and high-precision tracking of large dynamic PCM/FM signal carrier frequency, the method adopts 2 MSD modules in a synchronization loop to realize high complexity, and meanwhile, an integral averaging method is adopted in the loop and is not suitable for high-code-rate frequency modulation signals. The patent 'a low complexity bit synchronization method for PCM/FM multi-symbol detection' discloses a bit synchronization method for saving 1 MSD, which firstly carries out MSD calculation and then adopts Gardner timing synchronization, thereby reducing the realization complexity and being suitable for high code rate frequency modulation signals. Although this method saves 1 MSD module, the MSD used in this method is placed before bit synchronization, timing errors cause MSD correlation loss, and thus this method has poor estimation accuracy.
Disclosure of Invention
The object of the present invention is to solve at least one of the technical drawbacks mentioned.
Therefore, the present invention is directed to a synchronization method for high-bit-rate frequency modulated signals, so as to solve the problems mentioned in the background art and overcome the disadvantages of the prior art.
In order to achieve the above object, an embodiment of the present invention provides a synchronization method for a high-rate fm signal, including:
step S1, the input signal is re-sampled by an interpolation filter; performing multi-symbol detection (MSD) detection on the resampled signal to obtain an output signal;
step S2, after cross product frequency discrimination and automatic gain control AGC are carried out on the resampled signals, respectively carrying out leading accumulation and lagging accumulation to obtain leading accumulated values and lagging accumulated values, then carrying out timing error calculation on the leading accumulated values and the lagging accumulated values to obtain timing errors, and sending the timing errors to a loop filter to obtain loop control errors;
step S3, sending the loop control error to a numerically controlled oscillator, generating an interpolation time and an interpolation phase by the numerically controlled oscillator, and sending the interpolation time and the interpolation phase to the interpolation filter for controlling the generation of the required resampling signal;
in step S4, the dco sends the generated interpolation time to the leading bit clock generation module and the lagging bit clock generation module to generate a leading accumulation reset signal and a lagging accumulation reset signal for resetting the leading accumulation module and the lagging accumulation module.
Preferably, in any of the above schemes, the interpolation filter is a polyphase filter, and includes a plurality of filters, each of the filters having a set of filter coefficients obtained by polyphase decomposition.
Preferably, in any of the above solutions, in the step S2,
the output signal at the nth time isThe accumulated reset signal isThen, the value is accumulatedIs composed of
According to the calculated advance accumulated valueAnd lag accumulation valueCalculating the timing errorIs composed of
The timing error passes through a loop filter to obtain a loop control error.
Preferably, in any of the above schemes, the loop filter uses a second order loop or a third order loop.
Preferably, in any of the above schemes, when the loop filter adopts a second order loop, the loop control error isIs composed of
Preferably, in step S3, the method for generating an interpolation time and an interpolation phase by the digitally controlled oscillator includes:
wherein,is the accumulated value of the NCO,the amount of the carbon dioxide is the intermediate amount,for interpolating the time enable signal whenThe time is the interpolation time instant,in order to interpolate the phase of the phase,is NCO control word and the calculation method is
Wherein,in order to sample the signal with a frequency of,i is the number of filters for the signal bit rate.
In any of the above embodiments, preferably, in step S4, the advance bit clock and the retard bit clock are generated as the accumulation reset signal based on the interpolation time. The specific implementation method comprises the following steps: enabling loop counting of interpolation instants, i.e. count valuesClock with alarmIs shown as
Compared with the prior art, the invention has the following beneficial effects:
1. the applicable symbol rate is high. According to the scheme of the invention, the maximum supported code rate is known to beThe code rate supported by the conventional method is generallyThe following. Therefore, the invention is suitable for frequency modulation signals with higher code rate and is also suitable for frequency modulation signals with low code rate.
2. The synchronization precision is high. The invention resamples the input signal into the resample signal with fixed sampling multiple through the interpolation filter, and simultaneously ensures the stability of loop gain by combining with an AGC module; the loop is adopted to track the timing error, and NCO is adopted to adjust the interpolation time and the interpolation phase, so that the synchronization error is reduced; and the loop synchronization is performed firstly, and then the MSD detection is performed, so that the MSD detection performance is obviously improved. Therefore, the invention has extremely high synchronization precision.
3. The synchronization threshold is low. The invention adopts an interpolation filter to resample an input signal to obtain a resampled signal of 4 times of sampling times, and the resampled signal is processed by a synchronous loop to still have good synchronous signal at low signal-to-noise ratio and have low synchronous threshold.
4. The complexity is low. The invention only adopts 1 MSD module, and other modules (transversal filter, cross product frequency discrimination, AGC, loop filter) only consume more than 10 multipliers, and has the advantage of low realization complexity.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
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The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a flow chart of a synchronization method for high-rate fm signals according to an embodiment of the invention;
fig. 2 is a diagram of a synchronization method architecture for high-rate fm signals according to an embodiment of the invention;
fig. 3 is a schematic diagram of an interpolation filter according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
The invention provides a synchronization method suitable for high-code-rate frequency modulation signals, which can solve the problems that the existing synchronization technology is not suitable for the high-code-rate frequency modulation signals or the synchronization precision is poor. The method is realized by interpolation filter, multi-symbol detection MSD detection, cross product frequency discrimination, automatic gain control AGC, leading accumulation, lagging accumulation, timing error calculation, loop filter, numerically controlled oscillator NCO, leading bit clock generation, lagging bit clock generation and the like.
As shown in fig. 1 and fig. 2, the synchronization method for high-rate frequency modulated signals according to the embodiment of the present invention includes the following steps:
step S1, the input signal is re-sampled by an interpolation filter; and MSD (multi-symbol detection) detection is performed on the resampled signal to obtain an output signal.
In particular, assume that the input signal sampling frequency isAt a signal bit rate of. Firstly, an input signal is resampled by an interpolation filter to obtain a resampled signal, and the resampled signal is 4 times of an oversampled signal, namely the resampled signal has a sampling rate of。
In an embodiment of the present invention, the interpolation filter may be a polyphase filter, including a plurality of filters, each filter having a set of filter coefficients obtained by polyphase decomposition. With particular reference to FIG. 3, the interpolation filter employs a polyphase filter, includingA filter, isEach filter contains a set of filter coefficients resulting from a polyphase decomposition.
Assuming that the order of the polyphase filter is M, the M +1 filter coefficients of the ith filter are M. The interpolation filter first of all is based on the interpolation phaseSelectingAnd the group of filter coefficients are loaded into the transverse filter, and filtering processing is carried out on the input signal at the interpolation moment to obtain a resampled signal.
Output signal calculation process: the resampled signal is subjected to MSD detection and 4-point matched filtering to obtain an output signal with the rate of。
Step S2, specifically, while step S1 is executed, cross product frequency discrimination and AGC (automatic Gain Control) are performed on the resampled signal, then leading accumulation and lagging accumulation are performed respectively to obtain a leading accumulated value and a lagging accumulated value, timing error calculation is performed on the leading accumulated value and the lagging accumulated value to obtain a timing error, and the timing error is sent to a loop filter to obtain a loop Control error.
Specifically, in the synchronization loop, the resampled signal is subjected to difference product frequency discrimination, the frequency modulated signal is converted into a PCM signal, and the power level of the PCM signal is normalized through an AGC module.
The AGC processed signals are accumulated, including early accumulation and late accumulation. The two accumulation processing modes are the same, when the accumulation reset signal is equal to 1, the accumulation result is cleared, otherwise, the accumulation is continued. The calculation process is as follows: suppose that the output signal of the AGC module at the nth time isThe accumulated reset signal isThen, the value is accumulatedIs composed of
According to the calculated advance accumulated valueAnd lag accumulation valueCalculating the timing errorIs composed of
The timing error passes through a loop filter to obtain a loop control error.
In embodiments of the present invention, the loop filter employs a second order loop or a third order loop.
Step S3, sending the loop control error to an NCO (digital Oscillator), generating an interpolation time and an interpolation phase by the digital Oscillator, and sending the interpolation time and the interpolation phase to an interpolation filter for controlling to generate the required resampling signal.
In this step, the numerically controlled oscillator generates an interpolation time and an interpolation phase according to the loop control error, and includes the following steps:
wherein,is the accumulated value of the NCO,the amount of the carbon dioxide is the intermediate amount,for interpolating the time enable signal whenThe time is the interpolation time instant,in order to interpolate the phase of the phase,is NCO control word and the calculation method is
In step S4, the dco sends the generated interpolation time to the leading bit clock generation module and the lagging bit clock generation module to generate a leading accumulation reset signal and a lagging accumulation reset signal for resetting the leading accumulation module and the lagging accumulation module.
Specifically, an advance bit clock and a retard bit clock are generated as the accumulation reset signal based on the interpolation timing. The specific implementation method comprises the following steps: enabling loop counting of interpolation instants, i.e. count valuesClock with alarmIs shown as
The invention provides a synchronization method suitable for high-code-rate frequency modulation signals, which can be used for the synchronization of the high-code-rate frequency modulation signals and the synchronization of the low-code-rate frequency modulation signals, and has the advantages of low complexity, high synchronization precision, low synchronization threshold and good synchronization performance.
Compared with the prior art, the invention has the following beneficial effects:
1. the applicable symbol rate is high. According to the scheme of the invention, the maximum supported code rate is known to beThe code rate supported by the conventional method is generallyThe following. Therefore, the invention is suitable for frequency modulation signals with higher code rate and is also suitable for frequency modulation signals with low code rate.
2. The synchronization precision is high. The invention resamples the input signal into the resample signal with fixed sampling multiple through the interpolation filter, and simultaneously ensures the stability of loop gain by combining with an AGC module; the loop is adopted to track the timing error, and NCO is adopted to adjust the interpolation time and the interpolation phase, so that the synchronization error is reduced; and the loop synchronization is performed firstly, and then the MSD detection is performed, so that the MSD detection performance is obviously improved. Therefore, the invention has extremely high synchronization precision.
3. The synchronization threshold is low. The invention adopts an interpolation filter to resample an input signal to obtain a resampled signal of 4 times of sampling times, and the resampled signal is processed by a synchronous loop to still have good synchronous signal at low signal-to-noise ratio and have low synchronous threshold.
4. The complexity is low. The invention only adopts 1 MSD module, and other modules (transversal filter, cross product frequency discrimination, AGC, loop filter) only consume more than 10 multipliers, and has the advantage of low realization complexity.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
It will be understood by those skilled in the art that the present invention includes any combination of the summary and detailed description of the invention described above and those illustrated in the accompanying drawings, which is not intended to be limited to the details and which, for the sake of brevity of this description, does not describe every aspect which may be formed by such combination. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made in the above embodiments by those of ordinary skill in the art without departing from the principle and spirit of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (7)
1. A synchronization method suitable for high-bit-rate frequency modulation signals is characterized by comprising the following steps:
step S1, the input signal is re-sampled by an interpolation filter; performing multi-symbol detection (MSD) detection on the resampled signal to obtain an output signal;
step S2, after cross product frequency discrimination and automatic gain control AGC are carried out on the resampled signals, respectively carrying out leading accumulation and lagging accumulation to obtain leading accumulated values and lagging accumulated values, then carrying out timing error calculation on the leading accumulated values and the lagging accumulated values to obtain timing errors, and sending the timing errors to a loop filter to obtain loop control errors;
step S3, sending the loop control error to a numerically controlled oscillator, generating an interpolation time and an interpolation phase by the numerically controlled oscillator, and sending the interpolation time and the interpolation phase to the interpolation filter for controlling the generation of the required resampling signal;
in step S4, the dco sends the generated interpolation time to the leading bit clock generation module and the lagging bit clock generation module to generate a leading accumulation reset signal and a lagging accumulation reset signal for resetting the leading accumulation module and the lagging accumulation module.
2. A method of synchronizing a frequency modulated signal at a high rate as defined in claim 1, wherein the interpolation filter is a polyphase filter comprising a plurality of filters, each of the filters having a set of filter coefficients derived from a polyphase decomposition.
3. The method for synchronizing high rate FM signals as claimed in claim 1, wherein in said step S2,
the output signal at the nth time isCumulative complexBit signal isThen, the value is accumulatedIs composed of
According to the calculated advance accumulated valueAnd lag accumulation valueCalculating the timing errorIs composed of
The timing error passes through a loop filter to obtain a loop control error.
4. A method of synchronizing a frequency modulated signal having a high code rate as defined in claim 3, wherein the loop filter uses a second order loop or a third order loop.
6. The method for synchronizing a high rate fm signal according to claim 1, wherein in step S3, the interpolation time and the interpolation phase are generated by the digitally controlled oscillator, comprising the steps of:
wherein,is the accumulated value of the NCO,the amount of the carbon dioxide is the intermediate amount,for interpolating the time enable signal whenThe time is the interpolation time instant,in order to interpolate the phase of the phase,is NCO control word and the calculation method is
7. A method for synchronizing a high rate fm signal as claimed in claim 1, wherein in step S4, the leading bit clock and the lagging bit clock are generated as the accumulated reset signal according to the interpolation time;
the specific implementation method comprises the following steps: enabling loop counting of interpolation instants, i.e. count valuesClock with alarmIs shown as
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