CN105161537A - 降低起始电压及导通电阻的mosfet组件 - Google Patents

降低起始电压及导通电阻的mosfet组件 Download PDF

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CN105161537A
CN105161537A CN201510466253.2A CN201510466253A CN105161537A CN 105161537 A CN105161537 A CN 105161537A CN 201510466253 A CN201510466253 A CN 201510466253A CN 105161537 A CN105161537 A CN 105161537A
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廖奇泊
陈俊峰
周雯
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Shanghai Jingliang Electronic Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions

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  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明提供了一种降低起始电压及导通电阻的MOSFET组，包括源极、电介质层、N+源区、多晶硅栅极、栅极电介质层、漏极、P井区、N型外延区、P型区域,电介质层位于源极和多晶硅栅极之间，N+源区位于栅极电介质层的侧面，栅极电介质层位于多晶硅栅极的***，漏极位于N型外延区的下方，P型区域位于P井区内，P井区位于N+源区的下方。本发明在提高N型衬底区的状况下，不需提高P井区的参杂浓度和深度，具有低导通电压和低导通电阻的特性。

Description

降低起始电压及导通电阻的MOSFET组件
技术领域
本发明涉及一种MOSFET组件，具体地，涉及一种降低起始电压(Lowthresholdvoltage)及导通电阻的MOSFET组件。
背景技术
在传统功率MOSFET(Metal-Oxide-SemiconductorField-EffectTransistor，金氧半场效晶体管)组件中，主要通过低参杂浓度和一定厚度的N型衬底区来提供组件足够的耐压能力，因此N型衬底区是主要的导通电阻来源，在SiC工艺中由于材料具有更高的临界崩溃电压，因此可以提高衬底参杂浓度及厚度来降低导通电阻，但是高衬底参杂浓度会造成组件空乏区分布特性的改变，为了抑止P井区的空乏区接触到N+source(源)区造成耐压能力的下降，在组件设计上需要提高P井区的参杂浓度和深度，但是这样的做法会大幅提高组件的起始电压和信道电阻。
如图1所示，传统高压MOSFET组件包括源极1、电介质层2、N+source(源)区3、多晶硅栅极4、栅极电介质层(gate-dielectric)5、漏极6、P井区7、N型外延区8。传统高压MOSFET组件中的耐压能力主要由相当厚度且轻参杂的N型衬底所提供，因此来自N型衬底区的电阻会是MOSFET组件的导通电阻的主要来源。
由于材料具有较高的临界崩溃电场特性，因此可以提高N型衬底的参杂浓度和降低厚度来获得足够的耐压能力，但是提高N型衬底的参杂浓度需要相对的提高P井区的浓度和深度来避免空乏区延伸至Source(源)区域造成耐压能力的下降，这样会提高组件导通的起始电压(thresholdvoltage)和通道电阻(channelresistance)。
发明内容
针对现有技术中的缺陷，本发明的目的是提供一种降低起始电压及导通电阻的MOSFET组件，其在提高N型衬底区的状况下，不需提高P井区的参杂浓度和深度，具有低导通电压和低导通电阻的特性。
根据本发明的一个方面，提供一种降低起始电压及导通电阻的MOSFET组，其特征在于，包括源极、电介质层、N+源区、多晶硅栅极、栅极电介质层、漏极、P井区、N型外延区、P型区域,电介质层位于源极和多晶硅栅极之间，N+源区位于栅极电介质层的侧面，栅极电介质层位于多晶硅栅极的***，漏极位于N型外延区的下方，P型区域位于P井区内，P井区位于N+源区的下方。
优选地，所述栅极电介质层的底端和N型外延区之间设有P型植入区。
优选地，所述P型区域的长度大于N+源区的长度。
与现有技术相比，本发明具有如下的有益效果：本发明在提高N型衬底区的状况下，不需提高P井区的参杂浓度和深度，具有低导通电压和低导通电阻的特性。
附图说明
通过阅读参照以下附图对非限制性实施例所作的详细描述，本发明的其它特征、目的和优点将会变得更明显：
图1为传统高压MOSFET组件的结构示意图。
图2为本发明降低起始电压及导通电阻的MOSFET组件的结构示意图。
具体实施方式
下面结合具体实施例对本发明进行详细说明。以下实施例将有助于本领域的技术人员进一步理解本发明，但不以任何形式限制本发明。应当指出的是，对本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进。这些都属于本发明的保护范围。
如图2所示，本发明降低起始电压及导通电阻的MOSFET组件包括源极1、电介质层2、N+source(源)区3、多晶硅栅极4、栅极电介质层(gate-dielectric)5、漏极6、P井区7、N型外延区8、P型区域9,电介质层2位于源极1和多晶硅栅极4之间，N+source(源)区3位于栅极电介质层(gate-dielectric)5的侧面，栅极电介质层(gate-dielectric)5位于多晶硅栅极4的***，漏极6位于N型外延区8的下方，P型区域9位于P井区7内，P井区7位于N+source(源)区3的下方。所述P型区域的长度大于N+源区的长度，这样方便区分，另外大幅降低组件的导通电阻。
栅极电介质层(gate-dielectric)5的底端和N型外延区8之间设有P型植入区10。P型植入区10通过P型离子植入改变栅极下方电流分布来保护栅极下方栅极电介质层(gate-dielectric)，可以更进一步提升组件的可靠度。
本发明在P井区内增加一个重参杂的P型区域，在增加N型衬底的参杂浓度的状况下，不需特别提高P井区的深度和参杂浓度，即可抑止空乏区延伸至N+Source区域，因此可以大幅降低组件的导通电阻。本发明可以提供不随N型衬底的参杂浓度而须改变的的P井区浓度和深度的特性，在降低的N型衬底电阻的条件下不须牺牲信道电阻和提高起始电压，特别是在SiC工艺中。
以上对本发明的具体实施例进行了描述。需要理解的是，本发明并不局限于上述特定实施方式，本领域技术人员可以在权利要求的范围内做出各种变形或修改，这并不影响本发明的实质内容。

Claims (3)

1.一种降低起始电压及导通电阻的MOSFET组，其特征在于，包括源极、电介质层、N+源区、多晶硅栅极、栅极电介质层、漏极、P井区、N型外延区、P型区域,电介质层位于源极和多晶硅栅极之间，N+源区位于栅极电介质层的侧面，栅极电介质层位于多晶硅栅极的***，漏极位于N型外延区的下方，P型区域位于P井区内，P井区位于N+源区的下方。
2.根据权利要求1所述的降低起始电压及导通电阻的MOSFET组，其特征在于，所述栅极电介质层的底端和N型外延区之间设有P型植入区。
3.根据权利要求1所述的降低起始电压及导通电阻的MOSFET组，其特征在于，所述P型区域的长度大于N+源区的长度。
CN201510466253.2A 2015-07-31 2015-07-31 降低起始电压及导通电阻的mosfet组件 Pending CN105161537A (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103247681A (zh) * 2012-02-02 2013-08-14 万国半导体股份有限公司 沟槽底部氧化物屏蔽以及三维p-本体接触区的纳米mosfet
WO2014146870A1 (de) * 2013-03-18 2014-09-25 Robert Bosch Gmbh Gleichrichterdiode
US9093522B1 (en) * 2014-02-04 2015-07-28 Maxpower Semiconductor, Inc. Vertical power MOSFET with planar channel and vertical field plate
CN204857733U (zh) * 2015-07-31 2015-12-09 上海晶亮电子科技有限公司 降低起始电压及导通电阻的mosfet组件

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103247681A (zh) * 2012-02-02 2013-08-14 万国半导体股份有限公司 沟槽底部氧化物屏蔽以及三维p-本体接触区的纳米mosfet
WO2014146870A1 (de) * 2013-03-18 2014-09-25 Robert Bosch Gmbh Gleichrichterdiode
US9093522B1 (en) * 2014-02-04 2015-07-28 Maxpower Semiconductor, Inc. Vertical power MOSFET with planar channel and vertical field plate
CN204857733U (zh) * 2015-07-31 2015-12-09 上海晶亮电子科技有限公司 降低起始电压及导通电阻的mosfet组件

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