CN105137864A - Lower computer coordinative control SoC chip for spacecraft - Google Patents
Lower computer coordinative control SoC chip for spacecraft Download PDFInfo
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- CN105137864A CN105137864A CN201510465834.4A CN201510465834A CN105137864A CN 105137864 A CN105137864 A CN 105137864A CN 201510465834 A CN201510465834 A CN 201510465834A CN 105137864 A CN105137864 A CN 105137864A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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Abstract
The invention provides a lower computer coordinative control SoC chip for a spacecraft, and the chip comprises a single-core Sparc V8 processor, a Spacewire bus interface, a 1553B bus interface, an external storage unit interface, a multichannel analog-digital converter ADC, a digital-analog converter DAC, an instruction pulse output interface, a serial communication interface UART, a PWM output interface, and a universal IO interface. The chip is integrated with most of common function interfaces of a lower computer in a spaceborne distributed control system, greatly improves the integration degree of an electronic system of the spacecraft, can remarkably reduce the weight, size and power consumption of all electronic subsystems of a satellite, is more reliable in operation, is simple in system design, and is of great significance to the miniaturization development of the satellite.
Description
Technical field
The present invention relates to aerospace electron technical field, particularly a kind of spacecraft slave computer association controls SoC chip.
Background technology
Aerospace electron Integrated system is installed on the spacecraft such as satellite, airship usually, and it is mainly used in the function such as collection, process, route, storage realizing aerospace information.The development of the development of aerospace electron Integrated system and Computer Control Technology, the communication technology, digital integration technology and numerical model analysis SoC technology is closely related.Along with the develop rapidly progress of correlation technique, aerospace electron Integrated system develops into current dcs from simple centralized control.
Namely the most typical framework of satellite distributed control system is CTU (CentralTerminalUnit, central control unit), RTU (RemoteTerminalUnit, Star Service far puts unit) combined electrical subsystem, comprehensive now satellite platform each RTU/ expanding element and each subsystem slave computer are to signals collecting, data are packed, interface communication, control the existing demand of output etc., propose " the spacecraft slave computer association controller SoC " of the above-mentioned all kinds of resource of integrated some, more high integration can substitute existing each subsystem slave computer, and as the basic ingredient of each RTU/ expanding element.The entity of the more high integration that the realization of this SoC can provide interface resource to serve as whole star.
Key components mainly each quasi-controller in the slave computer of each subsystem of current version, is generally realized by CPU and fpga chip.
Summary of the invention
For defect of the prior art, the object of this invention is to provide a kind of spacecraft slave computer association and control SoC chip.
Control SoC chip according to a kind of spacecraft slave computer association provided by the invention, comprising: monokaryon SparcV8 processor core, Spacewire bus interface, 1553B bus interface, external memory interface, multipath A/D converter ADC, digital to analog converter DAC, command pulse output interface, serial communication interface UART, PWM output interface, general I/O interface;
Described monokaryon SparcV8 processor core, Spacewire bus interface, 1553B bus interface, external memory interface are connected to AMBAAXI bus;
Described multipath A/D converter ADC, digital to analog converter DAC, command pulse output interface, serial communication interface UART, PWM output interface, general I/O interface are connected to AMBAAPB bus;
Described AMBAAXI bus and AMBAAPB bus are connect by AXI/APB bridging.
Preferably, described monokaryon SparcV8 processor core, as the main equipment on sheet, provides association's processing capacity of slave computer, the control and management of auxiliary whole star electronic system CTU, and the maintenance being responsible for each interface unit on sheet controls.
Preferably, described Spacewire bus interface and 1553B bus interface are used for the satellite-bone bus connection communication with house keeping computer CTU and subsystem slave computer.
Preferably, described monokaryon SparcV8 processor core adopts LEON2-FTSparcV8 processor core;
The integrated Spacewire router of described Spacewire bus interface and terminal control unit, for realizing the expansion of multistage route network topological structure;
Described 1553B bus interface can be operated in BC pattern and RT pattern, supports the differentiated control of 1553B bus;
Described external memory interface supports SRAM, SDRAM, FLASH;
Described multipath A/D converter ADC supports 128 road analog acquisition passages, the AD converter module of embedded 12 precision, and the sheet external pin of multipath A/D converter ADC, except analog input signal, separately has 7 Port Multiplier address output signal lines;
Described digital to analog converter DAC is used for discrete control signal to be converted to analog output, and Embedded D/A converter of digital to analog converter DAC is also equipped with the demodulation multiplexer on 8 tunnels, and the resolution of DAC is 16;
Described command pulse output interface, for completing the decoding of instruction, exports the pulse signal of one fixed width, supports that 32 tunnel pulses export and controls;
Described serial communication interface UART can be configured to asynchronous serial communication or the 3 line synchronous serial communications of standard as required, can self-adaptation export;
Described PWM output interface configuration register comprises: frequency division register, pulse width register, period register, exports the cycle, dutycycle is configurable;
Described general I/O interface, according to the value of direction register and data register in sheet, can configure input and output direction and the electrical level polar of any road interface.
Compared with prior art, the present invention has following beneficial effect:
1, the invention provides a kind of reliability and integrated level is high, the SOC (system on a chip) of volume and lower, the integrated all kinds of aircraft slave computer control interface of power consumption.
2, the present invention is integrated with most of common function interfaces of slave computer in dcs on satellite, substantially increases the synthesization degree of aircraft electrical subsystem;
3, the present invention significantly reduces the quality volume power consumption of each subsystem electronic system of satellite;
4, the present invention's operation is more reliable, system is simple, significant to the small light development of satellite.
Accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to the following drawings, other features, objects and advantages of the present invention will become more obvious:
Fig. 1 is chip system structural representation of the present invention;
Fig. 2 is of the present invention interior Spacewire node IP nuclear structure schematic diagram;
Fig. 3 is of the present invention interior Spacewire accessor nuclear structure schematic diagram;
Fig. 4 is the illustrative view of functional configuration of of the present invention interior 1553B bus interface;
Fig. 5 is well heater command pulse output control function structural representation of the present invention;
Fig. 6 is the illustrative view of functional configuration of of the present invention interior PWM output interface.
Embodiment
Below in conjunction with specific embodiment, the present invention is described in detail.Following examples will contribute to those skilled in the art and understand the present invention further, but not limit the present invention in any form.It should be pointed out that to those skilled in the art, without departing from the inventive concept of the premise, some changes and improvements can also be made.These all belong to protection scope of the present invention.
Along with develop rapidly and the maturation of large scale integrated circuit and asic technology, plate level function i ntegration traditional on satellite is become possibility in a chip.Spacecraft slave computer of the present invention association controls SoC chip can the several functions interface of integrated Spacecraft Electronic system, elaborates below to the structure and fuction of this chip system.
The present invention relates to the special IC controlled towards spacecraft slave computer, disclose a kind of spacecraft slave computer association and control SoC chip, with reference to figure 1, comprising: monokaryon SparcV8 processor core, Spacewire bus interface, 1553B bus interface, external memory interface, multipath A/D converter ADC, digital to analog converter DAC, command pulse output interface, serial communication interface UART, PWM output interface, general I/O interface (GPIO).Wherein, SparcV8 processor core, Spacewire bus interface, 1553B bus interface, external memory interface are connected to AMBAAXI bus, multipath A/D converter ADC, digital to analog converter DAC, command pulse output interface, serial communication interface UART, PWM output interface, general I/O interface (GPIO) are connected to AMBAAPB bus, and AMBAAXI bus and AMBAAPB bus are connect by AXI/APB bridging.
Described monokaryon SparcV8 processor core adopts LEON2-FTSparcV8 processor core, this processor core arithmetic capability under 100MHz works dominant frequency reaches 86MIPS, it has 5 grades of flowing water, 4K director data buffer memory, and is equipped with the timer of interruptable controller and 32.
The integrated Spacewire router of described Spacewire bus interface and terminal control unit, can realize the expansion of multistage route network topological structure.
Described 1553B bus interface can be operated in BC pattern and RT pattern, supports the differentiated control of 1553B bus.
Described external memory interface supports SRAM, SDRAM, FLASH, is a kind of general purpose memory interface, can adapt to storer conventional in space flight.
Described multipath A/D converter ADC supports 128 road analog acquisition passages, and the AD converter module of embedded 12 precision, slewing rate is not less than 100Kbps.Sheet external pin, except analog input signal, separately has 7 Port Multiplier address output signal lines.
Described digital to analog converter DAC is used for discrete control signal to be converted to analog output, if magnetic force is apart from device control, gyro control etc.Embedded D/A converter is also equipped with the demodulation multiplexer on 8 tunnels, and the resolution of DAC is 16.
Described command pulse output interface, for completing the decoding of instruction, exports the pulse signal of one fixed width.Comprise instruction buffer FIFO, instruction count unit, instruction decoding unit and instruction output unit.This command pulse output interface is supported that 32 tunnel pulses export and is controlled.
Described serial communication interface UART can be as required, be configured to asynchronous serial communication (containing start stop bit, check bit etc.) or the 3 line synchronous serial communications (containing clock, gating, data-signal) of standard, self-adaptation can export, sheet is supported 8 tunnel UART interface.
Described PWM output interface configuration register comprises: frequency division register, pulse width register, period register, exports the cycle, dutycycle is configurable; The highest frequency supported is not less than 500KHz, sheet maps the PWM output interface that 8 tunnels are identical.
Described general I/O interface (GPIO), according to the value of direction register and data register in sheet, can configure input and output direction and the electrical level polar of any road interface, sheet be supported 32 road GPIO.
With reference to figure 1, system of the present invention comprises: monokaryon SparcV8 processor core 1, Spacewire bus interface 2,1553B bus interface 3, external memory interface 4, multipath A/D converter ADC5, digital to analog converter DAC6, command pulse output interface 7, serial communication interface UART8, PWM output interface 9, general I/O interface (GPIO) 10; Wherein, described monokaryon SparcV8 processor core 1, Spacewire bus interface 2,1553B bus interface 3, external memory interface 4 are connected to AMBAAXI bus 11, described multipath A/D converter ADC5, digital to analog converter DAC6, command pulse output interface 7, serial communication interface UART8, PWM output interface 9, general I/O interface (GPIO) 10 are connected to AMBAAPB bus 12, and described AMBAAXI bus 11 is connected by AXI/APB bridge 13 with AMBAAPB bus 12.
Below the function of modules in present system is described further.
Monokaryon SparcV8 processor core is the processor of chip system inside of the present invention, and for receiving the instruction message in external communication bus, the functional module of commander and control chip performs the operation of specifying, and completes required controlling functions.In the present embodiment, SparcV8 processor core adopts LEON2-FTSparcV8 processor core, and this processor core arithmetic capability under 100MHz works dominant frequency reaches 86MIPS, can meet high speed data transfer demand.It has 5 grades of flowing water, 4K director data buffer memory, and is equipped with timer and the external memory interface of interruptable controller and 32.Described monokaryon SparcV8 processor core 1 adopts existing techniques in realizing.
Spacewire bus interface is in order to complete the exchange of high-speed data.Consider the extensibility that bus is applied, Embedded Spacewire router and node IP kernel, realize the expansion of multistage route network topological structure.Fig. 2 gives the illustrative view of functional configuration of described Spacewire node IP kernel.This node IP kernel comprises: data transmitter, data sink, protocol state machine, receive clock data recovery module, tranmitting data register module, transmission buffering FIFO, reception buffering FIFO, timer module.Fig. 3 gives the illustrative view of functional configuration of described Spacewire router IP kernel.This router IP kernel comprises: Spacewire interface module, TimeCode processing module, winding transmission control module, RMAP protocol module, dma controller module.
1553B bus interface is for realizing BC and the RT function of 1553B bus.Under 1553B bus interface of the present invention can be operated in BC or RT pattern respectively, support the hierarchical design of 1553B bus, as Star Service 1553B bus and load 1553B bus two-stage bus.Fig. 4 is the functional schematic of described 1553B bus interface, as shown in Figure 4, comprising: AXI is from equipment interface, BC module, RT module, ram in slice module, channel selecting module, scrambler A, scrambler B, demoder A, demoder B.
Multipath A/D converter ADC achieves Embedded analog to digital converter, for gathering analog signals, completing slave computer health status monitoring or measuring subsystem data, to complete controlling functions.Described multipath A/D converter ADC5 supports 128 road analog acquisition passages, and containing 7 address output line on sheet, resolution is 12, and switching rate is not less than 100Kbps.In sheet, data storage area is the block RAM of a 128x12bits.After described multipath A/D converter ADC is started by main equipment monokaryon SparcV8 processor core on sheet, automatically gather one from low to high and take turns 128 paths, gathered in a road autostore to sheet in data storage area, and triggered interrupts signal.
Digital to analog converter DAC is used for discrete control signal to be converted to analog output, if magnetic force is apart from device control, gyro control etc.Wherein gyro control needs 4 road DA to complete control, for ease of expansion, and association's controller SoC Embedded 8 road DA output interface.The resolution of DAC is also 16bit, and implementation is the demodulation multiplexer that a DAC is equipped with 8 tunnels.
Command pulse output interface is supported that 32 tunnel pulses export and is controlled.Each road can separate configurations output pulse width.Described spacecraft association controller SoC Embedded instruction buffer, Instruction decoding and instruction mode setting logic function, and support impulse type, level-type instruction, pulse width can be arranged; Support address matching operation, reduce peripheral decoding scheme; Support command status is inquired about.This command pulse output interface can be applicable to the drived control of solenoid valve, latching valve, relay, well heater even load.Fig. 5 is well heater controlling functions schematic diagram, and wherein, front two-stage instruction buffer and Instruction decoding are at Embedded.
Serial communication interface UART is the functional module communicated with unit in system, and by data by operation transmission conversion between serial communication and parallel communications, UART is used in usually with in the connection of other communication interfaces (as RS232, RS422 etc.).This UART can be as required, be configured to asynchronous serial communication (containing start stop bit, check bit etc.) or the 3 line synchronous serial communications (containing clock) of standard, be mainly used in following aspect: the interface (asynchronous serial communication) between remote control PCM and remote measurement pcm interface (synchronous serial communication), each unit of satellite electron system.Sheet is supported serial communication interface UART8 road, every road respectively containing IO interface, and can be configured to synchronous serial interface or asynchronous serial port, according to requirements configures the information such as start stop bit, check bit sum traffic rate; For synchronous serial interface, the direction of clock, gate, data line, speed, phase place are all configurable.
PWM output interface is for generating pulse-width signal.In the present embodiment, the pwm signal that generate has 8 tunnels, and this interface is actual is one-period pulse producer, and cycle, the dutycycle of pulse can configure with 32 bit registers.Described PWM output interface comprises PWM period register, PWM pulse width register, PWM forward position register, PWM configuration register.Functional block diagram as shown in Figure 6.
General I/O interface (GPIO) comprises 32 ports, and every Single port can be configured to input or output state, and independently can control data transfer direction and the output level state of each port, all of the port default setting is input pin.
Above specific embodiments of the invention are described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, those skilled in the art can make a variety of changes within the scope of the claims or revise, and this does not affect flesh and blood of the present invention.
Claims (4)
1. a spacecraft slave computer association controls SoC chip, it is characterized in that, comprising: monokaryon SparcV8 processor core, Spacewire bus interface, 1553B bus interface, external memory interface, multipath A/D converter ADC, digital to analog converter DAC, command pulse output interface, serial communication interface UART, PWM output interface, general I/O interface;
Described monokaryon SparcV8 processor core, Spacewire bus interface, 1553B bus interface, external memory interface are connected to AMBAAXI bus;
Described multipath A/D converter ADC, digital to analog converter DAC, command pulse output interface, serial communication interface UART, PWM output interface, general I/O interface are connected to AMBAAPB bus;
Described AMBAAXI bus and AMBAAPB bus are connect by AXI/APB bridging.
2. spacecraft slave computer association according to claim 1 controls SoC chip, it is characterized in that, described monokaryon SparcV8 processor core is as the main equipment on sheet, association's processing capacity of slave computer is provided, the control and management of auxiliary whole star electronic system CTU, the maintenance being responsible for each interface unit on sheet controls.
3. spacecraft slave computer association according to claim 1 controls SoC chip, it is characterized in that, described Spacewire bus interface and 1553B bus interface are used for the satellite-bone bus connection communication with house keeping computer CTU and subsystem slave computer.
4. spacecraft slave computer association according to claim 1 controls SoC chip, it is characterized in that,
Described monokaryon SparcV8 processor core adopts LEON2-FTSparcV8 processor core;
The integrated Spacewire router of described Spacewire bus interface and terminal control unit, for realizing the expansion of multistage route network topological structure;
Described 1553B bus interface can be operated in BC pattern and RT pattern, supports the differentiated control of 1553B bus;
Described external memory interface supports SRAM, SDRAM, FLASH;
Described multipath A/D converter ADC supports 128 road analog acquisition passages, the AD converter module of embedded 12 precision, and the sheet external pin of multipath A/D converter ADC, except analog input signal, separately has 7 Port Multiplier address output signal lines;
Described digital to analog converter DAC is used for discrete control signal to be converted to analog output, and Embedded D/A converter of digital to analog converter DAC is also equipped with the demodulation multiplexer on 8 tunnels, and the resolution of DAC is 16;
Described command pulse output interface, for completing the decoding of instruction, exports the pulse signal of one fixed width, supports that 32 tunnel pulses export and controls;
Described serial communication interface UART can be configured to asynchronous serial communication or the 3 line synchronous serial communications of standard as required, can self-adaptation export;
Described PWM output interface configuration register comprises: frequency division register, pulse width register, period register, exports the cycle, dutycycle is configurable;
Described general I/O interface, according to the value of direction register and data register in sheet, can configure input and output direction and the electrical level polar of any road interface.
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Application publication date: 20151209 |