CN101377793A - SOC chip logic verification method for server safe monitoring management - Google Patents
SOC chip logic verification method for server safe monitoring management Download PDFInfo
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- CN101377793A CN101377793A CNA2008101398754A CN200810139875A CN101377793A CN 101377793 A CN101377793 A CN 101377793A CN A2008101398754 A CNA2008101398754 A CN A2008101398754A CN 200810139875 A CN200810139875 A CN 200810139875A CN 101377793 A CN101377793 A CN 101377793A
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Abstract
The invention provides a server safety monitoring and management used SOC chip logic verification method. In the SOC chip logic verification method, a field programmable gate array FPGA is used for establishing a server safety monitoring and management SOC chip system. The system comprises a software platform and a hardware platform. The hardware platform comprises a chip logic verification model with the FPGA as the carrier of the model, various functional modules and interface modules thereof. The functional modules and the interface modules are connected with the chip logic verification model. The software platform is used for configuration of the chip logic verification model, the functional modules and the interface modules and processing related data, and inputting signals to the interface modules; the incoming signals of the chip logic verification model are generated through each functional module; control signals over software are generated through the chip logic verification model; the signals are converted into software display scalar quantities through each of the functional modules and the interface modules thereof.
Description
Technical field
The present invention relates to a kind of integrated circuit (IC) design field, the logic verification method of a kind of specifically server safe monitoring management SOC (System On Chip, SOC (system on a chip)) chip.
Background technology
Along with the development of microelectric technique, the integrated level of chip is more and more higher, and the design of SOC chip is used more and more general, but its checking and test job become increasingly complex.Any a chip all will pass through algorithm design, system design, RTL design, allocation plan and comprehensive, layout, connect up, authenticates to the process of the such complexity of flow, verifies that wherein this step is full of in all steps.Therefore, we can say that checking is a most important parts in the chip production process.The logic checking of chip passed through application-specific integrated circuit ASIC more in the past.Because the application-specific integrated circuit ASIC function singleness, reusable must not cause the raising greatly of R﹠D costs.And the appearance of on-site programmable gate array FPGA has then improved application-specific integrated circuit ASIC function singleness, the shortcoming of reusable not, makes chip development flow process flexible and convenient more.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of logic verification method of server safe monitoring management SOC chip, makes in this way, can improve SOC chip design performance, shortens the construction cycle of SOC chip.
In order to address the above problem, this patent provides a kind of server safe monitoring management SOC chip logic verification method, this method is to utilize on-site programmable gate array FPGA to build a server safe monitoring management SOC chip logic verification method, this method comprises software platform and hardware platform, hardware platform comprises chip logic checking model, types of functionality module and the interface module thereof of being done the carrier of model by FPGA, and wherein functional module and interface module thereof link to each other with the chip logic checking model.Software platform is used for realizing the configuration of chip logic checking model, functional module and interface module thereof and related data are handled, and signal is input to interface module, produce the input signal of chip logic checking model by each functional module, by the control signal of chip logic checking model generation, be converted into software by each functional module and interface module thereof and show scalar software.
Verification step is as follows:
(1) describes the chip logic checking model by hardware description language, make it meet SOC chip logic function;
(2) software platform is configured FPGA by functional module and interface thereof, and the result of configuration makes FPGA become SOC chip logic checking model, and is identical with the SOC chip logic function of required checking;
(3) software platform produces the checking initiation command, by functional module and interface module thereof signal is sent into the chip logic checking model.Signal is sent to functional module and interface module thereof through the logical process of chip logic checking model, is converted into software by each functional module and interface module thereof and shows scalar;
(4) software platform produces checking the finish command, by functional module and interface module thereof signal is sent into the chip logic checking model, and the generation Data Receiving was finished signal after model received the finish command, finished checking.
Wherein, simulation waveform output and the oscillographic waveform of the chip logic function in step (1), (2) by software platform exported and verified its logic function.In step (3), (4), all signals are by after the data acquisition, the checking conclusion that draws.
The invention has the beneficial effects as follows, method of the present invention is to utilize FPGA to build SOC chip logic checking model, the system verification method that utilization software platform and hardware platform combine, the correctness of check SOC chip logic, and can in time be corrected mistake in the logical design and problem, thereby improved the design performance of SOC chip, shortened the construction cycle.
Description of drawings
Fig. 1 is a server safe monitoring management SOC chip logic checking model structure synoptic diagram;
Fig. 2 is the hardware platform structural representation;
Fig. 3 is a SOC chip logic verification method process flow diagram.
Embodiment
Fig. 1 is a server safe monitoring management SOC logic checking model synoptic diagram.Wherein, PWM module 3, SMBUS driver module 4, LCD driver module 5, SPI control module 6, I2S control module 7, DSU serial ports 8, JTAG9, Ethernet driver module 10, PS/2 driver module 11, USB main equipment module 12 and LPC control module 13 link to each other with 32 risc processors by the AMBA bus.
D/A modular converter 14 links to each other with I2S control module 7, and VGA control module 15, SDRAM storer 16 link to each other with 32 risc processors by the EMI bus, and LPC Flash17 links to each other with LPC control module 13 by lpc bus.Above-mentioned module all is configured among the FPGA with the form of code except D/A modular converter 14, VGA control module 15, SDRAM storer 16 and LPC Flash17, forms SOC logic checking model 1.
Fig. 2 is the hardware platform structural representation.Wherein, fan wind speed control system 18 links to each other with PWM module 3,6 road SMBUS19 link to each other with SMBUS driver module 4, LCD screen 20 links to each other with LCD driver module 5, A/D converter 21 links to each other with SPI control module 6, PC and software platform link to each other with JTAG9 with DSU serial ports 8, Ethernet PHY circuit 23 links to each other with Ethernet driver module 10, keyboard/mouse 24 links to each other with PS/2 driver module 11, USB flash disk 25 links to each other with USB main equipment module 12, VGA output 26 links to each other with VGA control module 15, and audio frequency is exported 27 and linked to each other with D/A modular converter 14.PC and software platform 22 are configured SOC logic checking model by JTAG9; By DSU serial ports 8, make the intercommunication of PC and software platform 22 and SOC logic checking model, debug.
To sum up reach with reference to shown in Figure 3, this patent makes the chip checking process simplification, has improved the design performance of SOC chip, has shortened the construction cycle, thereby, have good value for applications.
Claims (7)
1. SOC chip logic verification method for server safe monitoring management, it is characterized in that this method is to utilize on-site programmable gate array FPGA to build a server safe monitoring management SOC chip system, this system comprises software platform and hardware platform, hardware platform comprises the chip logic checking model of being made the carrier of model by on-site programmable gate array FPGA, types of functionality module and interface module thereof, wherein functional module and interface module thereof link to each other with the chip logic checking model, software platform is used for realizing to the chip logic checking model, the configuration of functional module and interface module thereof and related data are handled, and signal is input to interface module, produce the input signal of chip logic checking model by each functional module, by the control signal of chip logic checking model generation, be converted into software by each functional module and interface module thereof and show scalar software.
2, SOC chip logic verification method according to claim 1, it is characterized in that: on-site programmable gate array FPGA is configured by software platform, needing to realize the logic function of checking SOC chip, and logic function is realized by hardware description language.
3, SOC chip logic verification method according to claim 1 is characterized in that verification step is as follows:
(1) describes the chip logic checking model by hardware description language, make it meet SOC chip logic function;
(2) software platform is configured on-site programmable gate array FPGA by functional module and interface thereof, and the result of configuration makes on-site programmable gate array FPGA become SOC chip logic checking model, and is identical with the SOC chip logic function of required checking;
(3) software platform produces the checking initiation command, by functional module and interface module thereof signal is sent into the chip logic checking model, signal is sent to functional module and interface module thereof through the logical process of chip logic checking model, is converted into software by each functional module and interface module thereof and shows scalar;
(4) software platform produces checking the finish command, by functional module and interface module thereof signal is sent into the chip logic checking model, and the generation Data Receiving was finished signal after model received the finish command, finished checking.
4, SOC chip logic verification method according to claim 3, its feature also is: in step (3), (4), all signals are by after the data acquisition, the checking conclusion that draws.
5, SOC chip logic verification method according to claim 3 is characterized in that: simulation waveform output and the oscillographic waveform of the chip logic function in step (1), (2) by software platform exported and verified its logic function.
6, SOC chip logic verification method according to claim 1, it is characterized in that, server safe monitoring management SOC logic checking model, comprise the PWM module, the SMBUS driver module, the LCD driver module, the SPI control module, the I2S control module, the DSU serial ports, JTAG, the Ethernet driver module, the PS/2 driver module, USB main equipment module, the LPC control module, the D/A modular converter, the VGA control module, SDRAM storer and LPC Flash, wherein, the PWM module, the SMBUS driver module, the LCD driver module, the SPI control module, the I2S control module, the DSU serial ports, JTAG9, the Ethernet driver module, the PS/2 driver module, USB main equipment module links to each other with 32 risc processors by the AMBA bus with the LPC control module, the D/A modular converter links to each other with the I2S control module, the VGA control module, the SDRAM storer links to each other with 32 risc processors by the EMI bus, LPC Flash links to each other with the LPC control module by lpc bus, above-mentioned module is except the D/A modular converter, the VGA control module, outside SDRAM storer and the LPCFlash, all the form with code is configured in the on-site programmable gate array FPGA, forms SOC logic checking model.
7, SOC chip logic verification method according to claim 1, it is characterized in that, the hardware platform structure comprises, fan wind speed control system, 6 road SMBUS, the LCD screen, A/D converter, PC and software platform, Ethernet PHY circuit, keyboard/mouse, USB flash disk, VGA output, audio frequency output, wherein, fan wind speed control system links to each other with the PWM module, 6 road SMBUS link to each other with the SMBUS driver module, the LCD screen links to each other with the LCD driver module, A/D converter links to each other with the SPI control module, PC and software platform link to each other with JTAG with the DSU serial ports, Ethernet PHY circuit links to each other with the Ethernet driver module, keyboard/mouse links to each other with the PS/2 driver module, USB flash disk links to each other with USB main equipment module, VGA output links to each other with the VGA control module, audio frequency output links to each other with the D/A modular converter, and PC and software platform are configured SOC logic checking model by JTAG; By the DSU serial ports, make the intercommunication of PC and software platform and SOC logic checking model, debug.
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| CNA2008101398754A CN101377793A (en) | 2008-09-22 | 2008-09-22 | SOC chip logic verification method for server safe monitoring management |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101605071B (en) * | 2009-07-02 | 2011-12-07 | 中兴通讯股份有限公司 | Method and device for verifying transport protocol chip |
| CN102497596A (en) * | 2011-12-02 | 2012-06-13 | 青岛海信信芯科技有限公司 | Debugging device and verification method of field programmable gate array (FPGA) platform of television network signal |
| CN105137864A (en) * | 2015-07-31 | 2015-12-09 | 上海卫星工程研究所 | Lower computer coordinative control SoC chip for spacecraft |
| CN105487950A (en) * | 2015-11-30 | 2016-04-13 | 致象尔微电子科技（上海）有限公司 | Chip front-end simulation detection method and apparatus |
| CN109542518A (en) * | 2018-10-09 | 2019-03-29 | 华为技术有限公司 | The method of chip and bootrom |
| CN110399645A (en) * | 2019-06-28 | 2019-11-01 | 深圳忆联信息***有限公司 | FPGA prototype verification acceleration system and implementation method based on solid state hard disk |
| CN111859832A (en) * | 2020-07-16 | 2020-10-30 | 山东云海国创云计算装备产业创新中心有限公司 | Chip simulation verification method and device and related equipment |
| CN114860519A (en) * | 2022-04-08 | 2022-08-05 | 中国人民解放军国防科技大学 | Multi-chip combined verification method and device for large-scale ASIC (application specific integrated circuit) chip |
-
2008
- 2008-09-22 CN CNA2008101398754A patent/CN101377793A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101605071B (en) * | 2009-07-02 | 2011-12-07 | 中兴通讯股份有限公司 | Method and device for verifying transport protocol chip |
| CN102497596A (en) * | 2011-12-02 | 2012-06-13 | 青岛海信信芯科技有限公司 | Debugging device and verification method of field programmable gate array (FPGA) platform of television network signal |
| CN105137864A (en) * | 2015-07-31 | 2015-12-09 | 上海卫星工程研究所 | Lower computer coordinative control SoC chip for spacecraft |
| CN105487950A (en) * | 2015-11-30 | 2016-04-13 | 致象尔微电子科技（上海）有限公司 | Chip front-end simulation detection method and apparatus |
| CN105487950B (en) * | 2015-11-30 | 2019-04-09 | 致象尔微电子科技（上海）有限公司 | Chip front-end simulation detection method and device |
| CN109542518A (en) * | 2018-10-09 | 2019-03-29 | 华为技术有限公司 | The method of chip and bootrom |
| CN110399645A (en) * | 2019-06-28 | 2019-11-01 | 深圳忆联信息***有限公司 | FPGA prototype verification acceleration system and implementation method based on solid state hard disk |
| CN111859832A (en) * | 2020-07-16 | 2020-10-30 | 山东云海国创云计算装备产业创新中心有限公司 | Chip simulation verification method and device and related equipment |
| CN111859832B (en) * | 2020-07-16 | 2022-07-08 | 山东云海国创云计算装备产业创新中心有限公司 | Chip simulation verification method and device and related equipment |
| CN114860519A (en) * | 2022-04-08 | 2022-08-05 | 中国人民解放军国防科技大学 | Multi-chip combined verification method and device for large-scale ASIC (application specific integrated circuit) chip |
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