CN105117513A - FPGA (Field Programmable Gate Array) layout and wiring delay characteristic testing method - Google Patents
FPGA (Field Programmable Gate Array) layout and wiring delay characteristic testing method Download PDFInfo
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Abstract
The present invention provides an FPGA layout and wiring delay characteristic testing method. The method comprises: S1, performing structural analysis on an FPGA; S2, according to a result obtained by the analysis in the step S1, designing a testing module and corresponding testing software; S3, performing synthesis on the testing module obtained in the step S2 by using a synthesis tool; S4, performing compilation on a synthesis result obtained in the step S3 by using a compiling tool; S5, performing a constraint by using a layout tool on the basis of the step S4, performing assignment on the testing module according to an FPGA overall layout characteristic, and performing assignment location on a register; and S6, performing layout and wiring by using a layout and wiring tool on the basis of the step S5, and obtaining each signal path delay characteristic by means of a time sequence analysis tool. According to the FPGA layout and wiring delay characteristic testing method provided by the present invention, the test module is designed by analyzing the FPGA structural characteristic, and manual layout and wiring are performed, so that the signal path delay characteristic is easy to know.
Description
Technical field
The invention belongs to space flight optical remote sensor technical field, particularly relate to a kind of FPGA placement-and-routing time-delay characteristics method of testing, can be applicable to CCD focal plane clock signal optimal design in space flight optical camera imaging circuit.
Background technology
Along with large scale integrated circuit development, FPGA device application is in system complicated at a high speed, and circuit signal high speed, integrality not only depend on device speed and also depend on FPGA design flexibly.Complete FPGA design comprises writes code, comprehensive, emulation, compiling, placement-and-routing and programming test, and placement-and-routing's stage is comparatively large to the performance impact of circuit, is optimal design, puies forward high performance key.
The problem of difficulty is regulated for satellite-based CCD remote sensing camera CCD focal plane sensing circuit time sequence precision, new scheme changes and adopts the present situation that hardware circuit adjustment difficulty was large, debugging cycle is long in the past, proposes to utilize manual intervention placement-and-routing to carry out adjustment to internal register layout to meet and output signal performance requirement.But this just needs, even quantitative test its time delay distribution character qualitative to selected fpga chip.Method of the present invention can test FPGA internal register time-delay characteristics by the method for testing of flexible design, to determine manual intervention placement-and-routing trend.
Summary of the invention
The technical problem to be solved in the present invention is: the problem that can not meet high-precision signal performance for current automatic placement and routing, in order to meet new departure of manual intervention placement-and-routing, adopt a kind of FPGA placement-and-routing time-delay characteristics method of testing, the time delay distribution character of FPGA placement-and-routing is tested, determine artificial placement-and-routing trend, to control, to optimize output signal performance.
Technical scheme of the present invention is: a kind of FPGA placement-and-routing time-delay characteristics method of testing, comprises, S1, carry out structure analysis to FPGA; S2, analyzes the result obtained according to step S1, design test module and corresponding testing software; S3, to the test module that step S2 obtains, utilizes synthesis tool to carry out comprehensively; S4, utilizes compilation tool to compile to the synthesis result that step S3 obtains; S5, the basis of step S4 utilizes layout tool to retrain, and distributes test module according to FPGA integral layout characteristic, carries out distribution location to register; S6, the basis of step S5 utilizes placement-and-routing's instrument carry out placement-and-routing, obtains each signal path time-delay characteristics by timing analysis tool.
Further, the testing software VHDL language in step S2 carrys out code Design, and comprise N number of same test module, test module is two-divider or counter, exports M the PIN pin being connected to FPGA by M register.
Further, being constrained in step S5: N number of test module is distributed, make its output to next stage register meet set up the retention time; By the position of one-level register, layout location is carried out to M signal, belongs to the register position of signal layout at same of same test module counter.
Further, the synthesis tool in step S2 is SynplifyPro, carries out comprehensive.
Further, the compilation tool in step S3 is Complie, compiles.
Further, the placement-and-routing's instrument in step S5 is ChipPlanner placement-and-routing, and timing analysis tool is TimingAnalyzer, carries out time series analysis, can check its signal path delay product.
The present invention's advantage is compared with prior art: the present invention, by analyzing FPGA Structural Feature Design test module, pedestrian's work of going forward side by side placement-and-routing, is easy to understand signal path time-delay characteristics, comprises critical registers and set up retention time t
eXSU, I/O pin exports t
codistribution value characteristic etc.In FPGA design, compared with traditional automatic placement and routing, introduce manual intervention placement-and-routing, have following advantage: critical registers can be controlled and set up retention time t
eXSU; Make not need to increase additional circuit just can be easy to control the deflection between output signal and t
covalue, control accuracy can reach ps level; Reliability, security are higher.
Accompanying drawing explanation
Fig. 1 is the process flow diagram of method of testing of the present invention;
Fig. 2 is method of testing testing software internal logic structure figure of the present invention;
Fig. 3 is method of testing internal register placement-and-routing mode one figure of the present invention;
Fig. 4 is method of testing internal register placement-and-routing mode two figure of the present invention.
Embodiment
FPGA placement-and-routing of the present invention time-delay characteristics method of testing, its step is as follows:
(1) FPGA structure analysis, analyzes its feature, comprises its scale, clock sources, logical resource and I/O pin etc.;
(2) result obtained by step (1) analysis, utilize the corresponding testing software of EDA (ElectronicDesignAutomatic) tool design: N number of same test module, each test module outputs to M the pin of FPGA by M register;
(3) to the testing software that step (2) obtains, EDA synthesis tool is utilized to carry out comprehensively;
(4) EDA compilation tool is utilized to compile to step (3) synthesis result;
(5) on the basis of step (4), utilize EDA layout tool to retrain, according to FPGA integral layout characteristic, N number of test module is distributed, distribution location is carried out to M × N number of register;
(6) on the basis of step (5), carry out placement-and-routing by eda tool, each signal path time-delay characteristics can be obtained by time series analysis device, comprise critical registers and set up retention time t
eXSU, I/O pin exports t
codistribution value characteristic.
Testing software in described step (2), carrys out code Design by VHDL language, comprises N number of same test module, and test module can be two-divider or counter, and it exports M the PIN pin being connected to FPGA by M register.
Being constrained in described step (5): distribute N number of test module, balance FPGA resource as far as possible, makes it output to next stage register and meets t
eXSUkeep Time Created; By the position of one-level register, layout location is carried out to M signal, belongs to the register position of signal layout at same of same test module counter.
EDA synthesis tool in described step (2) is SynplifyPro, carries out comprehensive.
EDA compilation tool in described step (3) is Complie, compiles.
EDA placement-and-routing instrument in described step (5) is ChipPlanner placement-and-routing, and timing analysis tool is TimingAnalyzer, carries out time series analysis, can check its signal path delay product.(SynplifyPro is business tool software, and Complie, ChipPlanner are liberoIDEPlatinum Software tool, all belongs to public technology field.)
One embodiment of the present of invention are: FPGA selects certain company's chip, and developing instrument selects corresponding eda tool platform, and SynplifyPro selected by synthesis tool, adopt VHDL language to design.
First, for certain company's fpga chip, recognize that this chip structure forms by Datasheet and be made up of two kinds of logic modules: block of registers and combined logic block; Clock sources has 1 external hardware clock, 4 global clocks; Chip-scale is 7.2 ten thousand; I/OPIN pin is greater than 160.Therefore consider equilibrium of stock, design four test modules, 80 PIN pin output signals.In actual applications, test module complexity and the balanced design of number of pins energy, do not design too numerous and jumbled simultaneously, can affect placement-and-routing's test effect.
Under eda tool platform, it is identical for designing four test modules, for convenience of understanding, so simplicity of design test module is two-divider, is critical registers, and its position determines that next stage register keeps setting up t
eXSU.Four two-dividers export four signals, respectively separate 9 output to PIN pin through one-level register by four signals, and this grade of register determines the t of output signal
co, retrain in VHDL code, make signal when comprehensive not optimised fall.
Carry out comprehensive in SynplifyPro, in eda tool, Compile external member compiles, ChipPlanner external member carries out assignment constraints, four two-divider positions are as Fig. 3, shown in Fig. 4,9 register position that each two-divider connects are come according to predetermined directional spreding, be satisfied maintenance Time Created simultaneously, frequency divider (i.e. register) position is not distributed too far away be connected next stage register position distance, carries out placement-and-routing after completing.Open TimingAnalyzer external member and carry out time series analysis, after can viewing placement-and-routing, the result of each signal path, comprises t
eXSU, t
covalue etc.When this afterbody register layout, as far as possible a point several situation is considered to carry out: make register symmetrical and symmetrical to examine or check its device time delay symmetry up and down; Be distributed in row different around two divided-frequency register and identical row, to determine different lines or same column time-delay characteristics; Be distributed in two parts of frequently different row and going together mutually, with the time-delay characteristics determining different rows or go together mutually around registers; Repeat above several distributed layout, until understand whole device layout situation.
Design a simple test software with an embodiment below to further illustrate distribution layout of the present invention.Specifically be implemented as follows:
In this example, design four test modules, each test module structure as shown in Figure 2, forms a two-divider by a d type flip flop, outputs to outside PIN pin after major clock two divided-frequency through oppositely separating 9 signals through one-level latch.When placement-and-routing, four triggers are assigned to four districts A, B, C and D respectively, hold extraction 9 identical signals to be drawn out to PIN pin by after one-level latch (1 ~ 9) after two reversers by a trigger Q, the position of reverser can affect t
eXSU36 latch positions as shown in Figure 3, during layout, distributing from the position close to PIN pin, make 36 symmetrical, laterally zygomorphic register position of latch distribution, and respective 9 registers being distributed in A, B, C and D tetra-districts in different rows, different lines, to go together and on same column, as 1. and 2. register is gone together different lines, 3., 4., 5. and 6. register different rows, different lines, 7., 8. and 9. register different rows same column, be arranged as the register time-delay characteristics drawn in fan-shaped distribution like this, also position changeable, repeat above operation.After placement-and-routing, obtain result by TimingAnalyzer time series analysis external member, this arrangement mode can measure the t of FPGA symmetry and peripheral registers position
covalue; If distribute according to Fig. 4, during layout, distributing from the position close to global clock HCLK, make 36 symmetrical, laterally zygomorphic register position of latch distribution, and respective 9 registers being distributed in A, B, C and D tetra-districts in different rows, different lines, go together and on same column, the t of the register position of the inside global clock HCLK periphery of FPGA structure can be tested
covalue.In this example, also the position of removable A, B, C and D tetra-district's triggers, surveys the time-delay characteristics in some limit ranges, but must ensure the t of next stage register input data
eXSUset up the retention time.
The content be not described in detail in instructions of the present invention belongs to the known technology of professional and technical personnel in the field.
Claims (6)
1. a FPGA placement-and-routing time-delay characteristics method of testing, is characterized in that, comprise,
S1, carries out structure analysis to FPGA;
S2, analyzes the result obtained according to step S1, design test module and corresponding testing software;
S3, to the test module that step S2 obtains, utilizes synthesis tool to carry out comprehensively;
S4, utilizes compilation tool to compile to the synthesis result that step S3 obtains;
S5, the basis of step S4 utilizes layout tool to retrain, and distributes test module according to FPGA integral layout characteristic, carries out distribution location to register;
S6, the basis of step S5 utilizes placement-and-routing's instrument carry out placement-and-routing, obtains each signal path time-delay characteristics by timing analysis tool.
2. FPGA placement-and-routing according to claim 1 time-delay characteristics method of testing, it is characterized in that, testing software VHDL language in step S2 carrys out code Design, comprise N number of same test module, test module is two-divider or counter, exports M the PIN pin being connected to FPGA by M register.
3. FPGA placement-and-routing according to claim 2 time-delay characteristics method of testing, is characterized in that, being constrained in step S5: distribute N number of test module, make its output to next stage register meet set up the retention time; By the position of one-level register, layout location is carried out to M signal, belongs to the register position of signal layout at same of same test module counter.
4. FPGA placement-and-routing according to claim 2 time-delay characteristics method of testing, is characterized in that, the synthesis tool in described step S2 is SynplifyPro, carries out comprehensive.
5. FPGA placement-and-routing according to claim 2 time-delay characteristics method of testing, it is characterized in that, the compilation tool in described step S3 is Complie, compiles.
6. FPGA placement-and-routing according to claim 2 time-delay characteristics method of testing, it is characterized in that, the placement-and-routing's instrument in described step S5 is ChipPlanner placement-and-routing, and timing analysis tool is TimingAnalyzer, carry out time series analysis, its signal path delay product can be checked.
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Cited By (6)
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| CN105842610A (en) * | 2016-03-31 | 2016-08-10 | 复旦大学 | FPGA circuit transmission delay rest system and method based on TDC |
| CN105868114A (en) * | 2016-03-31 | 2016-08-17 | 复旦大学 | FPGA software system and all module testing system and method thereof |
| CN107390522A (en) * | 2017-07-11 | 2017-11-24 | 中国科学院光电技术研究所 | A kind of error observation feed forward control method of view-based access control model tracking |
| CN108073734A (en) * | 2016-11-10 | 2018-05-25 | 龙芯中科技术有限公司 | Trigger autoplacement method and device |
| CN112530503A (en) * | 2020-12-16 | 2021-03-19 | 深圳市紫光同创电子有限公司 | Method for testing TCO (transparent conductive oxide) of FPGA (field programmable Gate array) register |
| CN118069447A (en) * | 2024-04-12 | 2024-05-24 | 济南智多晶微电子有限公司 | Automatic FPGA wiring resource testing method and device, electronic equipment and storage medium |
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Cited By (8)
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|---|---|---|---|---|
| CN105842610A (en) * | 2016-03-31 | 2016-08-10 | 复旦大学 | FPGA circuit transmission delay rest system and method based on TDC |
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| CN108073734A (en) * | 2016-11-10 | 2018-05-25 | 龙芯中科技术有限公司 | Trigger autoplacement method and device |
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| CN107390522A (en) * | 2017-07-11 | 2017-11-24 | 中国科学院光电技术研究所 | A kind of error observation feed forward control method of view-based access control model tracking |
| CN112530503A (en) * | 2020-12-16 | 2021-03-19 | 深圳市紫光同创电子有限公司 | Method for testing TCO (transparent conductive oxide) of FPGA (field programmable Gate array) register |
| CN118069447A (en) * | 2024-04-12 | 2024-05-24 | 济南智多晶微电子有限公司 | Automatic FPGA wiring resource testing method and device, electronic equipment and storage medium |
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