CN105117513B - A kind of FPGA placement-and-routings time-delay characteristics test method - Google Patents
A kind of FPGA placement-and-routings time-delay characteristics test method Download PDFInfo
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Abstract
The present invention is a kind of FPGA placement-and-routings time-delay characteristics test method, including, S1 carries out structural analysis to FPGA；S2, according to step S1 analyze as a result, design test module and corresponding test software；S3 integrates the test module that step S2 is obtained using synthesis tool；S4 is compiled the obtained synthesis results of step S3 using compilation tool；S5 is constrained on the basis of step S4 using layout tool, is allocated to test module according to FPGA integral layout characteristics, and positioning is allocated to register；S6 is laid out wiring on the basis of step S5 using placement-and-routing's tool, and each signal path time-delay characteristics are obtained by timing analysis tool.The present invention designs test module by analyzing FPGA structure characteristic, and carries out artificial placement-and-routing, is apparent to signal path time-delay characteristics.
Description
Technical field
The invention belongs to space flight optical remote sensor technical fields, are surveyed more particularly to a kind of FPGA placement-and-routings time-delay characteristics
Method for testing can be applied to CCD focal planes clock signal optimization design in space flight optical camera imaging circuit.
Background technology
As large scale integrated circuit develops, FPGA device is applied in the complicated system of high speed, circuit signal high speed, complete
Whole property depends not only upon device speed and also relies on flexible FPGA design.One complete FPGA design includes writing code, comprehensive
Close, emulation, compiling, placement-and-routing and programming test, placement-and-routing's stage is affected to the performance of circuit, be optimization design,
Put forward high performance key.
Difficult problem is adjusted for satellite-based CCD remote sensing camera CCD focal plane reading circuit time sequence precisions, new scheme changes
Previous present situation big using hardware circuit adjustment difficulty, debugging cycle length, it is proposed that using manual intervention placement-and-routing to inside
Register layout could be adjusted to meet output signal performance requirement.But this just needs qualitative to selected fpga chip, even fixed
Its distribution character that is delayed of amount analysis.The method of the present invention can test deposit inside FPGA by the test method of flexible design
Device time-delay characteristics, to determine manual intervention placement-and-routing trend.
Invention content
The technical problem to be solved in the present invention is：It cannot meet high-precision signal performance for current automatic placement and routing
Problem is right using a kind of FPGA placement-and-routings time-delay characteristics test method in order to meet new departure of manual intervention placement-and-routing
The delay distribution character of FPGA placement-and-routings is tested, to determine that manual layout connects up trend, to control, optimize output signal
Performance.
The technical scheme is that：A kind of FPGA placement-and-routings time-delay characteristics test method, including, S1, to FPGA into
Row structural analysis；S2, according to step S1 analyze as a result, design test module and corresponding test software；S3, to step
The test module that S2 is obtained, is integrated using synthesis tool；S4, the synthesis result that step S3 is obtained using compilation tool into
Row compiling；S5 is constrained on the basis of step S4 using layout tool, according to FPGA integral layout characteristics to test module
It is allocated, positioning is allocated to register；S6 is laid out cloth on the basis of step S5 using placement-and-routing's tool
Line obtains each signal path time-delay characteristics by timing analysis tool.
Further, the test software in step S2 with VHDL language come code Design, including N number of same test module,
Test module is two-divider or counter, and output is connected to the M PIN pin of FPGA by M register.
Further, being constrained in step S5：N number of test module is allocated, it is made to be output to next stage deposit
Device satisfaction establishes the retention time；Positioning is laid out by the position of level-one register to M signal, belongs to same test module
Register position of the signal layout of counter in same.
Further, the synthesis tool in step S2 is Synplify Pro, is integrated.
Further, the compilation tool in step S3 is Complie, is compiled.
Further, placement-and-routing's tool in step S5 is ChipPlanner placement-and-routings, and timing analysis tool is
Timing Analyzer carry out Time-Series analysis, can check its signal path delay product.
The advantages of the present invention over the prior art are that：The present invention is by analyzing FPGA structure characteristic design test mould
Block, and artificial placement-and-routing is carried out, signal path time-delay characteristics are apparent to, including critical registers establish the retention time
tEXSU, I/O pins output tcoDistribution value characteristic etc..In FPGA design, compared with traditional automatic placement and routing, introduce artificial dry
Pre-layout connects up, and has following advantage：Controllable critical registers establish retention time tEXSU；So that additional circuit need not be increased
The deflection i.e. t that can be easily controlled between output signalcoValue, control accuracy is up to ps grades；Reliability, safety higher.
Description of the drawings
Fig. 1 is the flow chart of test method of the present invention；
Fig. 2 is test method test software internal logic structure figure of the present invention；
Fig. 3 is one figure of test method internal register of the present invention placement-and-routing mode；
Fig. 4 is two figure of test method internal register of the present invention placement-and-routing mode.
Specific implementation mode
The FPGA placement-and-routings time-delay characteristics test method of the present invention, its step are as follows：
(1) FPGA structure is analyzed, and analyzes its feature, including its scale, clock sources, logical resource and I/O pins etc.；
(2) by step (1) analysis obtain as a result, being set using EDA (Electronic Design Automatic) tool
Count corresponding test software：N number of same test module, each test module are output to the M pipe of FPGA by M register
Foot；
(3) test software obtained to step (2), is integrated using EDA synthesis tools；
(4) step (3) synthesis result is compiled using EDA compilation tools；
(5) it is constrained using EDA layout tools on the basis of step (4), according to FPGA integral layout characteristics to N number of
Test module is allocated, and positioning is allocated to M × N number of register；
(6) wiring is laid out by eda tool on the basis of step (5), each signal road can be obtained by Time-Series analysis device
Diameter time-delay characteristics, including critical registers establish retention time tEXSU, I/O pins output tcoDistribution value characteristic.
Test software in the step (2), with VHDL language come code Design, including N number of same test module, test
Module can be two-divider or counter, and output is connected to the M PIN pin of FPGA by M register.
Being constrained in the step (5)：N number of test module is allocated, balances FPGA resource as possible, makes its output
Meet t to next stage registerEXSUKept for settling time；Positioning is laid out by the position of level-one register to M signal,
Belong to register position of the signal layout in same of same test module counter.
EDA synthesis tools in the step (2) are Synplify Pro, are integrated.
EDA compilation tools in the step (3) are Complie, are compiled.
EDA placement-and-routings tool in the step (5) is ChipPlanner placement-and-routings, and timing analysis tool is
Timing Analyzer carry out Time-Series analysis, can check its signal path delay product.(Synplify Pro are business tool
Software, Complie, ChipPlanner are libero IDE Platinum software tools, belong to public technology neck
Domain.)
One embodiment of the present of invention is：FPGA selects certain company's chip, developing instrument selection to correspond to eda tool platform,
Synthesis tool selects Synplify Pro, is designed using VHDL language.
First, for certain company's fpga chip, recognize that the chip structure is formed by two kinds of logic modules by Datasheet
Composition：Block of registers and combined logic block；Clock sources have 1 external hardware clock, 4 global clocks；Chip-scale is 7.2
Wan Men；I/O PIN pins are more than 160.Therefore consider equilibrium of stock, design four test modules, 80 PIN pins output letters
Number.In practical applications, test module complexity and number of pins energy balanced design, not design excessively numerous and jumbled simultaneously, can influence
Placement-and-routing tests effect.
Under eda tool platform, it is identical to design four test modules, for convenience of understanding, so design simple test mould
Block is two-divider, is critical registers, its position determines that t is established in the holding of next stage registerEXSU.Four two-dividers are defeated
Go out four signals, respectively separate 9 by four signals is output to PIN pins by level-one register, this grade of register determines output
The t of signalco, constrained in VHDL codes so that signal when comprehensive it is not optimised fall.
It is integrated in Synplify Pro, Compile external members are compiled in eda tool, ChipPlanner external members
It is allocated constraint, four two-divider positions are such as Fig. 3, shown in Fig. 4, while 9 registers that each two-divider is connected
Position be distributed in the predetermined direction come, for meet keep settling time, frequency divider (i.e. register) position with connect down
Level-one register position distance not distribute too far, be laid out wiring after the completion.Timing Analyzer external members are opened to carry out
Time-Series analysis, can view each signal path after placement-and-routing as a result, including tEXSU, tcoValue etc..Afterbody in this
When register is laid out, several situations is divided to consider to carry out as possible：So that register is symmetrical and symmetrical above and below to examine or check its device
Be delayed symmetry；Row different around two divided-frequency register and identical row are distributed in, to determine that different lines or same column are delayed
Characteristic；It is distributed in row different around two parts of frequency registers and mutually goes together, to determine the time-delay characteristics do not gone together or mutually gone together；Weight
It is multiple to carry out above several distributed layouts, until understanding entire device layout situation.
Further explanation is laid out to the distribution of the present invention to design a simple test software with one embodiment below.Tool
Body is implemented as follows：
In this example, four test modules are designed, each test module structure a d type flip flop as shown in Fig. 2, be made of
One two-divider is output to external PIN by level-one latch by reversely separating 9 signals after master clock two divided-frequency and manages
Foot.In placement-and-routing, four triggers are separately dispensed into four areas A, B, C and D, identical by the ends a trigger Q extraction 9
By being drawn out to PIN pins after level-one latch (1~9) after two reversers, the position of reverser can influence signal
tEXSU, 36 latch positions as shown in figure 3, layout when, be allocated in the position closer from PIN pins so that 36 lock
Storage is distributed register position symmetrical, symmetrical above and below, and respective 9 registers for being distributed in tetra- areas A, B, C and D exist
Do not go together, on different lines, colleague and same column, 1. and 2. such as register is gone together different lines, 3., 4., 5. and 6. register do not go together,
Different lines, 7., 8. and 9. register do not go together same column, be arranged as obtaining the register time-delay characteristics in fan-shaped distribution in this way,
Position changeable repeats above operation.After placement-and-routing, obtained as a result, this by Timing Analyzer Time-Series analysis external members
Arrangement mode can measure the t of FPGA symmetry and peripheral registers positioncoValue；If being allocated according to Fig. 4, when layout,
It is allocated in the position closer from global clock HCLK so that 36 latch are distributed deposit symmetrical, symmetrical above and below
Device position, and be distributed in respective 9 registers in tetra- areas A, B, C and D do not go together, different lines, go together and same column on, can survey
Try the t of the register position on the inside peripheries global clock HCLK of FPGA structurecoValue.In this example, also removable A, B, C and D
The time-delay characteristics in some limit ranges are surveyed in the position of four area's triggers, but must assure that next stage register input data
TEXSUEstablish the retention time.
The content that description in the present invention is not described in detail belongs to the known technology of professional and technical personnel in the field.
Claims (6)
1. a kind of FPGA placement-and-routings time-delay characteristics test method, which is characterized in that including,
S1 carries out structural analysis, including the scale of FPGA, clock sources, logical resource and I/O pins to FPGA；
S2, according to step S1 analyze as a result, design test module and corresponding test software；The test module includes
N number of same test module, each test module are output to the M pin of FPGA by M register；Test module is two divided-frequency
Device or counter, output are connected to the M PIN pin of FPGA by M register；
S3 integrates the test software that step S2 is obtained using synthesis tool；
S4 is compiled the obtained synthesis results of step S3 using compilation tool；
S5 is constrained on the basis of step S4 using layout tool, according to FPGA integral layouts characteristic to test module into
Row distribution, positioning is allocated to register；Register distributes the principle positioned：Afterbody register is symmetrical simultaneously
It is symmetrical above and below；Row different around two divided-frequency or counter register and identical row are distributed in, to determine different lines or phase
Same column time-delay characteristics；Be distributed in row different around two divided-frequency or counter register and mutually go together, with determine do not go together or
The mutually time-delay characteristics of colleague；
S6, wiring is laid out on the basis of step S5 using placement-and-routing's tool, and each signal is obtained by timing analysis tool
Path delay characteristic.
2. FPGA placement-and-routings time-delay characteristics test method according to claim 1, which is characterized in that the survey in step S2
Software is tried with VHDL language come code Design.
3. FPGA placement-and-routings time-delay characteristics test method according to claim 2, which is characterized in that the pact in step S5
Shu Wei：N number of test module is allocated, so that it is output to next stage register satisfaction and establishes the retention time；It is logical to M signal
The position for crossing level-one register is laid out positioning, belongs to deposit of the signal layout in same of same test module counter
Device position.
4. FPGA placement-and-routings time-delay characteristics test method according to claim 2, which is characterized in that in the step S3
Synthesis tool be Synplify Pro, integrated.
5. FPGA placement-and-routings time-delay characteristics test method according to claim 2, which is characterized in that in the step S4
Compilation tool be Complie, be compiled.
6. FPGA placement-and-routings time-delay characteristics test method according to claim 2, which is characterized in that in the step S6
Placement-and-routing's tool be ChipPlanner placement-and-routings, timing analysis tool is Timing Analyzer, carries out sequential point
Analysis, can check its signal path delay product.
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| CN105868114B (en) * | 2016-03-31 | 2019-04-05 | 复旦大学 | FPGA software systems and its each module test system and method |
| CN105842610A (en) * | 2016-03-31 | 2016-08-10 | 复旦大学 | FPGA circuit transmission delay rest system and method based on TDC |
| CN108073734B (en) * | 2016-11-10 | 2021-08-17 | 龙芯中科技术股份有限公司 | Automatic layout method and device for trigger |
| CN107390522A (en) * | 2017-07-11 | 2017-11-24 | 中国科学院光电技术研究所 | Error observation feedforward control method based on visual tracking |
| CN112530503A (en) * | 2020-12-16 | 2021-03-19 | 深圳市紫光同创电子有限公司 | Method for testing TCO (transparent conductive oxide) of FPGA (field programmable Gate array) register |
| CN118069447B (en) * | 2024-04-12 | 2024-07-16 | 济南智多晶微电子有限公司 | Automatic FPGA wiring resource testing method and device, electronic equipment and storage medium |
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