CN105100548A - Image processing enhancement circuit for medical endoscope - Google Patents
Image processing enhancement circuit for medical endoscope Download PDFInfo
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- CN105100548A CN105100548A CN201510385952.4A CN201510385952A CN105100548A CN 105100548 A CN105100548 A CN 105100548A CN 201510385952 A CN201510385952 A CN 201510385952A CN 105100548 A CN105100548 A CN 105100548A
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Abstract
The invention relates to an image processing enhancement circuit for a medical endoscope. The image processing enhancement circuit comprises an image processing chip, a signal converting chip and an image enhancement chip, wherein the signal converting chip comprises a first signal converting chip and a second signal converting chip; the first signal converting chip is used for converting a bt1120 signal into a lvds signal; the second signal conversion chip is used for converting the lvds signal into the bt1120 signal; the image processing chip sends a processed image signal to the first signal converting chip, and the first signal converting chip sends the processed image signal to the second signal converting chip; and the second signal converting chip converts the signal and sends the same to the image enhancement chip. Compared to the prior art, according to the image processing enhancement circuit provided by the invention, one image processing chip is added on a lens part to process collected images, an one image enhancement chip is added on a mainframe background to carry out two-level image enhancement, so as to make the finally output images be more clearer.
Description
Technical field
The present invention relates to a kind of image processing circuit, particularly a kind of for the image procossing intensifier circuit for medical endoscope.
Background technology
Endoscope is a kind of conventional medicine equipment, is become by flexible part, light source and an arrangement of mirrors head group.Through the natural hole of human body, or the minimal incision * that underwent operative is done enters in human body, during use, endoscope is imported the organ of preliminary examination, directly can spy on the change of relevant portion.
Wherein, the quality of picture quality directly affects the result of use of endoscope.Existing general use fujinon electronic video endoscope is observed, and the treatment system image after observation being sent to outside connection carries out image procossing.But, during owing to carrying out IMAQ in human body, can due to a variety of causes of inside of human body, and cause occurring noise jamming, brightness cannot regulate or cause due to the color of light image to occur aberration automatically, so cause in the image procossing in later stage, being difficult to the image of rediscover, making doctor be difficult to identification when observing.
Summary of the invention
The invention reside in the shortcoming and deficiency that overcome prior art, provide a kind of for the image procossing intensifier circuit for medical endoscope.
The present invention is achieved through the following technical solutions: a kind of image procossing intensifier circuit for medical endoscope, comprises picture processing chip, signal conversion chip and image enhaucament chip; Described signal conversion chip comprises the first signal conversion chip and secondary signal conversion chip; Described first signal conversion chip is used for bt1120 signal to be converted to lvds signal; Described secondary signal conversion chip is used for lvds signal to be converted to bt1120 signal; Picture signal after process is sent to the first signal conversion chip by described picture processing chip, and is sent to secondary signal conversion chip by this first signal conversion chip; Described secondary signal conversion chip is sent to image enhaucament chip after being changed by signal.
Compared to prior art, the present invention, by increasing by a picture processing chip in camera lens part, processes the image gathered, main frame backstage increases an image enhaucament chip, carries out level image enhancing, makes the last image exported more clear.
First, in picture processing chip, be divided into multiple functional module, difference also by each functional module independence co-ordination, can realize low-power consumption, low-light (level), and can be the picture high definition more exported.Meanwhile, a white balance permanent circuit being set in this image processor further, for being fixed by this white balance parameter, without the need to operationally carrying out the adjustment of white balance, thus preventing the phenomenon of aberration interference.
Then, in image enhaucament chip, be also divided into multiple functional module, difference also by each functional module independence co-ordination, can realize the enhancing process to image.Meanwhile, an image border intensifier circuit is set in this image intensifier further, in order to strengthen the definition of image border.
In addition, in order to improve the stability of Signal transmissions, the present invention is by being first converted to lvds signal by bt1120 signal, thus stable transmission, and there is low noise ability.Then, be bt1120 signal by lvds signals revivification, thus ensure that the quality of the picture of follow-up play.
As a further improvement on the present invention, described picture processing chip comprises: data sink, master controller, image processor, data logger;
---described data sink, it is for receiving outside view data;
---described master controller, it is for receiving outside triggering signal, and the operating state of the described data sink of corresponding control, image processor and data logger;
---described image processor, it is for processing image; Described image processor comprises a white balance permanent circuit, and it, for according to the parameter preset, carries out the fixed adjustment of white balance;
---described data logger, it is for exporting the view data after process;
Described first signal conversion chip comprises: controller, data reader, signal format converter, serializer, data logger;
---described controller, it is for receiving outside triggering signal, and the work of control data reader, signal format converter, serializer and data logger;
---described data reader, it for receiving outside bt1120 signal transmission, and is sent to signal format converter;
---described signal format converter, it for bt1120 vision signal being converted to the vision signal of lvds, and is sent to serializer;
---described serializer, it for parallel data is converted to serial data, and is sent to data logger;
---described data logger, for exporting lvds signal data to secondary signal conversion chip;
Described secondary signal conversion chip comprises: controller, data reader, signal format converter, deserializer, data logger;
---described controller, it is for receiving outside triggering signal, and the work of control data reader, signal format converter, deserializer and data logger;
---described data reader, it for the lvds video transfer signal of the first signal conversion chip, and is sent to signal format converter;
---described signal format converter, it for lvds vision signal being converted to the vision signal of bt1120, and is sent to deserializer;
---described deserializer, it for serial data is converted to parallel data, and is sent to data logger;
---described data logger, for bt1120 video signal data is exported;
Described image enhaucament chip comprises: data sink, controller, static memory, image intensifier, data logger and clock generator;
---described data sink, it is for receiving viewdata signal, and is sent to this image intensifier;
---described controller, it is for receiving outer triggering signal, and the operating state of corresponding control data receiver, image enhaucament itself and data logger;
---described static memory, it is for the driving data of memory image booster, to drive the work of this image intensifier;
---described image intensifier, it comprises an image border intensifier circuit; Described image border intensifier circuit is for strengthening the definition of image border;
---described data logger, it for receiving the view data after image intensifier process, and carries out data output;
---described clock generator, it is for being image enhaucament chip clocking.
As a further improvement on the present invention, described picture processing chip also comprises a frequency multiplier, and its frequency for the triggering signal inputted outside carries out doubling process, then is sent to master controller;
Described first signal conversion chip also comprises a phase-locked loop, is connected respectively, for unified integration clock signal with signal format converter and serializer;
Described secondary signal conversion chip also comprises a phase-locked loop, is connected respectively with signal format converter and serializer, for unified integration clock signal;
Described image enhaucament chip also comprises a de-noising processor; The viewdata signal that described data sink receives, is sent to de-noising processor and carries out noise reduction process, then be forwarded to image intensifier.
As a further improvement on the present invention, described image processor also comprises an exposure gain circuit, for increasing exposure gain size;
Described first signal conversion chip also comprises a clock data restorer, and it is connected with data reader, for recovering data from the distortion and noise of transmission channel;
Described secondary signal conversion chip also comprises a clock data restorer, and it is connected with data reader, for recovering data from the distortion and noise of transmission channel;
Described image enhaucament chip also comprises a dynamic memory; View data after described de-noising processor process, is first sent to dynamic memory and stores, then be forwarded to image intensifier.
As a further improvement on the present invention, described image processor also comprises an optical detection circuit and flash detection circuit, its brightness for detection image and flashing state, and result of detection is sent to exposure gain circuit;
Described image enhaucament chip also comprises a pixel self adaptation proofreading equipment; View data after process is first sent to described pixel self adaptation proofreading equipment by described image intensifier, carries out pixel and adapts to check and correction, then be sent to data logger by this pixel self adaptation proofreading equipment.
As a further improvement on the present invention, described image enhaucament chip also comprises a vision signal multiplier and a storage signal multiplier; Described clock generator, the clock signal of generation is sent to respectively vision signal multiplier and storage signal multiplier, and by this vision signal multiplier, clock signal is sent to data sink, by this storage signal multiplier, clock signal is sent to dynamic memory and static memory.
As a further improvement on the present invention, described picture processing chip outside is provided with: for receive supply power voltage power port, for receive picture signal receiver port, for outputting video signal video signal port, for export row field signal row field signal port, for receive external timing signal clock signal port, store the data receiver port and of data for receiving the PORT COM of external communication order for receiving;
Described first signal conversion chip outside is provided with: described center processing chip exterior is provided with: for receive supply power voltage power port, for receive bt1120 vision signal receiver port, for exporting the video signal port of lvds vision signal and the row field signal port for exporting row field signal;
Described secondary signal conversion chip outside is provided with: described center processing chip exterior is provided with: for receive supply power voltage power port, for receiving the receiver port of lvds vision signal and the video signal port for exporting bt1120 vision signal;
Described image enhaucament chip exterior is provided with: for receive supply power voltage power port, for receive picture signal receiver port, for outputting video signal video signal port, for export row field signal row field signal port, for receiving the clock signal port of external timing signal and storing the data receiver port of data for receiving.
As a further improvement on the present invention, the power port of described picture processing chip is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity;
The power port of described picture processing chip is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.
As a further improvement on the present invention, the external clock circuit of clock signal port of described picture processing chip, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity;
The external clock circuit of clock signal port of described image enhaucament chip, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity.
As a further improvement on the present invention, the data receiver port of described picture processing chip is circumscribed with a memory circuitry, and it comprises a memory, is connected to the filter circuit of the voltage port of this memory, and is connected to the resistance of output port of this memory.
In order to understand better and implement, describe the present invention in detail below in conjunction with accompanying drawing.
Accompanying drawing explanation
Fig. 1 is chip connection diagram of the present invention.
Fig. 2 is the internal module connection diagram of picture processing chip.
Fig. 3 is the circuit module schematic diagram of the image processor of picture processing chip.
Fig. 4 is the voltage segment circuit diagram of picture processing chip.
Fig. 5 is the outside port circuit diagram of picture processing chip.
Fig. 6 is the circuit diagram of the filter circuit of the 3.3V voltage of picture processing chip.
Fig. 7 is the circuit diagram of the filter circuit of the 1.8V voltage of picture processing chip.
Fig. 8 is the circuit diagram of the filter circuit of the 1.2V voltage of picture processing chip.
Fig. 9 is the partial enlarged drawing of the receiver port of picture processing chip.
Figure 10 is the partial enlarged drawing of the video signal port of picture processing chip.
Figure 11 is the partial enlarged drawing of the row field signal port of picture processing chip.
Figure 12 is the schematic diagram of the clock circuit of picture processing chip.
Figure 13 is the schematic diagram of the memory circuit of picture processing chip.
Figure 14 is the partial enlarged drawing of the PORT COM of picture processing chip.
Figure 15 is the internal components connection diagram of the first signal conversion chip.
Figure 16 is the internal module connection diagram of secondary signal conversion chip.
Figure 17 is the outside port connection diagram of the first signal conversion chip.
Figure 18 is the close-up schematic view of the power port of the first signal conversion chip.
Figure 19 is the partial enlarged drawing of the receiver port of the first signal conversion chip.
Figure 20 is the partial enlarged drawing of the video signal port of the first signal conversion chip.
Figure 21 is the partial enlarged drawing of the row field signal port of the first signal conversion chip.
Figure 22 is the outside connecting circuit figure of secondary signal conversion chip.
Figure 23 is the partial enlarged drawing of the receiver port of secondary signal conversion chip.
Figure 24 is the partial enlarged drawing of the video signal port of secondary signal conversion chip.
Figure 25 is the partial enlarged drawing of the row field signal port of secondary signal conversion chip.
Figure 26 is the internal module connection diagram of image enhaucament chip.
Figure 27 is the outside connecting circuit figure of Part I of image enhaucament chip.
Figure 28 is the outside connecting circuit figure of Part II of image enhaucament chip.
Figure 29 is the circuit diagram of the filter circuit of pressure-stabilizing of the 3.3V voltage of image enhaucament chip.
Figure 30 is the power-switching circuit figure that the 3.3V of image enhaucament chip is converted to 1.8V.
Figure 31 is the power-switching circuit figure that the 3.3V of image enhaucament chip is converted to 1.2V.
Figure 32 is the partial enlarged drawing of the receiver port of image enhaucament chip.
Figure 33 a is the partial enlarged drawing of the video signal port Part I of image enhaucament chip.
Figure 33 b is the partial enlarged drawing of the video signal port Part II of image enhaucament chip.
Figure 34 is the circuit diagram of the clock circuit of image enhaucament chip.
Figure 35 is the partial enlarged drawing of the row field signal port of image enhaucament chip.
Embodiment
Refer to Fig. 1, it is chip connection diagram of the present invention.The invention provides a kind of image procossing intensifier circuit for medical endoscope, comprise picture processing chip 10, signal conversion chip 20 and image enhaucament chip 30; Described signal conversion chip 20 comprises the first signal conversion chip 21 and secondary signal conversion chip 22; Described first signal conversion chip 21 is for being converted to lvds signal by bt1120 signal; Described secondary signal conversion chip 22 is for being converted to bt1120 signal by lvds signal; Picture signal after process is sent to the first signal conversion chip 21 by described picture processing chip 10, and is sent to secondary signal conversion chip 22 by this first signal conversion chip 21; Described secondary signal conversion chip 22 is sent to image enhaucament chip 30 after being changed by signal.
Refer to Fig. 2, it is the internal module connection diagram of picture processing chip.Described picture processing chip comprises: data sink 11, master controller 12, image processor 13, data logger 14.
Described data sink 11, it is for receiving outside view data;
Described master controller 12, it is for receiving outside triggering signal, and the operating state of the described data sink of corresponding control, image processor and data logger;
Described image processor 13, it is for processing image.
Described data logger 14, it is for exporting the view data after process.
Further, described picture processing chip also comprises a frequency multiplier 15, and its frequency for the triggering signal inputted outside carries out doubling process, then is sent to master controller 12.
Refer to Fig. 3, it is the circuit module schematic diagram of the image processor of picture processing chip.Concrete, described image processor 13 comprises a Lens Shading Compensation circuit 131, optical detection circuit 132, flash detection circuit 133, exposure gain circuit 134 and white balance permanent circuit 135.
Described Lens Shading Compensation circuit 131, it compensates process for the shade produced by camera lens.
Described optical detection circuit 132 and flash detection circuit 133, its brightness for detection image and flashing state, and result of detection is sent to exposure gain circuit.
Described exposure gain circuit 134, for increasing exposure gain size.
Described white balance permanent circuit 135, it, for according to the parameter preset, carries out the fixed adjustment of white balance.
Please refer to Fig. 4 and Fig. 5, it is respectively voltage segment and other outside port circuit diagrams of picture processing chip.In addition, in order to the application in order to adapt to this picture processing chip, be provided with in described picture processing chip outside further: for receive supply power voltage power port 101, for receive picture signal receiver port 102, for outputting video signal video signal port 103, for export row field signal row field signal port one 04, for receive external timing signal clock signal port 105, for receive store data data receiver port 106 and one for receiving the PORT COM 107 of external communication order.
Refer to Fig. 6-8, it is respectively the circuit diagram of 3.3V, 1.8V and 1.2V of picture processing chip.Further, described power port 101 is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.Concrete, the external voltage of described picture processing chip comprises: 3.3V, 1.8V and 1.2V tri-kinds.Wherein, 3.3V voltage place in circuit comprises 2 electric capacity, and 1.8V voltage place in circuit comprises 5 electric capacity, and the voltage place in circuit of 1.2V comprises 6 electric capacity, to filter the interference signal of different frequency respectively.
Refer to Fig. 9, it is the partial enlarged drawing of the receiver port of picture processing chip.Described receiver port 102 comprises 8 pins, for receiving outside video signal.
Refer to Figure 10, it is the partial enlarged drawing of the video signal port of picture processing chip.Described video signal port 103 comprises the vision signal of two groups of different-formats, carries out doubleway output, plays in real time respectively to facilitate and records.
Refer to Figure 11, it is the partial enlarged drawing of the row field signal port of picture processing chip.Described row field signal port one 04 is for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.
Refer to Figure 12, it is the schematic diagram of the clock circuit of picture processing chip.The external clock circuit of described clock signal port 105, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity.
Refer to Figure 13, it is the schematic diagram of the memory circuit of picture processing chip.Further, described data receiver port 106 is circumscribed with a memory circuitry, and it comprises a memory, is connected to the filter circuit of the voltage port of this memory, and is connected to the resistance of output port of this memory.
Refer to Figure 14, it is the partial enlarged drawing of the PORT COM of picture processing chip.Described PORT COM 107, for receiving the trigger command of external transmission, carries out work with what trigger this picture processing chip.
Refer to Figure 15, it is the internal components connection diagram of the first signal conversion chip.Described first signal conversion chip 21 comprises: controller 211, data reader 212, signal format converter 213, serializer 214, data logger 215, phase-locked loop 216 and clock data restorer 217;
Described controller 211, it is for receiving outside triggering signal, and the work of control data reader 212, signal format converter 213, serializer 214 and data logger 215;
Described data reader 212, it for receiving outside bt1120 signal transmission, and is sent to signal format converter;
Described signal format converter 213, it for bt1120 vision signal being converted to the vision signal of lvds, and is sent to serializer;
Described serializer 214, it for parallel data is converted to serial data, and is sent to data logger;
Described data logger 215, for exporting lvds signal data to secondary signal conversion chip.
Described phase-locked loop 216, is connected with signal format converter and serializer respectively, for unified integration clock signal.
Described clock data restorer 217, it is connected with data reader, for recovering data from the distortion and noise of transmission channel.
Refer to Figure 16, it is the internal module connection diagram of secondary signal conversion chip.Described secondary signal conversion chip 22 comprises: controller 221, data reader 222, signal format converter 223, deserializer 224, data logger 225, phase-locked loop 226 and clock data restorer 227;
Described controller 221, it is for receiving outside triggering signal, and the work of control data reader 222, signal format converter 223, deserializer 224 and data logger 225;
Described data reader 222, it for the lvds video transfer signal of the first signal conversion chip, and is sent to signal format converter;
Described signal format converter 223, it for lvds vision signal being converted to the vision signal of bt1120, and is sent to deserializer 224;
Described deserializer 224, it for serial data is converted to parallel data, and is sent to data logger;
Described data logger 225, for exporting bt1120 video signal data.
Described phase-locked loop 226, is connected with signal format converter and deserializer respectively, for unified integration clock signal.
Described clock data restorer 227, it is connected with data reader 222, for recovering data from the distortion and noise of transmission channel.
Refer to Figure 17, it is the outside port connection diagram of the first signal conversion chip.Described first signal conversion chip outside is provided with: described center processing chip exterior is provided with: for receive supply power voltage power port 2101, for receive bt1120 vision signal receiver port 2102, for exporting the video signal port 2103 of lvds vision signal and the row field signal port 2104 for exporting row field signal.
Please refer to Figure 18, it is the close-up schematic view of the power port of the first signal conversion chip.Described power port 2101 place is circumscribed with the electric capacity for filtering alternating current.
Refer to Figure 19, it is the partial enlarged drawing of the receiver port of the first signal conversion chip.Described receiver port 2102, it is connected with described data reader 21; Concrete, this receiver port includes 20 pins, for receiving the vision signal of outside bt1120.
Refer to Figure 20, it is the partial enlarged drawing of the video signal port of the first signal conversion chip.Described video signal port 2103 includes 4 output pins, and for exporting lvds vision signal, and this video signal port is connected with this data logger.
Refer to Figure 21, it is the partial enlarged drawing of the row field signal port of the first signal conversion chip.Described row field signal port 2104 includes a line signal output pin and a field signal output pin; Described row field signal port 2104 is for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.
Refer to Figure 22, it is the outside connecting circuit figure of secondary signal conversion chip.Described secondary signal conversion chip outside is provided with: for receive lvds vision signal receiver port 2201, for exporting video signal port 2202 and the row field signal port 2203 of bt1120 vision signal.
Refer to Figure 23, it is the partial enlarged drawing of the receiver port of secondary signal conversion chip.Described receiver port 2201, it is connected with described data reader 221; Concrete, this receiver port includes 4 pins, for receiving the lvds vision signal that the first signal conversion chip exports.
Refer to Figure 24, it is the partial enlarged drawing of the video signal port of secondary signal conversion chip.Described video signal port 2202 includes 20 output pins, and for exporting bt1120 vision signal, and this video signal port is connected with this data logger.
Refer to Figure 25, it is the partial enlarged drawing of the row field signal port of secondary signal conversion chip.Described row field signal port 2203 includes a line signal output pin and a field signal output pin; Described row field signal port 2104 is for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.
Refer to Figure 26, it is the internal module connection diagram of image enhaucament chip.Described image enhaucament chip comprises: data sink 31, de-noising processor 32, dynamic memory 33, image intensifier 34, pixel self adaptation proofreading equipment 35, data logger 36, static memory 37, controller 38, vision signal multiplier 39, storage signal multiplier 310, clock generator 311.
Described data sink 31, it is for receiving viewdata signal, and is sent to de-noising processor 32;
The viewdata signal that described data sink 31 receives, is sent to de-noising processor 32 and carries out noise reduction process, then be forwarded to dynamic memory 33.
After the view data of described dynamic memory 33 after receiving de-noising processor 22 process, then be forwarded to image intensifier 34.
Described image intensifier 34, it comprises an image border intensifier circuit; Described image border intensifier circuit is for strengthening the definition of image border.Further, the view data after process is first sent to described pixel self adaptation proofreading equipment 35 by described image intensifier, carries out pixel and adapts to check and correction, then be sent to data logger 36 by this pixel self adaptation proofreading equipment 35.
Described data logger 36, it for receiving the view data after image intensifier process, and carries out data output;
Described static memory 37, it is for the driving data of memory image booster, to drive the work of this image intensifier;
Described controller 38, it is for receiving outer triggering signal, and the operating state of corresponding control data receiver, image enhaucament itself and data logger;
Described clock generator 311, it is for being image enhaucament chip clocking.Further, described clock generator, the clock signal of generation is sent to respectively vision signal multiplier 29 and storage signal multiplier 310, and by this vision signal multiplier 39, clock signal is sent to data sink, by this storage signal multiplier 310, clock signal is sent to dynamic memory and static memory.
Please refer to Figure 27 and Figure 28, it is respectively the outside connecting circuit figure of image enhaucament chip.
Further, described image enhaucament chip exterior is provided with: for receive supply power voltage power port, for receive picture signal receiver port 301, for outputting video signal video signal port 302, for receive external timing signal clock signal port 303, for exporting the row field signal port 304 of row field signal.
Concrete, in the present embodiment, the external voltage of described power port comprises 3.3V, 1.8V and 1.2V tri-kinds of voltages.Refer to Figure 29, it is the circuit diagram of the filter circuit of pressure-stabilizing of 3.3V voltage.Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.
Refer to Figure 30-31, it is respectively the change-over circuit figure that power-switching circuit figure and 3.3V that 3.3V is converted to 1.8V is converted to 1.2V.In the present embodiment, by a power-switching circuit, the voltage of 3.3V is converted to respectively the voltage of 1.8V and 1.2V.Concrete, described power-switching circuit comprises a power conversion chip; The voltage of the input access 3.3V of described power conversion chip, output exports the voltage of 1.8V and 1.2V respectively, to power to image enhaucament chip.
Refer to Figure 32, it is the partial enlarged drawing of the receiver port of image enhaucament chip.Described receiver port 301 comprises 20 signal pins, is connected with the data sink 31 of inside, for receiving the picture signal of input.
Refer to Figure 33 a and 33b, it is respectively the Part I of the video signal port of image enhaucament chip and the partial enlarged drawing of Part II.Described video signal port 302 comprises 20 signal pins, and it is connected, for output image signal with inner data logger 36.
Refer to Figure 34, it is the circuit diagram of the clock circuit of image enhaucament chip.Further, the external clock circuit of described clock signal port 303, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity.
Refer to Figure 35, it is the partial enlarged drawing of the row field signal port of image enhaucament chip.Described row field signal port 304 comprises a row signal pins and a field signal pin.Described row field signal port 304 is for controlling frequency and the order of video frequency output.Such as: the display frequency of vision signal on screen and DISPLAY ORDER can be controlled, can be from every line output under upper, also can be export from left to right.
Below the course of work of image processing circuit of the present invention is described:
S1: will to this picture processing chip, the first signal conversion chip, secondary signal conversion chip, and the outside port of image enhaucament chip carries out circuit access according to above-mentioned requirement;
S2: when picture processing chip is energized, first carries out multiplication by this frequency multiplier by input voltage frequency and regulates, to adapt to current operating frequency;
S3: first receive outside view data by the data sink 11 of picture processing chip 10;
S4: described image processor 13 pairs of images process.Specifically respectively by described Lens Shading Compensation circuit 131, the shade that camera lens produces is compensated process; By brightness and the flashing state of described optical detection circuit 132 and flash detection circuit 133 detection image, and result of detection is sent to exposure gain circuit; Then exposure gain size is increased by described exposure gain circuit 134.Last again by described white balance permanent circuit 35 according to default parameter, carry out the fixed adjustment of white balance.
S5: the view data after process is carried out output first signal conversion chip by described data logger 14.
S6: the data reader 212 of described first signal conversion chip receives the bt1120 signal transmission of picture processing chip output, and is sent to signal format converter;
S7: bt1120 vision signal is converted to the vision signal of lvds by described signal format converter 213, and is sent to serializer 214;
S8: parallel data is converted to serial data by described serializer 214, and is sent to data logger;
S9: described data logger 215, for exporting lvds signal data to secondary signal conversion chip.
S10: by the lvds video transfer signal of the data reader 222 in secondary signal conversion chip by the first signal conversion chip, and be sent to signal format converter;
S11: lvds vision signal is converted to the vision signal of bt1120 by described signal format converter 223, and is sent to deserializer;
S12: serial data is converted to parallel data by described deserializer 224, and is sent to data logger;
S13: described data logger 225 exports bt1120 video signal data to image enhaucament chip.
S14: receive outside view data by the data sink 31 of image enhaucament chip;
S15: described data sink 31, receives viewdata signal, and is sent to de-noising processor 32;
S16: described de-noising processor 32 carries out noise reduction process, then is forwarded to dynamic memory 33.
S17: after the view data of described dynamic memory 33 after receiving de-noising processor 32 process, then be forwarded to image intensifier 34.
S18: described image intensifier 34, it comprises an image border intensifier circuit; Described image border intensifier circuit strengthens the definition of image border.View data after process is first sent to described pixel self adaptation proofreading equipment 35 by described image intensifier.
S19: described pixel self adaptation proofreading equipment 35 carries out pixel and adapts to check and correction, then is sent to data logger 36.
S20: the view data after process exports by described data logger 36.
Compared to prior art, the present invention, by increasing by a picture processing chip in camera lens part, processes the image gathered, main frame backstage increases an image enhaucament chip, carries out level image enhancing, makes the last image exported more clear.
First, in picture processing chip, be divided into multiple functional module, difference also by each functional module independence co-ordination, can realize low-power consumption, low-light (level), and can be the picture high definition more exported.Meanwhile, a white balance permanent circuit being set in this image processor further, for being fixed by this white balance parameter, without the need to operationally carrying out the adjustment of white balance, thus preventing the phenomenon of aberration interference.
Then, in image enhaucament chip, be also divided into multiple functional module, difference also by each functional module independence co-ordination, can realize the enhancing process to image.Meanwhile, an image border intensifier circuit is set in this image intensifier further, in order to strengthen the definition of image border.
In addition, in order to improve the stability of Signal transmissions, the present invention is by being first converted to lvds signal by bt1120 signal, thus stable transmission, and there is low noise ability.Then, be bt1120 signal by lvds signals revivification, thus ensure that the quality of the picture of follow-up play.
The present invention is not limited to above-mentioned execution mode, if do not depart from the spirit and scope of the present invention to various change of the present invention or distortion, if these are changed and distortion belongs within claim of the present invention and equivalent technologies scope, then the present invention is also intended to comprise these changes and distortion.
Claims (10)
1. for an image procossing intensifier circuit for medical endoscope, it is characterized in that: comprise picture processing chip, signal conversion chip and image enhaucament chip; Described signal conversion chip comprises the first signal conversion chip and secondary signal conversion chip; Described first signal conversion chip is used for bt1120 signal to be converted to lvds signal; Described secondary signal conversion chip is used for lvds signal to be converted to bt1120 signal; Picture signal after process is sent to the first signal conversion chip by described picture processing chip, and is sent to secondary signal conversion chip by this first signal conversion chip; Described secondary signal conversion chip is sent to image enhaucament chip after being changed by signal.
2., according to claim 1 for the image procossing intensifier circuit of medical endoscope, it is characterized in that: described picture processing chip comprises: data sink, master controller, image processor, data logger;
---described data sink, it is for receiving outside view data;
---described master controller, it is for receiving outside triggering signal, and the operating state of the described data sink of corresponding control, image processor and data logger;
---described image processor, it is for processing image; Described image processor comprises a white balance permanent circuit, and it, for according to the parameter preset, carries out the fixed adjustment of white balance;
---described data logger, it is for exporting the view data after process;
Described first signal conversion chip comprises: controller, data reader, signal format converter, serializer, data logger;
---described controller, it is for receiving outside triggering signal, and the work of control data reader, signal format converter, serializer and data logger;
---described data reader, it for receiving outside bt1120 signal transmission, and is sent to signal format converter;
---described signal format converter, it for bt1120 vision signal being converted to the vision signal of lvds, and is sent to serializer;
---described serializer, it for parallel data is converted to serial data, and is sent to data logger;
---described data logger, for exporting lvds signal data to secondary signal conversion chip;
Described secondary signal conversion chip comprises: controller, data reader, signal format converter, deserializer, data logger;
---described controller, it is for receiving outside triggering signal, and the work of control data reader, signal format converter, deserializer and data logger;
---described data reader, it for the lvds video transfer signal of the first signal conversion chip, and is sent to signal format converter;
---described signal format converter, it for lvds vision signal being converted to the vision signal of bt1120, and is sent to deserializer;
---described deserializer, it for serial data is converted to parallel data, and is sent to data logger;
---described data logger, for bt1120 video signal data is exported;
Described image enhaucament chip comprises: data sink, controller, static memory, image intensifier, data logger and clock generator;
---described data sink, it is for receiving viewdata signal, and is sent to this image intensifier;
---described controller, it is for receiving outer triggering signal, and the operating state of corresponding control data receiver, image enhaucament itself and data logger;
---described static memory, it is for the driving data of memory image booster, to drive the work of this image intensifier;
---described image intensifier, it comprises an image border intensifier circuit; Described image border intensifier circuit is for strengthening the definition of image border;
---described data logger, it for receiving the view data after image intensifier process, and carries out data output;
---described clock generator, it is for being image enhaucament chip clocking.
3. according to claim 2 for the image procossing intensifier circuit of medical endoscope, it is characterized in that: described picture processing chip also comprises a frequency multiplier, its frequency for the triggering signal inputted outside carries out doubling process, then is sent to master controller;
Described first signal conversion chip also comprises a phase-locked loop, is connected respectively, for unified integration clock signal with signal format converter and serializer;
Described secondary signal conversion chip also comprises a phase-locked loop, is connected respectively with signal format converter and serializer, for unified integration clock signal;
Described image enhaucament chip also comprises a de-noising processor; The viewdata signal that described data sink receives, is sent to de-noising processor and carries out noise reduction process, then be forwarded to image intensifier.
4. according to claim 1 for the image procossing intensifier circuit of medical endoscope, it is characterized in that: described image processor also comprises an exposure gain circuit, for increasing exposure gain size;
Described first signal conversion chip also comprises a clock data restorer, and it is connected with data reader, for recovering data from the distortion and noise of transmission channel;
Described secondary signal conversion chip also comprises a clock data restorer, and it is connected with data reader, for recovering data from the distortion and noise of transmission channel;
Described image enhaucament chip also comprises a dynamic memory; View data after described de-noising processor process, is first sent to dynamic memory and stores, then be forwarded to image intensifier.
5. according to claim 3 for the image procossing intensifier circuit of medical endoscope, it is characterized in that: described image processor also comprises an optical detection circuit and flash detection circuit, its brightness for detection image and flashing state, and result of detection is sent to exposure gain circuit;
Described image enhaucament chip also comprises a pixel self adaptation proofreading equipment; View data after process is first sent to described pixel self adaptation proofreading equipment by described image intensifier, carries out pixel and adapts to check and correction, then be sent to data logger by this pixel self adaptation proofreading equipment.
6. the video acquisition intensifier circuit of medical endoscope according to claim 5, is characterized in that: described image enhaucament chip also comprises a vision signal multiplier and a storage signal multiplier; Described clock generator, the clock signal of generation is sent to respectively vision signal multiplier and storage signal multiplier, and by this vision signal multiplier, clock signal is sent to data sink, by this storage signal multiplier, clock signal is sent to dynamic memory and static memory.
7. according to claim 1 for the image procossing intensifier circuit of medical endoscope, it is characterized in that: described picture processing chip outside is provided with: for receive supply power voltage power port, for receive picture signal receiver port, for outputting video signal video signal port, for export row field signal row field signal port, for receive external timing signal clock signal port, store the data receiver port and of data for receiving the PORT COM of external communication order for receiving;
Described first signal conversion chip outside is provided with: described center processing chip exterior is provided with: for receive supply power voltage power port, for receive bt1120 vision signal receiver port, for exporting the video signal port of lvds vision signal and the row field signal port for exporting row field signal;
Described secondary signal conversion chip outside is provided with: described center processing chip exterior is provided with: for receive supply power voltage power port, for receiving the receiver port of lvds vision signal and the video signal port for exporting bt1120 vision signal;
Described image enhaucament chip exterior is provided with: for receive supply power voltage power port, for receive picture signal receiver port, for outputting video signal video signal port, for export row field signal row field signal port, for receiving the clock signal port of external timing signal and storing the data receiver port of data for receiving.
8. according to claim 7 for the image procossing intensifier circuit of medical endoscope, it is characterized in that: the power port of described picture processing chip is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity;
The power port of described picture processing chip is circumscribed with one for the filter circuit of voltage stabilizing; Described filter circuit comprises an inductance and at least one electric capacity; Described inductance one end is connected with external power source, and the other end is connected with each electric capacity respectively, the other end of described each electric capacity and ground connection; Power port is accessed in one end that described inductance is connected with electric capacity.
9. according to claim 7 for the image procossing intensifier circuit of medical endoscope, it is characterized in that: the external clock circuit of clock signal port of described picture processing chip, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port by a debug circuit; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock shake chip power end with to be connected and between inductance and electric capacity; Described debug circuit is made up of resistance and electric capacity; One end of the resistance of this debug circuit is connected with the output of Zhong Zhen, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity; Described clock signal port is connected between this resistance and electric capacity;
The external clock circuit of clock signal port of described image enhaucament chip, it comprises a clock and to shake chip; The shake power end of chip of described clock is connected with power supply by a filter circuit, and the shake output of chip of this clock is connected with described clock signal port; Described filter circuit comprises and being made up of an inductance and capacitances in series, and one end of described inductance is connected with power supply, and the other end is connected with electric capacity, and the other end ground connection of this electric capacity.
10. according to claim 7 for the image procossing intensifier circuit of medical endoscope, it is characterized in that: the data receiver port of described picture processing chip is circumscribed with a memory circuitry, it comprises a memory, is connected to the filter circuit of the voltage port of this memory, and is connected to the resistance of output port of this memory.
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2805688Y (en) * | 2005-07-07 | 2006-08-16 | 傅强 | Endoscope vidicon with automation, manual enhancement and white balance function |
| CN201001147Y (en) * | 2007-01-10 | 2008-01-02 | 云南金隆伟业科技有限公司 | Network digital camera |
| CN101105097A (en) * | 2007-08-23 | 2008-01-16 | 上海交通大学 | Platform shield door intelligent control method |
| CN101217621A (en) * | 2007-01-05 | 2008-07-09 | 安奇逻辑股份有限公司 | Camera module, electronic apparatus having the same and method of manufacturing the same |
| CN101309430A (en) * | 2008-06-26 | 2008-11-19 | 天津市亚安科技电子有限公司 | Video image preprocessor on basis of FPGA |
| CN201229452Y (en) * | 2008-05-30 | 2009-04-29 | 邱环中 | Optical adapter |
| CN101485194A (en) * | 2006-06-30 | 2009-07-15 | 索尼株式会社 | Solid-state image pickup device, data transmitting method and image pickup device |
| CN101620315A (en) * | 2009-08-10 | 2010-01-06 | 浙江大学 | Electronic endoscope image pick-up device |
| CN103519771A (en) * | 2012-07-02 | 2014-01-22 | 富士胶片株式会社 | Light source apparatus and endoscope system |
| CN103607545A (en) * | 2013-11-20 | 2014-02-26 | 四川九洲电器集团有限责任公司 | High definition video acquisition device and working method thereof |
-
2015
- 2015-06-30 CN CN201510385952.4A patent/CN105100548B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2805688Y (en) * | 2005-07-07 | 2006-08-16 | 傅强 | Endoscope vidicon with automation, manual enhancement and white balance function |
| CN101485194A (en) * | 2006-06-30 | 2009-07-15 | 索尼株式会社 | Solid-state image pickup device, data transmitting method and image pickup device |
| CN101217621A (en) * | 2007-01-05 | 2008-07-09 | 安奇逻辑股份有限公司 | Camera module, electronic apparatus having the same and method of manufacturing the same |
| CN201001147Y (en) * | 2007-01-10 | 2008-01-02 | 云南金隆伟业科技有限公司 | Network digital camera |
| CN101105097A (en) * | 2007-08-23 | 2008-01-16 | 上海交通大学 | Platform shield door intelligent control method |
| CN201229452Y (en) * | 2008-05-30 | 2009-04-29 | 邱环中 | Optical adapter |
| CN101309430A (en) * | 2008-06-26 | 2008-11-19 | 天津市亚安科技电子有限公司 | Video image preprocessor on basis of FPGA |
| CN101620315A (en) * | 2009-08-10 | 2010-01-06 | 浙江大学 | Electronic endoscope image pick-up device |
| CN103519771A (en) * | 2012-07-02 | 2014-01-22 | 富士胶片株式会社 | Light source apparatus and endoscope system |
| CN103607545A (en) * | 2013-11-20 | 2014-02-26 | 四川九洲电器集团有限责任公司 | High definition video acquisition device and working method thereof |
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|---|---|
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