CN105047603A - 一种混合键合金属突出界面的处理方法 - Google Patents
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- 239000002184 metal Substances 0.000 title claims abstract description 46
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 46
- 238000003672 processing method Methods 0.000 title claims abstract description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 23
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 21
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052802 copper Inorganic materials 0.000 claims abstract description 8
- 239000010949 copper Substances 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 8
- 239000000126 substance Substances 0.000 claims abstract description 7
- 238000000227 grinding Methods 0.000 claims abstract description 6
- 238000001465 metallisation Methods 0.000 claims abstract description 4
- 238000001259 photo etching Methods 0.000 claims abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 3
- 239000012774 insulation material Substances 0.000 abstract 1
- 238000005498 polishing Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 7
- 239000010408 film Substances 0.000 description 3
- 235000019994 cava Nutrition 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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Abstract
本发明涉及一种混合键合金属突出界面的处理方法。包括如下步骤：提供一待处理晶圆，晶圆表面形成有一氮化硅层，在氮化硅层上淀积一薄膜层；涂布光刻胶覆盖薄膜层的上表面，依次采用光刻、刻蚀方法于薄膜层和氮化硅层中形成沟槽；利用金属沉积方法淀积金属填充沟槽并覆盖薄膜层上表面；利用化学机械研磨方法去除薄膜层表面的金属铜及部分的薄膜层，确保沟槽上方的金属铜全部被去除；对薄膜层进行刻蚀，得到薄膜层与金属之间的金属突出界面；继续刻蚀，刻蚀止于氮化硅层，得到氮化硅层与金属之间的金属突出界面。本发明可以解决由于绝缘物质的硬度带来的，由化学机械研磨无法制造金属突出键合表面的困难，具有良好的效果。
Description
技术领域
本发明涉及半导体制造领域，具体涉及一种混合键合金属突出界面的处理方法。
背景技术
在超大规模集成电路发展日益接近物理极限的情况下，于物理尺寸和成本方面都具有优势的三维集成电路是延长摩尔定律并解决先进封装问题的有效途径。而晶圆键合技术正是三维电路集成的关键技术之一，尤其是混合键合技术可以在两片晶圆键合的同时实现数千个芯片的内部互联，可以极大改善芯片性能并节约成本。混合键合技术是指晶圆键合界面上同时存在金属和绝缘物质的键合方式。
混合键合表面同时存在金属和绝缘物质，制造出金属突出或凹陷的键合界面可有效减低键合对表面平坦度的要求。但当绝缘物质比较硬时，很难通过传统的化学机械研磨方法得到金属突出的界面。
发明内容
本发明的目的是提供一种表面处理技术，以制造混合键合技术中所要求的金属突出键合表面。
为解决上述技术问题，本发明提供了一种混合键合金属突出界面的处理方法，包括如下步骤：
步骤一，提供一待处理晶圆，所述晶圆表面形成有一氮化硅层，在所述氮化硅层上淀积一薄膜层；
步骤二，涂布光刻胶覆盖所述薄膜层的上表面，依次采用光刻、刻蚀方法于所述薄膜层和氮化硅层中形成沟槽；
步骤三，利用金属沉积方法淀积金属填充所述沟槽并覆盖所述薄膜层上表面；
步骤四，利用化学机械研磨方法去除所述薄膜层表面的金属铜及部分的薄膜层，确保所述沟槽上方的金属铜全部被去除；
步骤五，对所述薄膜层进行刻蚀，得到所述薄膜层与金属之间的金属突出界面；继续刻蚀，刻蚀止于所述氮化硅层，得到所述氮化硅层与金属之间的金属突出界面。
优选的，所述薄膜层的材质为二氧化硅或碳化硅。
本发明的有益效果是：本发明可以忽略由于绝缘物质的硬度带来的，由传统技术(如化学机械研磨)无法制造金属突出键合表面的困难。
附图说明
图1至图6为本发明一种混合键合金属突出界面的处理方法实施例流程剖面示意图。
附图中，各标号所代表的部件列表如下：
1、晶圆，2、氮化硅层，3、薄膜层，4、金属。
具体实施方式
以下结合附图对本发明的原理和特征进行描述，所举实例只用于解释本发明，并非用于限定本发明的范围。
混合键合表面同时存在金属和绝缘物质，制造出金属突出或凹陷的键合界面可有效减低键合对表面平坦度的要求；但当混合键合表面的绝缘物质比较硬时，很难通过传统的化学机械研磨方法得到混和键合金属突出界面，本发明是在待处理的晶圆表面绝缘物质上沉积一层较软的薄膜(如处理氮化硅和金属表面时，在氮化硅表面沉积一层二氧化硅)，之后再进行传统的金属后端互联工艺，在最后进行表面处理时，首先得到金属与较软薄膜之间的金属突出界面，再找到将薄膜耗尽的临界点，即制造出金属绝缘物质之间的金属突出界面；因而可以忽略由于绝缘物质的硬度带来的，由传统技术(如化学机械研磨)无法制造金属突出键合表面的困难。
图1至图6为本发明一种混合键合金属突出界面的处理方法实施例工艺流程结构示意图，如图1至图6所示，一种混合键合金属突出界面的处理方法，包括如下步骤：
步骤一，提供一待处理晶圆1，晶圆1表面形成有一氮化硅层2，在氮化硅层2上淀积一薄膜层3；薄膜层3的材质为二氧化硅或碳化硅；
步骤二，涂布光刻胶覆盖薄膜层3的上表面，依次采用光刻、刻蚀方法于薄膜层3和氮化硅层2中形成沟槽；
步骤三，利用金属沉积方法淀积金属4填充沟槽并覆盖薄膜层3上表面；
步骤四，利用化学机械研磨方法去除薄膜层3表面的金属铜及部分的薄膜层3，确保沟槽上方的金属铜全部被去除；
步骤五，对薄膜层3进行刻蚀，得到薄膜层3与金属之间的金属突出界面；继续刻蚀，刻蚀止于氮化硅层2，得到氮化硅层2与金属之间的金属突出界面。
以上所述实施步骤和方法仅仅表达了本发明的一种实施方式，描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。在不脱离本发明专利构思的前提下，所作的变形和改进应当都属于本发明专利的保护范围。
Claims (2)
1.一种混合键合金属突出界面的处理方法，其特征在于，包括如下步骤：
步骤一，提供一待处理晶圆，所述晶圆表面形成有一氮化硅层，在所述氮化硅层上淀积一薄膜层；
步骤二，涂布光刻胶覆盖所述薄膜层的上表面，依次采用光刻、刻蚀方法于所述薄膜层和氮化硅层中形成沟槽；
步骤三，利用金属沉积方法淀积金属填充所述沟槽并覆盖所述薄膜层上表面；
步骤四，利用化学机械研磨方法去除所述薄膜层表面的金属铜及部分的薄膜层，确保所述沟槽上方的金属铜全部被去除；
步骤五，对所述薄膜层进行刻蚀，得到所述薄膜层与金属之间的金属突出界面；继续刻蚀，刻蚀止于所述氮化硅层，得到所述氮化硅层与金属之间的金属突出界面。
2.根据权利要求1所述一种混合键合金属突出界面的处理方法，其特征在于，所述薄膜层的材质为二氧化硅或碳化硅。
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109346419A (zh) * | 2018-12-05 | 2019-02-15 | 德淮半导体有限公司 | 半导体器件及其制造方法 |
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| CN101197297A (zh) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | 晶片压焊键合方法及其结构 |
| US20100255262A1 (en) * | 2006-09-18 | 2010-10-07 | Kuan-Neng Chen | Bonding of substrates including metal-dielectric patterns with metal raised above dielectric |
| CN104167353A (zh) * | 2014-08-08 | 2014-11-26 | 武汉新芯集成电路制造有限公司 | 键合衬底表面的处理方法 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100255262A1 (en) * | 2006-09-18 | 2010-10-07 | Kuan-Neng Chen | Bonding of substrates including metal-dielectric patterns with metal raised above dielectric |
| CN101197297A (zh) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | 晶片压焊键合方法及其结构 |
| CN104167353A (zh) * | 2014-08-08 | 2014-11-26 | 武汉新芯集成电路制造有限公司 | 键合衬底表面的处理方法 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109346419A (zh) * | 2018-12-05 | 2019-02-15 | 德淮半导体有限公司 | 半导体器件及其制造方法 |
| CN109346419B (zh) * | 2018-12-05 | 2020-11-06 | 德淮半导体有限公司 | 半导体器件及其制造方法 |
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