CN105045752A - High speed AD data PXI bus transmission analytic method based on wide SRAM memory - Google Patents
High speed AD data PXI bus transmission analytic method based on wide SRAM memory Download PDFInfo
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- CN105045752A CN105045752A CN201510400890.XA CN201510400890A CN105045752A CN 105045752 A CN105045752 A CN 105045752A CN 201510400890 A CN201510400890 A CN 201510400890A CN 105045752 A CN105045752 A CN 105045752A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0024—Peripheral component interconnect [PCI]
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Abstract
The invention provides a high speed AD data PXI bus transmission analytic method based on wide SRAM memory. SRAM address space addressing decoding and multiple reading strobe judgment processing of once SRAM read data are carried out directly through a PXI bus address in a manner of synchronous control implementation of address decoding and address strobe, a coordinated processing procedure of multiple links during a data processing flow is simplified greatly, meanwhile, the problem of matching between a SRAM operating speed and a PXI bus speed is solved skilfully in a manner of direct decoding and addressing of the address in the SRAM address space, trouble and hidden risks of a separate design of a SRAM read clock and a SRAM write clock are avoided; in a manner of directly performing strobe reading on once data segments of the SRAM through the PXI address, logic implementation of FPGA is reduced, simultaneously, the manner of strobe reading can be combined with the SRAM addressing skilfully, and direct SRAM wide data continuous reading of the PXI is realized.
Description
Technical field
The present invention relates to digital processing field, particularly a kind of high-speed AD data PXI bus transfer analytic method stored based on wide mouth SRAM.
Background technology
Under low speed sampling situations, because sampling rate is not high, only the SRAM of applicable sampling width need be used to carry out design Storage, usually not need wide mouth SRAM to carry out storage to realize, so the data transmission of SRAM is resolved also relatively easy many.
And under high speed sampling condition, because sampling rate all samples with GSps or more usually, the operating rate of rear end SRAM is difficult to reach the requirement matched, so in order to realize real-time storage, must process in the mode of changing down, expansion interface width, the expansion of memory interface width makes the matching problem between itself and transfer bus complicated.
In the prior art, in rate-matched, there is the method that uses different SRAM to read and write clock to process the solution that PXI bus and SRAM read and write rate matching issue, take SRAM write clock and high-speed AD to sample and carry out matched design, SRAM reads clock and PXI Bus Speed carries out matched design, thus carry out the process of coordinate storage transmission, but there are two kinds of operating clocks for SRAM in the method, add the complicacy of SRAM sequential control and the risk of storage implementation process, be unfavorable for that FPGA carries out the stability Design of logic control.
In data width matching transmission, because SRAM interface width is wider than bus interface width, as multi-disc parallel connection uses, then often reach the doubly poor relation of tens times or tens times, because bus once can not take the data read-out by a SRAM reading away, often need inside in FPGA to do logical circuit of counter and judge that gradation transmission is carried out in process, this kind of mode not only adds fpga logic flow process, bus transfer efficiency is also made to reduce, immediate data reading can not be carried out in continuation address mode, add PXI bus read operation number of times, extend and read T.T., when especially Large Volume Data being read, the time expended is by the speed of the speed and display update that directly affect main control computer process.
Summary of the invention
For solving above-mentioned the deficiencies in the prior art, the present invention proposes a kind of high-speed AD data PXI bus transfer analytic method stored based on wide mouth SRAM.
Technical scheme of the present invention is achieved in that
Based on the high-speed AD data PXI bus transfer analytic method that wide mouth SRAM stores, comprise the following steps:
Step (1): transmission resolving is read for the PXI bus stored in N high-speed AD sampled data in SRAM, first needs according to the total interface width K of SRAM data
1, high-speed AD sample quantization bit wide K
2, PXI bus data interface width K
3, SRAM address-bus width W
2determine the decoding of PXI address bus composition and PXI bus read from SRAM N high-speed AD sampled data the actual reading times NL that need carry out;
Step (2): after the actual times N L that need carry out read operation of PXI bus determines, then host computer main control unit is by PXI bus from the base address set, carries out traveling through peek continuously NL time, obtains NL K successively
3the data array X of bit wide
nL;
Step (3): judge data array X
nLwhether needing the rejecting process carrying out gibberish, is then to X
nLcarry out gibberish and reject process, and obtain N
5the SRAM new data array X that the individual PXI containing useful AD data reads
l; Otherwise by data array X
nLindirect assignment is to data array X
l;
Step (4): to data array X
lcarry out the separating treatment of AD data, obtain the N number of high-speed AD sampled data array X read from SRAM, X data are passed to next flow process and are carried out other signal analysis and processing, and return step (1), wait for the transmission dissection process of next group data.
Alternatively, in described step (1), described PXI address bus is decoded as and is made up of SRAM address space addressable address section and address strobe control address field;
Wherein, SRAM address space addressable address section is wide is W
2, decided by the address-bus width of SRAM device, in this section, address bus docks with SRAM address bus in FPGA; It is W that address strobe controls address field bit wide
1; The low W of PXI address bus
1-1 to 0 is defined as address strobe and controls address field, the W of PXI address bus
2+ W
1-1 to W
1position is defined as SRAM address space addressable address section.
Alternatively, described address strobe controls address field bit wide W
1defining method be: it need meet following relation:
Wherein, N
1be defined as the maximum number of the complete AD sampled data that SRAM read data packet contains, N
2be defined as a PXI bus and read the maximum complete AD sampled data number comprised of data;
Wherein,
value be set to N
3, represent SRAM read data transmitted by PXI bus needed for number of times; N
1%N
2value be set to N
4if, N
4be greater than 0, represent that the last AD data amount check read is less than N
2.
Alternatively, the maximum number N of the complete AD sampled data that a described SRAM read data packet contains
1defining method be K
1with K
2the maximum positive integer value of ratio:
in a SRAM data reading, AD data arrange from low to high with sampling order.
Alternatively, described N
1defining method in, work as K
1with K
2when ratio is integer, SRAM storage resources realizes the peak use rate that AD data store.
Alternatively, a described PXI bus reads the maximum complete AD sampled data number N comprised of data
2defining method be K
3with K
2the maximum positive integer value of ratio:
Alternatively, described N
2defining method in, work as K
3with K
2when ratio is integer, PXI data bus interface realizes the peak use rate of AD data transmission.
Alternatively, described W
1defining method in, work as N
3equal
time, address strobe controls the gating coding of address field to AD data and realizes peak use rate.
Alternatively, described W
1defining method in, work as N
3equal
time, and N
4when equaling 0, PXI bus realizes the maximizing efficiency of AD data transmission.
Alternatively, in described step (1), described PXI bus read from SRAM N high-speed AD sampled data the defining method of the actual reading times NL that need carry out be:
Wherein,
value be set to N
5, for calculating the PXI number of operations needed for N AD sampled data reading,
n is greater than because address strobe controls address field coded number for calculating during N AD sampled data reads continuously
3time need the number of operations of PXI bus gibberish that do more.
Alternatively, in described step (2), described NL time traversal peek operation continuously, comprises the following steps:
Step (21): set the count number of traversal peek continuously as I, initialization value is 0;
Step (22): be added by PXI bus base address and count number I and obtain PXI bus address, PXI bus initiates reading request;
Step (23): FPGA is after receiving reading request, according to SRAM address space addressable address, SRAM is peeked, then control address according to address strobe to judge, and give PXI data bus by the AD data of gating corresponding in current SRAM data;
Step (24): main control unit receives data bus K
3the data of bit wide, and assignment is to data array X
nLwith the numerical value of I index, count number I adds 1;
Step (25): judge whether count number I equals NL, is, represents that NL peek is complete, waits pending AD Data Analysis flow process, otherwise return step (22).
Alternatively, in described step (23), described control address according to address strobe and carry out judging and the disposal route that the AD data current SRAM being read corresponding gating in data give PXI data bus is:
Meter W
1it is E that the gating of bit wide controls address bit values, as E < N
3when-1, by E × N that SRAM institute read data comprises
2to (E+1) × N
2-1 AD data with the common assignment of a definite sequence to PXI data bus; As E==(N
3-1) time, as N
4equal 0, then by E × N that SRAM institute read data comprises
2to (E+1) × N
2-1 AD data with the common assignment of a definite sequence to PXI data bus, if N
4be not equal to 0, then by E × N that SRAM institute read data comprises
2to E × N
2+ N
4-1 AD data with the common assignment of a definite sequence to PXI data bus; If
send 0 process then to PXI bus data.
Alternatively, described AD data with the common assignment of a definite sequence to the assignment method of PXI data bus are: E × N
2individual AD data assignment is to the K of PXI data bus
2-1 to the 0th, E × N
2+ 1 AD data assignment is to the 2nd × K of PXI data bus
2-1 to K
2position, the rest may be inferred, (E+1) × N
2-1 AD data assignment is to the N of PXI data bus
2× K
2-1 to (N
2-1) × K
2position, if PXI data bus N
2× K
2position and position of also having a surplus above, then remaining position zero padding process or do not process; If N
4be not equal to 0, then when E equals (N
3-1) time, the complete E × N of assignment
2+ N
4after-1 AD data, the high-order zero padding process of the residue of PXI data bus or do not process.
Alternatively, described W
1the defining method of the gating control address bit values E of bit wide is:
wherein subscript H represents the binary value under the corresponding positions of gating address.
Alternatively, in described step (3), the described foundation of whether carrying out gibberish rejecting process is: N
3whether equal
that W is described
1just in time with one time, the address SRAM that the address strobe of bit wide controls address field coding gating read data transmitted by PXI bus needed for number of times match, without the need to carrying out the transmission operation of zero padding gibberish; If
continuous transmission work in order to realize PXI bus is then described, centre needs to carry out
the gibberish transmission operation of number of times.
Alternatively, in described step (3), described to X
nLcarry out the process that gibberish rejects process, comprise the following steps:
Step (31): establish data array X
nLthe count number of operation is J
1, to new data array X
lthe count number of operation is J
2, J
1and J
2equal initialization value is 0;
Step (32): judge J
1with
whether the remainder of complementation is more than or equal to N
3, be enter step (33); Otherwise enter step (34);
Step (33): J
1add 1, enter step (35);
Step (34): by array X
nLwith J
1the data assignment of index is to array X
lwith J
2the data of index, J
1add 1, J
2add 1, enter step (35);
Step (35): judge J
1whether be less than NL, be, return step (32), otherwise represent that gibberish has been rejected complete, wait the separating treatment of pending AD data.
Alternatively, in described step (4), described to data array X
lcarry out the separating treatment process of AD data, comprise the following steps:
Step (41): establish data array X
lthe count number of operation is R
1, the count number operated final AD data array X is R
2, R
3for being separated count number, R
1, R
2and R
3equal initialization value is 0, and sets θ as K
2bit wide every is the binary number of 1 entirely;
Step (42): by array X
lwith R
1the data assignment of index is K to bit wide
3service data δ, and judge R
1with N
3whether the remainder of complementation equals N
3-1, be enter step (43); Otherwise enter step (44);
Step (43): judge N
4whether equal 0, be, enter step (44); Otherwise enter step (47);
Step (44): δ and θ is carried out step-by-step with operation obtain only retain its low K
2the new data assignment of bit data to array X with R
2the data of index, R
2add 1, R
3add 1, enter step (45);
Step (45): judge R
3whether equal N
2, be then R
3assignment 0, R
1add 1, then proceed to step (410); Otherwise enter step (46);
Step (46): by δ to the right according to K
2position, then carry out with θ step-by-step with operation obtain only retain its low K
2the new data assignment of bit data to array X with R
2the data of index, R
2add 1, R
3add 1, then return step (45);
Step (47): δ and θ is carried out step-by-step with operation obtain only retain its low K
2the new data assignment of bit data to array X with R
2the data of index, R
2add 1, R
3add 1, enter step (48);
Step (48): judge R
3whether equal N
4, be then R
3assignment 0, R
1add 1, then proceed to step (410); Otherwise enter step (49);
Step (49): by δ to the right according to K
2position, then carry out with θ step-by-step with operation obtain only retain its low K
2the new data assignment of bit data to array X with R
2the data of index, R
2add 1, R
3add 1, then return step (48);
Step (410): judge R
1whether be less than N
5, be return step (42), otherwise represent that the separating treatment work of N number of AD data completes.
Alternatively, described PXI address bus, the bus data variable quantity of its address increment counts K
3, for the situation of carrying out incremental computations with byte, need by
bit wide is as lowest order address increment, and other corresponding address fields are to moving to left
position.
Alternatively, carry out the timing really of PXI bus address, for the situation taking byte as increment, need with count number
calculate as address change.
The invention has the beneficial effects as follows:
(1) the repeatedly reading gating judgement process of SRAM address space addressing decode and SRAM reading data is directly carried out by PXI bus address, carry out in order to the mode realized by address decoding and address strobe synchro control, enormously simplify the Coordination Treatment process of multiple link in flow chart of data processing;
(2) in the mode of the direct decoding addressing in address SRAM address space, the problem that the ingenious SRAM of solving operation rate and PXI Bus Speed match, avoids trouble and risk hidden danger that SRAM reads and writes clock separate design;
(3) read the data section mode of a SRAM by the direct gating in PXI address, decrease fpga logic and realize, also can combine with SRAM addressing cleverly, the wide mouth data of direct SRAM realizing PXI bus read continuously simultaneously;
(4) carry out data continuous read operation fast in the mode of PXI Bulk transport or burst transfer, substantially increase speed and the efficiency of the reading of wide mouth SRAM data, shorten the time of host computer data processing, improve system performance.
Embodiment
Below in conjunction with in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
In high-speed sampling design is implemented, because high-speed AD sampling rate is high, rear end real-time storage difficulty can be very large, sampling rate and memory rate need be considered during design, matching relationship good between sampling bit wide and memory interface width, usually stores and all adopts the mode of multi-disc wide mouth SRAM parallel memorizing to carry out, reduce memory rate in the mode of extension storage interface width, improve logic operative, reduce storing process risk.And the expansion of SRAM interface width, in PXI bus transfer and parsing, bring again new problem, make transmission coupling complicated, transmission is resolved complicated.Method of the present invention just based on realize under this background be adapted to high-speed AD sampled data SRAM store after by PXI bus carry out transmit resolve method.
The present invention proposes a kind of high-speed AD data PXI bus transfer analytic method stored based on wide mouth SRAM, its ultimate principle is the mode utilizing address decoding and address strobe synchronously to realize, the high-speed AD sampled data transmission being carried out SRAM storage by FPGA is read and data transmission matching design, the ingenious synchronism problem solving SRAM operation rate and PXI Bus Speed, solve the matching transmission problem of SRAM interface width and PXI highway width, achieve high-speed AD data effectively the transmitting in order by PXI bus that SRAM stores, effective improvement transmission control flow, improve bus transfer timeliness, simultaneously specification AD data bus transmission form, simplify the transmission of AD data and resolve difficulty, can elevator system transmission performance.
The repeatedly reading gating that the inventive method directly carries out SRAM address space addressing decode and SRAM reading data by PXI bus address judges process, carries out in order to the mode realized by address decoding and address strobe synchro control.PXI bus address is made up of two parts, and low level section part is that address strobe controls address field, and high-order section is SRAM address space addressable address section.SRAM addressable address section is directly docked with SRAM address bus in FPGA, the mode of SRAM addressing of address change is directly upgraded by PXI bus appropriate address section, when high-speed sampling SRAM operation rate is far above PXI Bus Speed, the nonsynchronous problem of SRAM and PXI Bus Speed can be ignored, bring great convenience to design, can effectively simplify FPGA design cycle.The change of low level sector address gating, the process of high-order segment addressing decoding can not be affected, by the organic assembling of PXI bus address, when PXI bus carries out reading transmission continuously, always make low level section gating address and the co-ordination of high-order section decoding addressable address, realize the maximization transmittability of PXI bus under its configuration surroundings.
PXI bus address two parts specifically take how many addresses bit wide, take which address bit scope of address, need be determined by SRAM total data interface width, high-speed AD sampling bit wide, PXI bus data interface width, SRAM maximum address scope etc.
A kind of high-speed AD data PXI bus transfer analytic method stored based on wide mouth SRAM of the present invention, specifically comprises the following steps:
Step (1): transmission resolving is read for the PXI bus stored in N high-speed AD sampled data in SRAM, first needs according to the total interface width K of SRAM data
1, high-speed AD sample quantization bit wide K
2, PXI bus data interface width K
3, SRAM address-bus width W
2determine the decoding of PXI address bus composition and PXI bus read from SRAM N high-speed AD sampled data the actual reading times NL that need carry out;
Step (2): after the actual times N L that need carry out read operation of PXI bus determines, then host computer main control unit is by PXI bus from the base address set, carries out traveling through peek continuously NL time, obtains NL K successively
3the data array X of bit wide
nL;
Step (3): judge data array X
nLwhether needing the rejecting process carrying out gibberish, is then to X
nLcarry out gibberish and reject process, and obtain N
5the SRAM new data array X that the individual PXI containing useful AD data reads
l; Otherwise by data array X
nLindirect assignment is to data array X
l;
Step (4): to data array X
lcarry out the separating treatment of AD data, obtain the N number of high-speed AD sampled data array X read from SRAM, X data are passed to next flow process and are carried out other signal analysis and processing, and return step (1), wait for the transmission dissection process of next group data.
In above-mentioned steps (1), PXI address bus is decoded as and is made up of SRAM address space addressable address section and address strobe control address field.
Wherein, SRAM address space addressable address section is wide is W
2, decided by the address-bus width of SRAM device, in this section, address bus docks with SRAM address bus in FPGA; It is W that address strobe controls address field bit wide
1; The low W of PXI address bus
1-1 to 0 is defined as address strobe and controls address field, the W of PXI address bus
2+ W
1-1 to W
1position is defined as SRAM address space addressable address section.
Above-mentioned address strobe controls address field bit wide W
1defining method be: it need meet following relation:
N
1be defined as the maximum number of the complete AD sampled data that SRAM read data packet contains, N
1defining method be K
1with K
2the maximum positive integer value of ratio:
here suppose that in the SRAM data read, AD data arrange with sampling order from low to high, the data row number namely first adopted is minimum, N
1in the SRAM data that individual AD data read at homogeneous on the time the most rearward.
Above-mentioned N
1defining method in, work as K
1with K
2when ratio is integer, SRAM storage resources realizes the peak use rate that AD data store.
N
2be defined as a PXI bus and read the maximum complete AD sampled data number comprised of data, N
2defining method be K
3with K
2the maximum positive integer value of ratio:
Above-mentioned N
2defining method in, work as K
3with K
2when ratio is integer, PXI data bus interface realizes the peak use rate of AD data transmission.
value be set to N
3, represent SRAM read data transmitted by PXI bus needed for number of times; N
1%N
2value be set to N
4if, N
4be greater than 0, represent that the last AD data amount check read is less than N
2.
Above-mentioned W
1defining method in, work as N
3equal
time, address strobe controls the gating coding of address field to AD data and realizes peak use rate.
Above-mentioned W
1defining method in, work as N
3equal
time, and N
4when equaling 0, PXI bus realizes the maximizing efficiency of AD data transmission.
Work as K
1with K
2when ratio is integer, work as K
3with K
2when ratio is integer, work as N
3equal
time, and N
4when equaling 0, SRAM storage resources can be realized, PXI bus interface resource utilization maximizes, PXI bus transfer maximizing efficiency.
In above-mentioned steps (1), PXI bus read from SRAM N high-speed AD sampled data the defining method of the actual reading times NL that need carry out be:
Wherein,
value be set to N
5, for calculating the PXI number of operations needed for N AD sampled data reading,
n is greater than because address strobe controls address field coded number for calculating during N AD sampled data reads continuously
3time need the number of operations of PXI bus gibberish that do more.
In above-mentioned steps (2), described NL time traversal peek operation continuously, comprises the following steps:
Step (21): set the count number of traversal peek continuously as I, initialization value is 0;
Step (22): be added by PXI bus base address and count number I and obtain PXI bus address, PXI bus initiates reading request; Above-mentioned PXI bus base address, can start for zero-address, also can start non-vanishing address, can do determine according to concrete PXI address utilization and SRAM storage condition;
Step (23): FPGA is after receiving reading request, according to SRAM address space addressable address, SRAM is peeked, then control address according to address strobe to judge, and give PXI data bus by the AD data of gating corresponding in current SRAM data;
Step (24): main control unit receives data bus K
3the data of bit wide, and assignment is to data array X
nLwith the numerical value of I index, count number I adds 1;
Step (25): judge whether count number I equals NL, is, represents that NL peek is complete, waits pending AD Data Analysis flow process, otherwise return step (22).
In above-mentioned steps (23), control address according to address strobe and carry out judging and the disposal route that the AD data current SRAM being read corresponding gating in data give PXI data bus is:
Meter W
1it is E that the gating of bit wide controls address bit values, as E < N
3when-1, by E × N that SRAM institute read data comprises
2to (E+1) × N
2-1 AD data with the common assignment of a definite sequence to PXI data bus; As E==(N
3-1) time, as N
4equal 0, then by E × N that SRAM institute read data comprises
2to (E+1) × N
2-1 AD data with the common assignment of a definite sequence to PXI data bus, if N
4be not equal to 0, then by E × N that SRAM institute read data comprises
2to E × N
2+ N
4-1 AD data with the common assignment of a definite sequence to PXI data bus; If
send 0 process then to PXI bus data.
Wherein, AD data with the common assignment of a definite sequence to the assignment method of PXI data bus are: E × N
2individual AD data assignment is to the K of PXI data bus
2-1 to the 0th, E × N
2+ 1 AD data assignment is to the 2nd × K of PXI data bus
2-1 to K
2position, the rest may be inferred, (E+1) × N
2-1 AD data assignment is to the N of PXI data bus
2× K
2-1 to (N
2-1) × K
2position, if PXI data bus N
2× K
2position and position of also having a surplus above, then remaining position zero padding process or do not process; If N
4be not equal to 0, then when E equals (N
3-1) time, the complete E × N of assignment
2+ N
4after-1 AD data, the high-order zero padding process of the residue of PXI data bus or do not process.
Wherein, W
1the defining method of the gating control address bit values E of bit wide is:
wherein subscript H represents the binary value under the corresponding positions of gating address.
In above-mentioned steps (3), the foundation of whether carrying out gibberish rejecting process is: N
3whether equal
that W is described
1just in time with one time, the address SRAM that the address strobe of bit wide controls address field coding gating read data transmitted by PXI bus needed for number of times match, without the need to carrying out the transmission operation of zero padding gibberish; If
continuous transmission work in order to realize PXI bus is then described, centre needs to carry out
the gibberish transmission operation of number of times.
In above-mentioned steps (3), to X
nLcarry out the process that gibberish rejects process, comprise the following steps:
Step (31): establish data array X
nLthe count number of operation is J
1, to new data array X
lthe count number of operation is J
2, J
1and J
2equal initialization value is 0;
Step (32): judge J
1with
whether the remainder of complementation is more than or equal to N
3, be enter step (33); Otherwise enter step (34);
Step (33): J
1add 1, enter step (35);
Step (34): by array X
nLwith J
1the data assignment of index is to array X
lwith J
2the data of index, J
1add 1, J
2add 1, enter step (35);
Step (35): judge J
1whether be less than NL, be, return step (32), otherwise represent that gibberish has been rejected complete, wait the separating treatment of pending AD data.
In above-mentioned steps (4), described to data array X
lcarry out the separating treatment process of AD data, comprise the following steps:
Step (41): establish data array X
lthe count number of operation is R
1, the count number operated final AD data array X is R
2, R
3for being separated count number, R
1, R
2and R
3equal initialization value is 0, and sets θ as K
2bit wide every is the binary number of 1 entirely;
Step (42): by array X
lwith R
1the data assignment of index is K to bit wide
3service data δ, and judge R
1with N
3whether the remainder of complementation equals N
3-1, be enter step (43); Otherwise enter step (44);
Step (43): judge N
4whether equal 0, be, enter step (44); Otherwise enter step (47);
Step (44): δ and θ is carried out step-by-step with operation obtain only retain its low K
2the new data assignment of bit data to array X with R
2the data of index, R
2add 1, R
3add 1, enter step (45);
Step (45): judge R
3whether equal N
2, be then R
3assignment 0, R
1add 1, then proceed to step (410); Otherwise enter step (46);
Step (46): by δ to the right according to K
2position, then carry out with θ step-by-step with operation obtain only retain its low K
2the new data assignment of bit data to array X with R
2the data of index, R
2add 1, R
3add 1, then return step (45);
Step (47): δ and θ is carried out step-by-step with operation obtain only retain its low K
2the new data assignment of bit data to array X with R
2the data of index, R
2add 1, R
3add 1, enter step (48);
Step (48): judge R
3whether equal N
4, be then R
3assignment 0, R
1add 1, then proceed to step (410); Otherwise enter step (49);
Step (49): by δ to the right according to K
2position, then carry out with θ step-by-step with operation obtain only retain its low K
2the new data assignment of bit data to array X with R
2the data of index, R
2add 1, R
3add 1, then return step (48);
Step (410): judge R
1whether be less than N
5, be return step (42), otherwise represent that the separating treatment work of N number of AD data completes.
PXI address bus, the bus data variable quantity of its address increment counts K
3, for the situation of carrying out incremental computations with byte, the inventive method is applicable equally, only need by
bit wide is as lowest order address increment, and other corresponding address fields are to moving to left
position; For the situation taking byte as increment, in step (2), carry out bus address timing really, need with count number
calculate as address change.
Below in conjunction with a specific embodiment, method of the present invention is described in detail.
First, assuming that the total interface width K of SRAM data
1be 144 bit wides, high-speed AD sample quantization bit wide K
2be 12 bit wides, PXI bus data interface width K
3be that 32 bit wides resolve implementation process explanation to the concrete transmission carrying out the inventive method.
According to above information, first determine the mode of PXI address segmentation composition.For the data of a SRAM reading, the sampled data number N that it comprises
1, can be defined as
In order to pare down expenses, maximize the utilization realizing storage resources, when designing, SRAM interface width is chosen for the integral multiple of AD bit wide, for non-integral multiple, the SRAM bit wide that remaining deficiency once stores is by idle.
For the sampled data number N that the data of a PXI bus reading can maximumly comprise
2for K
3with K
2the maximum positive integer value of ratio, namely
therefore, address strobe controls the bit wide W of address field
1need meet
namely
w can be determined thus
1be 3, namely adopt 2 ~ 0 of PXI address bus to carry out address strobe and control address field, realize the gating read operation to 12 AD sampled datas that SRAM address reading data comprises.And the wide W of SRAM address space addressable address section
2being determined by selected concrete SRAM type number, such as, drafting SRAM in the present embodiment is 1M addressing space, therefore W
2=20, namely adopt 22 ~ 3 of PXI address bus and carry out the addressing of SRAM address decoding, so PXI address bus only uses its low 23 to carry out data read-write operation in the present embodiment.
Because SRAM data overall width is 144, a SRAM reads and comprises 12 AD sampled datas, and PXI data-bus width is 32, once read and can read at most 2 complete AD sampled datas, so the data of a SRAM reading need 6 PXI read operations can read complete, and adopt 2 ~ 0 of PXI address bus to carry out address strobe control, 3 bit address can control the reading of 8 secondary data by gating, in order to realize the continuous read operation of PXI bus, every 8 gatings control high 2 times in FPGA to send zero to fill.According to the order of digital independent, what need were strict gives corresponding data by the order that 6 times are read in FPGA, and the control that SRAM data reading is carried out in PXI address is described below shown in table 1.
Table 1:PXI address uses and describes
Because AD sampling output data width is 12, so comprise 2 AD data altogether for each 32 PXI data, 11 ~ 0 is (n-1)th sampling, 23 ~ 12 is n-th sampling, 31 ~ 24 do not pay close attention to, and low precedence is front in high precedence in time, and data increase progressively reading from low to high according to address.
For the reading transmission resolving stored in N=1024 sampled data in SRAM, before the peek of host computer main control unit, the address realm of reality when first determining that PXI bus is peeked according to the length of required acquisition sampled data.
Because each SRAM addressing is changed once, often get 12 AD data, PXI bus just need be carried out 2 times and invalid be got Z-operation, so the actual number of times carrying out peeking of PXI bus is more than the N secondary data of actual needs, the actual continuous-reading times N L of PXI bus, can be defined as:
Wherein,
for calculating the PXI number of operations needed for N sampled data reading,
for calculating during N sampled data reads continuously the PXI number of operations needing to do more.
PXI is actual need read operation number of times to determine after, from the base address set, 682 continuation addresses carrying out 32 bit data bus increase progressively peek, obtain the data array X of 682 32 bit wides
nL.The base address of PXI can start for zero-address herein, also can start non-vanishing address, can change according to concrete PXI address utilization and SRAM storage condition, can flexible Application.Then, based on this data array, carry out the parsing transmitting data.
Because of in the present embodiment, first the null value gibberish that the last data obtained for 2 times of low 3 continually varyings of PXI bus address are sent for FPGA, so need to be weeded out.
The method rejecting gibberish is, from data array X
nL682 data start counting, if be 6 or 7 with count value by the value of 8 complementations, then judge that these data are as gibberish, rejected, if remainder is not 6 or 7, be then judged to be useful reading data, by its successively assignment to new data array X
l, finally reject 170 gibberishes, obtain 512 useful datas.
Useful data array X
leach data be 32 bit wide PXI data, each data containing 2 useful AD data, so need by X
leach data carry out the separation of AD data, be reassembled into 1024 AD data of actual needs, the method for separation is: from data array X
lstart carry out, step-by-step and operation is carried out with sexadecimal number 0xFFF by low 12 of 32 bit data, the new number obtained only will retain its low 12 effective informations, be effective AD data, assignment is to final data array X, 32 bit data are moved right 12, originally another the effective AD data being in 23 ~ 12 are moved to low level, then step-by-step and operation is carried out with sexadecimal number 0xFFF, the new number obtained only will retain its low 12 effective informations, then assignment is to next number of data array X, completes all X with this
larray operates to the AD data separating of X array, just can obtain the data read from SRAM of X array 1024 actual needs.
In the process that whole transmission is resolved, the process of by-carriage null value and rejecting null value gibberish in the middle of existing, here the actual application being just illustrated the inventive method and the situation that may exist in applying, although have in every 8 read operations read for 2 times for gibberish, seem and waste the transmission time, but in real work, because the lasting reading capability of PXI bus is achieved, in fact total work efficiency improves greatly compared to art methods.
If front end SRAM data width K
1when expanding to 192 bit wide, then do not need the centre of carrying out gibberish again to supplement, actual transmissions efficiency will be higher.
In the present embodiment, PXI data bus only employs that it is low 24, and most-significant byte is not utilized, and this is also relevant with design, and the present embodiment just illustrates in practical application there is this situation, if high-speed AD sampling quantizes bit wide K
2when being 8, then the present embodiment then can reach maximization in PXI data transmission efficiency.
The repeatedly reading gating that method of the present invention directly carries out SRAM address space addressing decode and SRAM reading data by PXI bus address judges process, carry out in order to the mode realized by address decoding and address strobe synchro control, enormously simplify the Coordination Treatment process of multiple link in flow chart of data processing, the problem simultaneously matched with the ingenious SRAM of the solving operation rate of mode of address direct decoding addressing SRAM address space and PXI Bus Speed, avoids trouble and risk hidden danger that SRAM reads and writes clock separate design.The data section mode of a SRAM is read by the direct gating in PXI address, decrease fpga logic to realize, also can combine with SRAM addressing cleverly simultaneously, the wide mouth data of direct SRAM realizing PXI bus read continuously, data continuous read operation fast can be carried out in the mode of PXI Bulk transport or burst transfer, substantially increase speed and the efficiency of the reading of wide mouth SRAM data, shorten the time of host computer data processing, improve system performance.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (19)
1., based on the high-speed AD data PXI bus transfer analytic method that wide mouth SRAM stores, it is characterized in that, comprise the following steps:
Step (1): transmission resolving is read for the PXI bus stored in N high-speed AD sampled data in SRAM, first needs according to the total interface width K of SRAM data
1, high-speed AD sample quantization bit wide K
2, PXI bus data interface width K
3, SRAM address-bus width W
2determine the decoding of PXI address bus composition and PXI bus read from SRAM N high-speed AD sampled data the actual reading times NL that need carry out;
Step (2): after the actual times N L that need carry out read operation of PXI bus determines, then host computer main control unit is by PXI bus from the base address set, carries out traveling through peek continuously NL time, obtains NL K successively
3the data array X of bit wide
nL;
Step (3): judge data array X
nLwhether needing the rejecting process carrying out gibberish, is then to X
nLcarry out gibberish and reject process, and obtain N
5the SRAM new data array X that the individual PXI containing useful AD data reads
l; Otherwise by data array X
nLindirect assignment is to data array X
l;
Step (4): to data array X
lcarry out the separating treatment of AD data, obtain the N number of high-speed AD sampled data array X read from SRAM, X data are passed to next flow process and are carried out other signal analysis and processing, and return step (1), wait for the transmission dissection process of next group data.
2. a kind of high-speed AD data PXI bus transfer analytic method stored based on wide mouth SRAM as claimed in claim 1, it is characterized in that, in described step (1), described PXI address bus is decoded as and is made up of SRAM address space addressable address section and address strobe control address field;
Wherein, SRAM address space addressable address section is wide is W
2, decided by the address-bus width of SRAM device, in this section, address bus docks with SRAM address bus in FPGA; It is W that address strobe controls address field bit wide
1; The low W of PXI address bus
1-1 to 0 is defined as address strobe and controls address field, the W of PXI address bus
2+ W
1-1 to W
1position is defined as SRAM address space addressable address section.
3. a kind of high-speed AD data PXI bus transfer analytic method stored based on wide mouth SRAM as claimed in claim 2, it is characterized in that, described address strobe controls address field bit wide W
1defining method be: it need meet following relation:
Wherein, N
1be defined as the maximum number of the complete AD sampled data that SRAM read data packet contains, N
2be defined as a PXI bus and read the maximum complete AD sampled data number comprised of data;
Wherein,
value be set to N
3, represent SRAM read data transmitted by PXI bus needed for number of times; N
1%N
2value be set to N
4if, N
4be greater than 0, represent that the last AD data amount check read is less than N
2.
4. a kind of high-speed AD data PXI bus transfer analytic method stored based on wide mouth SRAM as claimed in claim 3, is characterized in that, the maximum number N of the complete AD sampled data that a described SRAM read data packet contains
1defining method be K
1with K
2the maximum positive integer value of ratio:
in a SRAM data reading, AD data arrange from low to high with sampling order.
5. a kind of high-speed AD data PXI bus transfer analytic method stored based on wide mouth SRAM as claimed in claim 4, is characterized in that, described N
1defining method in, work as K
1with K
2when ratio is integer, SRAM storage resources realizes the peak use rate that AD data store.
6. a kind of high-speed AD data PXI bus transfer analytic method stored based on wide mouth SRAM as claimed in claim 3, it is characterized in that, a described PXI bus reads the maximum complete AD sampled data number N comprised of data
2defining method be K
3with K
2the maximum positive integer value of ratio:
7. a kind of high-speed AD data PXI bus transfer analytic method stored based on wide mouth SRAM as claimed in claim 6, is characterized in that, described N
2defining method in, work as K
3with K
2when ratio is integer, PXI data bus interface realizes the peak use rate of AD data transmission.
8. a kind of high-speed AD data PXI bus transfer analytic method stored based on wide mouth SRAM as claimed in claim 3, is characterized in that, described W
1defining method in, work as N
3equal
time, address strobe controls the gating coding of address field to AD data and realizes peak use rate.
9. a kind of high-speed AD data PXI bus transfer analytic method stored based on wide mouth SRAM as claimed in claim 3, is characterized in that, described W
1defining method in, work as N
3equal
time, and N
4when equaling 0, PXI bus realizes the maximizing efficiency of AD data transmission.
10. a kind of high-speed AD data PXI bus transfer analytic method stored based on wide mouth SRAM as claimed in claim 1, it is characterized in that, in described step (1), described PXI bus read from SRAM N high-speed AD sampled data the defining method of the actual reading times NL that need carry out be:
Wherein,
value be set to N
5, for calculating the PXI number of operations needed for N AD sampled data reading,
n is greater than because address strobe controls address field coded number for calculating during N AD sampled data reads continuously
3time need the number of operations of PXI bus gibberish that do more.
11. a kind of high-speed AD data PXI bus transfer analytic methods stored based on wide mouth SRAM as claimed in claim 1, is characterized in that, in described step (2), described NL time continuously traversal peek operate, comprise the following steps:
Step (21): set the count number of traversal peek continuously as I, initialization value is 0;
Step (22): be added by PXI bus base address and count number I and obtain PXI bus address, PXI bus initiates reading request;
Step (23): FPGA is after receiving reading request, according to SRAM address space addressable address, SRAM is peeked, then control address according to address strobe to judge, and give PXI data bus by the AD data of gating corresponding in current SRAM data;
Step (24): main control unit receives data bus K
3the data of bit wide, and assignment is to data array X
nLwith the numerical value of I index, count number I adds 1;
Step (25): judge whether count number I equals NL, is, represents that NL peek is complete, waits pending AD Data Analysis flow process, otherwise return step (22).
12. a kind of high-speed AD data PXI bus transfer analytic methods stored based on wide mouth SRAM as claimed in claim 11, it is characterized in that, in described step (23), described control address according to address strobe and carry out judging and the disposal route that the AD data current SRAM being read corresponding gating in data give PXI data bus is:
Meter W
1it is E that the gating of bit wide controls address bit values, as E < N
3when-1, by E × N that SRAM institute read data comprises
2to (E+1) × N
2-1 AD data with the common assignment of a definite sequence to PXI data bus; As E==(N
3-1) time, as N
4equal 0, then by E × N that SRAM institute read data comprises
2to (E+1) × N
2-1 AD data with the common assignment of a definite sequence to PXI data bus, if N
4be not equal to 0, then by E × N that SRAM institute read data comprises
2to E × N
2+ N
4-1 AD data with the common assignment of a definite sequence to PXI data bus; If
send 0 process then to PXI bus data.
13. a kind of high-speed AD data PXI bus transfer analytic methods stored based on wide mouth SRAM as claimed in claim 12, it is characterized in that, described AD data with the common assignment of a definite sequence to the assignment method of PXI data bus are: E × N
2individual AD data assignment is to the K of PXI data bus
2-1 to the 0th, E × N
2+ 1 AD data assignment is to the 2nd × K of PXI data bus
2-1 to K
2position, the rest may be inferred, (E+1) × N
2-1 AD data assignment is to the N of PXI data bus
2× K
2-1 to (N
2-1) × K
2position, if PXI data bus N
2× K
2position and position of also having a surplus above, then remaining position zero padding process or do not process; If N
4be not equal to 0, then when E equals (N
3-1) time, the complete E × N of assignment
2+ N
4after-1 AD data, the high-order zero padding process of the residue of PXI data bus or do not process.
14. a kind of high-speed AD data PXI bus transfer analytic methods stored based on wide mouth SRAM as claimed in claim 12, is characterized in that,
Described W
1the defining method of the gating control address bit values E of bit wide is:
wherein subscript H represents the binary value under the corresponding positions of gating address.
15. a kind of high-speed AD data PXI bus transfer analytic methods stored based on wide mouth SRAM as claimed in claim 1, is characterized in that, in described step (3), described whether carry out gibberish reject process according to being: N
3whether equal
that W is described
1just in time with one time, the address SRAM that the address strobe of bit wide controls address field coding gating read data transmitted by PXI bus needed for number of times match, without the need to carrying out the transmission operation of zero padding gibberish; If
continuous transmission work in order to realize PXI bus is then described, centre needs to carry out
the gibberish transmission operation of number of times.
16. a kind of high-speed AD data PXI bus transfer analytic methods stored based on wide mouth SRAM as claimed in claim 1, is characterized in that, in described step (3), described to X
nLcarry out the process that gibberish rejects process, comprise the following steps:
Step (31): establish data array X
nLthe count number of operation is J
1, to new data array X
lthe count number of operation is J
2, J
1and J
2equal initialization value is 0;
Step (32): judge J
1with
whether the remainder of complementation is more than or equal to N
3, be enter step (33); Otherwise enter step (34);
Step (33): J
1add 1, enter step (35);
Step (34): by array X
nLwith J
1the data assignment of index is to array X
lwith J
2the data of index, J
1add 1, J
2add 1, enter step (35);
Step (35): judge J
1whether be less than NL, be, return step (32), otherwise represent that gibberish has been rejected complete, wait the separating treatment of pending AD data.
17. a kind of high-speed AD data PXI bus transfer analytic methods stored based on wide mouth SRAM as claimed in claim 1, is characterized in that, in described step (4), described to data array X
lcarry out the separating treatment process of AD data, comprise the following steps:
Step (41): establish data array X
lthe count number of operation is R
1, the count number operated final AD data array X is R
2, R
3for being separated count number, R
1, R
2and R
3equal initialization value is 0, and sets θ as K
2bit wide every is the binary number of 1 entirely;
Step (42): by array X
lwith R
1the data assignment of index is K to bit wide
3service data δ, and judge R
1with N
3whether the remainder of complementation equals N
3-1, be enter step (43); Otherwise enter step (44);
Step (43): judge N
4whether equal 0, be, enter step (44); Otherwise enter step (47);
Step (44): δ and θ is carried out step-by-step with operation obtain only retain its low K
2the new data assignment of bit data to array X with R
2the data of index, R
2add 1, R
3add 1, enter step (45);
Step (45): judge R
3whether equal N
2, be then R
3assignment 0, R
1add 1, then proceed to step (410); Otherwise enter step (46);
Step (46): by δ to the right according to K
2position, then carry out with θ step-by-step with operation obtain only retain its low K
2the new data assignment of bit data to array X with R
2the data of index, R
2add 1, R
3add 1, then return step (45);
Step (47): δ and θ is carried out step-by-step with operation obtain only retain its low K
2the new data assignment of bit data to array X with R
2the data of index, R
2add 1, R
3add 1, enter step (48);
Step (48): judge R
3whether equal N
4, be then R
3assignment 0, R
1add 1, then proceed to step (410); Otherwise enter step (49);
Step (49): by δ to the right according to K
2position, then carry out with θ step-by-step with operation obtain only retain its low K
2the new data assignment of bit data to array X with R
2the data of index, R
2add 1, R
3add 1, then return step (48);
Step (410): judge R
1whether be less than N
5, be return step (42), otherwise represent that the separating treatment work of N number of AD data completes.
18. a kind of high-speed AD data PXI bus transfer analytic methods stored based on wide mouth SRAM as claimed in claim 1, it is characterized in that, described PXI address bus, the bus data variable quantity of its address increment counts K
3, for the situation of carrying out incremental computations with byte, need by
bit wide is as lowest order address increment, and other corresponding address fields are to moving to left
position.
19. a kind of high-speed AD data PXI bus transfer analytic methods stored based on wide mouth SRAM as claimed in claim 11, is characterized in that, carry out the timing really of PXI bus address, for the situation taking byte as increment, and need with count number
calculate as address change.
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