CN102468902B - Method for Turbo coding of rate match/de-rate match in LTE (long term evolution) system - Google Patents
Method for Turbo coding of rate match/de-rate match in LTE (long term evolution) system Download PDFInfo
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Abstract
The invention provides a method for Turbo coding of rate match/de-rate match in an LTE (long term evolution) system. The method comprises the following steps of: confirming an interweaving mode according to the date length K of a code block; obtaining a system matrix according to a system bit stream, wherein a first check bit stream P1 and a second check bit stream P2 are alternately stored to obtain a check matrix, every eight lines from a first line of the system matrix is taken as a subsystem matrix, and every eight lines from a first line of the check matrix is taken as a subsystem check matrix; confirming a system matrix address and a check matrix address; putting the system bit stream in the address after the data is packed, and putting the check bit stream into the check matrix address after the data is packed; and outputting the data in the system matrix address and the check matrix address according to lines, so that the bit stream after the rate match/de-rate match can be obtained. After the method is used, the speed of rate match/de-rate match can be accelerated.
Description
Technical field
The present invention relates to communication technical field, more specifically, relate to the method for LTE system Turbo code rate coupling/rate de-matching.
Background technology
Long Term Evolution (LTE) is the Long Term Evolution of the 3G communication technology, and for following wireless communication system provides higher transmission rate, its code check has at a high speed brought white elephant to the Base-Band Processing of base station and terminal.For the Base-Band Processing in LTE technology, how to accelerate the data processing speed of bit-level, especially the rate-matched processing speed of transmission channel is one of bottleneck of whole Base-Band Processing.
The transmission channel rate-matched process of existing Turbo coding as shown in Figure 1.The original bit stream of transmitting terminal obtains systematic bits stream after Turbo coding
the first check bit stream
the second check bit stream
amount to three circuit-switched data.
with
the length of three road bit streams is identical, and the length of bit stream equals K+4, and K is the data length of encoding block, and the 4th, tail bit.Tail bit is through the Turbo remaining bit of encoding.
with
three road bit streams are inputted respectively sub-block interleaver, and to send into a R capable for bit stream, in the matrixes of 32 row, write line by line, then displacement between being listed as, then read line by line obtain respectively with
corresponding output bit flow
with
corresponding output bit flow
with
corresponding output bit flow
enter bit collection module.In bit collection module, the mode of collection is that systematic bits flows front, and the first check bit stream is alternately deposited with the second check bit stream, forms a complete bit stream w
k.Again according to the length of the original position of rate-matched and rate-matched output, cutting or repeat peek, until meet output length requirement output bit flow e
kto terminal.
According to above-mentioned overall flow analysis, do not need systematic bits stream by the time
the first check bit stream
the second check bit stream
arrive and just start rate adaptation operating simultaneously, but will after each bit stream coding of encoding after Turbo, carry out respectively rate-matched.Owing to need to repeatedly reading the data in bit stream in internal memory, therefore the processing speed of above-mentioned rate-matched is lower.
Summary of the invention
The embodiment of the present invention proposes the method for Turbo code rate coupling/rate de-matching in a kind of LTE system, can accelerate the speed of rate-matched/rate de-matching.
A method for Turbo code rate coupling/rate de-matching in LTE system, the method comprises:
According to the data length K of encoding block, determine interlace mode;
By systematic bits stream, obtain sytem matrix, the first check bit stream P1 and the second check bit stream P2 alternately deposit and obtain check matrix, from the 1st row beginning every 8 of sytem matrix, classify a sub-sytem matrix as, from the 1st row beginning every 8 of check matrix, classify a sub-check matrix as;
From N=1, start and increase progressively by 1, until N=8, after extracting successively the N row of each subsystem matrix, according to interlace mode, calculate the sytem matrix address that this column data is corresponding, from N=1, start and increase progressively by 1, until N=8, according to interlace mode, calculate the check matrix address that this column data is corresponding after extracting successively the N row of every sub-check matrix;
In each extraction, after the word packing of selecting 4 systematic bits to flow, according to pre-defined rule, be placed in described sytem matrix address, after selecting the word of 4 P1 and the word of 4 P2 to pack, according to pre-defined rule, be placed in the address of described check matrix, this selection comprises S circulation, after the line number R that S equals subsystem matrix subtracts 1, divided by 4, round downwards, R equals after K adds 4 to round up divided by 32;
Press in row output system matrix address and check matrix address in data, obtain the bit stream after rate-matched/rate de-matching.
The described data length K according to encoding block determines that interlace mode comprises, K, to 32 remainder numbers, determines interlace mode by described remainder.
After the described N that extracts successively each subsystem matrix is listed as, according to interlace mode, calculating the sytem matrix address that this column data is corresponding comprises, according to interlace mode, determine interleaving index, in the N row that are offset successively each subsystem matrix by interleaving index, the address of each data obtains the middle offset address that this is listed as each data, then obtains sytem matrix address according to middle offset address described in interlace mode and N overall offset;
After the described N that extracts successively every sub-check matrix is listed as, according to interlace mode, calculating the check matrix address that this column data is corresponding comprises, according to interlace mode, determine interleaving index, in the N row that are offset successively every sub-check matrix by interleaving index, the address of each data obtains the middle offset address that this is listed as each data, then obtains check matrix address according to middle offset address described in interlace mode and N overall offset.
In the described N row that are offset successively each subsystem matrix by interleaving index, the address of each data obtains further comprising before middle offset address, the initial column position of computing system matrix, and the original position of sytem matrix equals k
0,
n
cbfor the soft Buffer size of rate-matched, RV is redundancy version parameters.
Work as k
0be greater than 32, the initial column position of sytem matrix equals k '
0,
Describedly according to offset address in the middle of described in interlace mode and N overall offset, obtain sytem matrix address and comprise, according to interlace mode and N, determine overall offset amount, then according to offset address in the middle of described in overall offset amount overall offset, obtain sytem matrix address;
Describedly according to offset address in the middle of described in interlace mode and N overall offset, obtain check matrix address and comprise, according to interlace mode and N, determine overall offset amount, then according to offset address in the middle of described in overall offset amount overall offset, obtain check matrix address.
Describedly according to interlace mode and N, determine that overall offset amount comprises, by interlace mode, determine filling bit, overall offset amount H equal 32 deduct after filling bit with N the data of P1 and.
Describedly according to interlace mode and N, determine that overall offset amount comprises, by interlace mode, determine unnecessary bit, overall offset amount H equals the poor of N data of P1 and filling bit.
After the word packing of 4 systematic bits streams of described selection, according to pre-defined rule, be placed in described sytem matrix address and comprise,
Since the 0th system word, every 8 words, take out the word of bit stream, obtain the first system word, second system word, the 3rd system word and Quaternary system system word; The maximum data of getting respectively described four systems word forms the first system output word, and inferior high data form second system output word, and inferior low data form the 3rd system output word, and minimum data forms Quaternary system system output word;
Described the first system output word is positioned in the address of 4 data of capable the 1st data to the of described sytem matrix S, described second system output word is positioned in the address of 12 data of capable the 9th data to the of described sytem matrix S, described the 3rd system output word is positioned in the address of 8 data of capable the 5th data to the of described sytem matrix S, described Quaternary system system output word is positioned in the address of 16 data of capable the 13rd data to the of described sytem matrix S.
The address that is placed in described check matrix according to pre-defined rule after the packing of the word of 4 P1 of described selection and the word of 4 P2 comprises,
Order is taken out the 0th word and the 8th word from P1, is designated as successively the first check word and the second check word, and order is taken out the 1st word and the 9th word from P2, is designated as successively the 3rd check word and the 4th check word;
The maximum data of getting respectively the first check word to the four check words forms the first verification output word, and inferior high data form the second verification output word, and inferior low data form the 3rd verification output word, and minimum data forms the 4th verification output word;
Described the first verification output word is positioned in the address of 4 data of capable the 1st data to the of described check matrix S, described the second verification output word is positioned in the address of 12 data of capable the 9th data to the of described check matrix S, described the 3rd verification output word is positioned in the address of 8 data of capable the 5th data to the of described check matrix S, described the 4th verification output word is positioned in the address of 16 data of capable the 13rd data to the of described check matrix S;
Then, then order is from P1 the 16th word of taking-up and the 24th word, is designated as successively the 5th check word and the 6th check word, and order is taken out the 17th data and the 25th data from P2, is designated as successively the 7th check word and the 8th check word;
The maximum data of getting respectively the 5th check word to the eight check words forms the 5th verification output word, and inferior high data form the 6th verification output word, and inferior low data form the 7th verification output word, and minimum data forms the 8th verification output word;
Described the 5th verification output word is positioned in the address of 4 data of capable the 1st data to the of described check matrix S+1, described the 6th verification output word is positioned in the address of 12 data of capable the 9th data to the of described check matrix S+1, described the 7th verification output word is positioned in the address of 8 data of capable the 5th data to the of described check matrix S+1, described the 8th verification output word is positioned in the address of 16 data of capable the 13rd data to the of described check matrix S+1.
While there is remaining data after S circulation, get a remaining data at every turn and be positioned in the address of described remaining data.
When N equals 8, further comprise, according to the unnecessary bit of interlace mode fill system data, according to interlace mode, fill the unnecessary bit of checking data.
From technique scheme, can find out, in embodiments of the present invention, first according to the data length of encoding block, determine interlace mode, then sytem matrix is divided into subsystem matrix and check matrix is divided into sub-check matrix; According to interlace mode, press column count sytem matrix address and check matrix address, the systematic bits stream packing of every four words is positioned in sytem matrix address, the P2 packing of the P1 of every four words and every four words is positioned in the address of check matrix, by row output system matrix and check matrix.Data placement after packing, in corresponding address, is conducive to the water operation of processor, thereby can accelerates the speed of rate-matched.Identical technical scheme also can be applied in rate de-matching, thereby can accelerate the speed of rate de-matching.
Accompanying drawing explanation
Fig. 1 is the rate-matched schematic diagram of Turbo coding in prior art;
Fig. 2 is the method flow schematic diagram of Turbo code rate coupling in LTE system of the present invention;
Fig. 3 is the schematic diagram of interlace mode 1 in the embodiment of the present invention;
Fig. 4 is the schematic diagram of interlace mode 2 in the embodiment of the present invention;
Fig. 5 is the schematic diagram of interlace mode 3 in the embodiment of the present invention;
Fig. 6 is the schematic diagram of interlace mode 4 in the embodiment of the present invention;
Fig. 7 is embodiment of the present invention input data storage schematic diagram;
Fig. 8 is data packing operation chart in the embodiment of the present invention.
Embodiment
For making the object, technical solutions and advantages of the present invention express clearlyer, below in conjunction with drawings and the specific embodiments, the present invention is further described in more detail.
In embodiments of the present invention, systematic bits stream, the first check bit stream (P1) and the second check bit stream (P2) parallel processing simultaneously, and the data read-write operation of continuous 4 words constructs and is applicable to the data access structure that main flow processor is realized packing data operation, and has reduced the read-write number of times to internal memory.Processing mode is simple, and loop structure is clear, does not exist judgement redirect etc. to interrupt the operation of streamline, processor calculatings of can fetching data faster, and the data after bundle block interleaving map directly on outgoing position, and then the speed of quickening rate-matched.
In the present invention, Turbo code rate coupling comprises the following steps A to E:
Steps A, according to the data length K of encoding block, determine interlace mode.
Step B, by systematic bits stream, obtain sytem matrix, P1 and P2 alternately deposit and obtain check matrix, start every 8 classify a sub-sytem matrix as from the 1st row of sytem matrix, start every 8 classify a sub-check matrix as from the 1st row of check matrix.
P1 and P2 alternately deposit that to obtain the implementation of check matrix and prior art identical, do not repeat them here.Sytem matrix is totally 32 row, four sub-sytem matrixes, consists of; Check matrix is totally 32 row, and same consists of four sub-check matrixes.
Step C, according to interlace mode, calculate the sytem matrix address that this column data is corresponding after extracting successively the N row of each subsystem matrix, according to interlace mode, calculate the check matrix address that this column data is corresponding after extracting successively the N row of every sub-check matrix.
Each N row that extract subsystem matrix, the N row of sub-check matrix, until complete 8 circulations, with the data address in computing system matrix and the data address in check matrix.When N is less than 8 N+1 row that continue to extract each submatrix, the initial value of N is 1.
The word packing of step D, 4 systematic bits streams of selection is placed in described sytem matrix address, select the word of 4 P1 and the packing of the word of 4 P2 to be placed in the address of described check matrix, described selection comprises S circulation, the line number R that S equals submatrix subtracts 1 and rounds downwards divided by 4, and R equals after K adds 4 to round up divided by 32.
The data packing of systematic bits stream is processed and is positioned in the data address of sytem matrix; The data packing of P1 and P2 is processed and is positioned in the data address of check matrix.Each word comprises 4 data, in technical scheme of the present invention, selects four words to select 16 data.
Step e, press the data in row output system matrix address and in check matrix address, obtain the bit stream after rate-matched.
Referring to accompanying drawing 2, are method flow schematic diagrames of Turbo code rate coupling in LTE system, specifically comprise the following steps:
Because sub-block interleaver matrix is fixed as 32 row, according to the data length K of encoding block, to 32 remainder numbers, it is 0,8,16 and 24 that remainder has four kinds of situations, is directed to different remainders and need to fills different bits.Remainder is that 0 this encoding block belongs to interlace mode 1; Remainder is that 8 these encoding blocks belong to interlace mode 2; Remainder is that 16 these encoding blocks belong to interlace mode 3; Remainder is that 24 these encoding blocks belong to interlace mode 4.4 kinds of interlace modes have determined the side-play amount of matrix data address
LTE has stipulated 188 kinds of fixing encoding block length, below these 188 kinds of encoding block length is analyzed:
Step-length is that 8 encoding block length amounts to 60 kinds:
40，48，56，64，72，80，88，96，104，112，120，128，136，144，152，160，168，176，184，192，200，208，216，224，232，240，248，256，264，272，280，288，296，304，312，320，328，336，344，352，360，368，376，384，392，400，408，416，424，432，440，448，456，464，472，480，488，496，504，512。
Step-length is that 16 encoding block length amounts to 32 kinds
528，544，560，576，592，608，624，640，656，672，688，704，720，736，752，768，784，800，816，832，848，864，880，896，912，928，944，960，976，992，1008，1024。
Step-length is that 32 encoding block length amounts to 32 kinds
1056，1088，1120，1152，1184，1216，1248，1280，1312，1344，1376，1408，1440，1472，1504，1536，1568，1600，1632，1664，1696，1728，1760，1792，1824，1856，1888，1920，1952，1984，2016，2048。
Step-length is that 64 encoding block length amounts to 64 kinds
2112，2176，2240，2304，2368，2432，2496，2560，2624，2688，2752，2816，2880，2944，3008，3072，3136，3200，3264，3328，3392，3456，3520，3584，3648，3712，3776，3840，3904，3968，4032，4096，4160，4224，4288，4352，4416，4480，4544，4608，4672，4736，4800，4864，4928，4992，5056，5120，5184，5248，5312，5376，5440，5504，5568，5632，5696，5760，5824，5888，5952，6016，6080，6144。
Wherein, for step-length, be 32 and 64 encoding block, K is 0 to 32 remainder numbers, all meets the requirement of interlace mode 1; Step-length is 16 encoding block, and 528 meet interlace mode 3,544 meets interlace mode 1, replaces successively; Step-length is that in 8 encoding block, the existing encoding block that meets interlace mode 3 also has the encoding block that meets interlace mode 1.
Above-mentioned encoding block obtains interlace mode under each encoding block to 32 remainders.
The encoding block length of interlace mode 1 correspondence: amount to 127 kinds
64，96，128，160，192，224，256，288，320，352，384，416，448，480，512，544，576，608，640，672，704，736，768，800，832，864，896，928，960，992，1024，1056，1088，1120，1152，1184，1216，1248，1280，1312，1344，1376，1408，1440，1472，1504，1536，1568，1600，1632，1664，1696，1728，1760，1792，1824，1856，1888，1920，1952，1984，2016，2048，2112，2176，2240，2304，2368，2432，2496，2560，2624，2688，2752，2816，2880，2944，3008，3072，3136，3200，3264，3328，3392，3456，3520，3584，3648，3712，3776，3840，3904，3968，4032，4096，4160，4224，4288，4352，4416，4480，4544，4608，4672，4736，4800，4864，4928，4992，5056，5120，5184，5248，5312，5376，5440，5504，5568，5632，5696，5760，5824，5888，5952，6016，6080，6144。
The encoding block length of interlace mode 2 correspondences: amount to 15 kinds
40，72，104，136，168，200，232，264，296，328，360，392，424，456，488。
The encoding block length of interlace mode 3 correspondences: amount to 31 kinds
48，80，112，144，176，208，240，272，304，336，368，400，432，464，496；
528，560，592，624，656，688，720，752，784，816，848，880，912，944，976，1008。
The encoding block length of interlace mode 4 correspondences: amount to 15 kinds
56，88，120，152，184，216，248，280，312，344，376，408，440，472，504。
Systematic bits stream forms four sub-sytem matrixes successively, and each subsystem matrix is totally 8 row, and front 7 row are often shown R data, and the 8th shows R-1 data; Check bit stream forms four sub-check matrixes successively, and every sub-check matrix 8 is listed as totally, and front 7 row are often shown 2 (R-1) individual data, and the 8th shows 2R data.Because check matrix is alternately deposited acquisition by P1 and P2, so in check matrix, the length of every column data is longer than the length of the every column data of sytem matrix.
Under regard to every kind of interlace mode and illustrate:
Interlace mode 1: corresponding filling bit N
d=28, the encoding block length in the length of bit stream can be by 32 situations about dividing exactly.Example K=6144, referring to accompanying drawing 3.
The shorter length correspondence system matrix of front 32 row, the corresponding check matrix of length that rear 32 row are longer.Systematic bits consists of four sub-sytem matrixes successively, and its short-and-medium rectangular strip is that length is R-1 not containing the row of unnecessary bit, and long rectangular strip is the row containing unnecessary bit, and length is R.Unnecessary bit is in interleaver matrix, not meet the unnecessary bit of row length.Check bit consists of four sub-check matrixes successively, and its short-and-medium rectangular strip is that length is 2 (R-1) not containing the row of unnecessary bit, and long rectangular strip is the row containing unnecessary bit, and length is 2R.
Interlace mode 2: corresponding N
d=20, the situation that the encoding block length in the length of bit stream is 8 to 32 remainders.Example K=488, referring to accompanying drawing 4.
Interlace mode 3: corresponding N
d=12, the situation that the encoding block length in the length of bit stream is 16 to 32 remainders.Example K=496, referring to accompanying drawing 5.
Interlace mode 4: corresponding N
d=4, the situation that the encoding block length in the length of bit stream is 32 to 32 remainders.Example K=504, referring to accompanying drawing 6.
Be similar to interlace mode 1, interlace mode 2,3,4 is the different of K from interlace mode 1 difference, and its sytem matrix is different from the corresponding row length of check matrix.
After extracting successively the N row of each subsystem matrix, according to interlace mode, calculate the sytem matrix address that this column data is corresponding, according to interlace mode, calculate the check matrix address that this column data is corresponding after extracting successively the N row of every sub-check matrix.
Each subsystem matrix is totally 8 row, and a column data address of each subsystem matrix of cycle calculations is carried out altogether eight circulations and just can be calculated all sytem matrixes address; Accordingly, every sub-check matrix is also 8 row, and a column data address of every sub-check matrix of a cycle calculations is carried out altogether eight circulations and just can be calculated all check matrixes address.Therefore the initial value of N is 1, and the maximum of N is 8.
Step 2031, calculating interleaving index.
Interleaving index is according to the list of the side-play amount of each data address in the determined matrix of interlace mode.For different interlace modes, calculate the side-play amount of each data address in every kind of interlace mode, in corresponding sytem matrix each data address increase corresponding side-play amount obtain in the middle of offset address, then according to the middle offset address of interlace mode and each data of N overall offset, obtain sytem matrix address; In check matrix each data address increase corresponding side-play amount obtain in the middle of offset address, then according to the middle offset address of interlace mode and each data of N overall offset, obtain check matrix address.
Describe the calculating of interleaving index below in detail:
First according to redundancy version parameters RV and the soft Buffer N of rate-matched
cbsize, and the formula of LTE protocol description calculates initial row k
0:
In above formula, R is the line number of subsystem matrix, N
cbfor the soft Buffer size of rate-matched, RV is redundancy version parameters, scope: 0,1,2,3.Wherein, N
cbfor known parameters, RV is known parameters.
In addition, due to the particularity of matrix spread pattern, if k
0be greater than 32, the initial column position of sytem matrix equals k '
0:
Formula (2) has guaranteed k '
0span be 2 to 53.Because check matrix is that P1 and P2 combine, if the every column data number of check matrix is identical with the every column data of sytem matrix, check matrix should be 64 row.And for LTE system, P1 and P2 calculate separately, check matrix 96 is listed as totally.If calculated according to former formula (1), k
0span be 2 to 74.After calculating by formula (2), be equivalent to original corresponding columns to be converted to the columns at check matrix place.For example be originally 74 row, be at the 53rd row after formula (2) calculates.
The initial column position of sytem matrix calculates respectively interleaving index according to four kinds of interlace modes after determining.
To the length assignment of each row, be the length of each row of initialization, assignment may be R, R-1 or 2R, and 2 (R-1) amount to four kinds may.
The output index value of the beginning position of K row is that the output index value of the beginning position of 0, the K+1 row is the length that the output index value of K row beginning position adds K row, by that analogy.Therefore especially, due to RV parameter, after the 0th row can be put into all the time, the output index value of the beginning position of the 0th row is the length that the output index value of the beginning position of the 63rd row adds the 63rd row.
In addition, also need to calculate the OPADD index of unnecessary bit, for sytem matrix, owing to only there being the unnecessary bit of 1 bit, the OPADD index that the OPADD of unnecessary bit is equivalent to the next column of this unnecessary bit column subtracts 1; For check matrix, owing to there being the unnecessary bit of 2 bits, the OPADD index that the OPADD of unnecessary bit is equivalent to the next column of this unnecessary bit column subtracts 2.
In conjunction with the number of filling bit, can obtain the feature of following 4 kinds of interlace modes.
<4，20，12，28，8，24，16，0，6，22，14，30，10，26，18，2，5，21，13，29，9，25，17，1，7，23，15，31，11，27，19，3>
When systematic bits stream and P1 get the 31st element, the 59th in Fig. 3 matrix is listed as, and P2 gets the 0th element.The saltus step of having fetched data this time, therefore, in order to construct special structure, the initial address of the output of 59 to 64 row in the matrix of our definition row need to be offset to 1 unit successively backward, the unnecessary bit initial address of respective column is offset to 1 unit backward simultaneously.
<12，28，20，4，16，0，24，8，14，30，22，6，18，2，26，10，13，29，21，5，17，1，25，9，15，31，23，7，19，3，27，11>
When systematic bits stream and P1 get the 31st element, the 57th in Fig. 4 matrix is listed as, and P2 gets the 0th element.The saltus step of having fetched data this time, therefore, in order to construct special structure, the initial address of the output of 57 to 64 row in the matrix of our definition row need to be offset to 1 unit successively backward, the unnecessary bit initial address of respective column is offset to 1 unit backward simultaneously.
<20，4，28，12，24，8，0，16，22，6，30，14，26，10，2，18，21，5，29，13，25，9，1，17，23，7，31，15，27，11，3，19>
When systematic bits stream and P1 get the 31st element, the 58th in Fig. 5 matrix is listed as, and P2 gets the 0th element.The saltus step of having fetched data this time, therefore, in order to construct special structure, the initial address of the output of 58 to 64 row in the matrix of our definition row need to be offset to 1 unit successively backward, the unnecessary bit initial address of respective column is offset to 1 unit backward simultaneously.
<28，12，4，20，0，16，8，24，30，14，6，22，2，18，10，26，29，13，5，21，1，17，9，25，31，15，7，23，3，19，11，27>
When systematic bits stream and P1 get the 31st element, the 56th in matrix is listed as, and P2 gets the 0th element.The saltus step of now having fetched data, therefore, in order to construct special structure, need to be offset 1 unit to the initial address of 64 row output row by 56 in matrix successively backward, the unnecessary bit initial address of respective column is offset to 1 unit backward simultaneously.
The size of interleaving index is 64+56=120 length.Front 64 index storage system matrixes, 32 row, check matrix 32 row amount to the initial address index of 64 row, the i.e. position of the bit of beginning in output buffer memory; Rear 56 index are the unnecessary bit of each special length row positions in output buffer memory.Due to check matrix containing two unnecessary bits in the long line of unnecessary bit, be close-connected, therefore only need to calculate an allocation index, the address of the unnecessary bit of another one can add according to this allocation index
The sytem matrix of interlace mode 1 and check matrix have respectively in the end a line of 4 unnecessary bits, why are that last column is that filling bit NULL has been put into last column here, are therefore called unnecessary bit, only need the index of 8 unnecessary bits.Similarly, interlace mode 2 needs the index of 24 remaining bits.Interlace mode 3 needs the index of 40 remaining bits, and interlace mode 4 needs the index of 56 remaining bits.According to interlace mode 4, getting maximum length is 56, above-mentioned 120 index altogether.These 120 allocation indexs, have determined the side-play amount that output data are stored.
Precalculated above-mentioned indexing parameter before rate-matched.Because LTE system exists the identical situation of length of a plurality of encoding blocks, so only need to calculate interleaving index one time for identical encoding block.
Step 2032, according to offset address in the middle of interlace mode and N overall offset, obtain respectively sytem matrix address and check matrix address.
Because the block interleaver matrix in sub-block interleaver has 32 row, the filling bit of encoding block equals 32 and deducts K+4 to 32 remainders.The length of systematic bits stream, P1 and P2 is equal to K+4.That is: the filling bit N of interlace mode 1 correspondence
dequal 28; The N of interlace mode 2 correspondences
dequal 20; The N of interlace mode 3 correspondences
dequal 12; The N of interlace mode 4 correspondences
dequal 4.
According to N
dthe first eight data of the interlace mode of P 1 in associative list one, can obtain the overall offset amount of four kinds of each column datas of interlace mode.Deduct N when 32
dafter, with N data of P1 and be less than or equal to 32, overall offset amount H equals 32 and deducts N
dafterwards with N data of P1 and; Deduct N when 32
dafter, with N the data of P1 and be greater than 32, N the data that overall offset amount H equals P1 deduct N
d.
Table 1 P1 check matrix interlace mode
<0，16，8，24，4，20，12，28，2，18，10，26，6，22，14，30，1，17，9，25，5，21，13，29，3，19，11，27，7，23，15，31>
Interlace mode 1:N
dthe H of=28 corresponding each row is respectively: 4,20,12,28,8,24,16,0;
Interlace mode 2:N
dthe H of=20 corresponding each row is respectively: 12,28,20,4,16,0,24,8;
Interlace mode 3:N
dthe H of=12 corresponding each row is respectively: 20,4,28,12,24,8,0,16;
Interlace mode 4:N
dthe H of=4 corresponding each row is respectively: 28,12,4,20,0,16,8,24.
For the encoding block of interlace mode 1, the overall offset amount of the first row of its subsystem matrix and sub-check matrix is 4, and the overall offset amount of secondary series is 20, can obtain by that analogy the 3rd row to the overall offset amount of the 8th row.Overall offset amount herein refers to the side-play amount of the address of this column data.
The data of step 204, S packaging system bit stream of circulation, the data of packing P1 and P2.
In step 203, calculated address corresponding to data in sytem matrix and check matrix.In step 204, the data packing of systematic bits stream is positioned over to the address in sytem matrix; The data packing of P1 and P2 is positioned over to the address in check matrix.The line number R that cycle-index S equals subsystem matrix subtracts 1 and rounds downwards divided by 4, and R equals after K adds 4 to round up divided by 32.
If there is remaining data after S circulation, get a remaining data and be positioned in the address of remaining data at every turn.
For the input data of systematic bits stream, P1 and P2 depositing as shown in Figure 7 of totally three code streams.First character in systematic bits stream is by data S
0, data S
1, data S
2with data S
3form, the first character of P1 is by data P
0, data P
1, data P
2with data P
3form, and the first character of P2 is only by the data B in the 4th position
0form.If the input data of systematic bits stream, P1 and P2 do not meet above-mentioned condition, need the bit stream not satisfying condition to adjust to above-mentioned condition.Adjustment mode is prior art, at this, just repeats no more.
Below introduce in detail the word packing of systematic bits stream be positioned over to the address in sytem matrix.
Since the 0th word, every the word of 8 word extraction system bit streams, obtain the first system word A0, second system word A8, the 3rd system word A16 and Quaternary system system word A24.Referring to accompanying drawing 8, the maximum data of getting respectively four systems word forms the first system output word B0, and inferior high data form second system output word B8, and inferior low data form the 3rd system output word B16, and minimum data forms Quaternary system system output word B16.Said process is data packing process.Wherein, a word is to consist of four data.
B0 is positioned in the address of 4 data of capable the 1st data to the of sytem matrix S, B8 is positioned in the address of 12 data of capable the 9th data to the of sytem matrix S, B16 is positioned in the address of 8 data of capable the 5th data to the of sytem matrix S, B24 is positioned in 16 data of the 13rd data to the of capable the 4th row of sytem matrix S.
Carry out after S circulation, the word in systematic bits stream is positioned over respectively in the address in sytem matrix.
The data packing of P1 and P2 is positioned over to the address in check matrix, be with the data packing difference to sytem matrix, because the data number in check matrix is the twice of data number in sytem matrix, therefore sytem matrix carries out a secondary data packing, and corresponding check matrix carries out secondary data packing.
Order is taken out the 0th word and the 8th word from P1, is designated as successively the first check word and the second check word, and order is taken out the 1st word and the 9th word from P2, is designated as successively the 3rd check word and the 4th check word.
The maximum data of getting respectively the first check word to the four check words forms the first verification output word, and inferior high data form the second verification output word, and inferior low data form the 3rd verification output word, and minimum data forms the 4th verification output word.
The first verification output word is positioned in the address of 4 data of capable the 1st data to the of check matrix S, the second verification output word is positioned in the address of 12 data of capable the 9th data to the of check matrix S, the 3rd verification output word is positioned in the address of 8 data of capable the 5th data to the of check matrix S, the 4th verification output word is positioned in the address of 16 data of capable the 13rd data to the of described check matrix S.
Then, then order is from P1 the 16th word of taking-up and the 24th word, is designated as successively the 5th check word and the 6th check word, and order is taken out the 17th word and the 25th word from P2, is designated as successively the 7th check word and the 8th check word.
The maximum data of getting respectively the 5th check word to the eight check words forms the 5th verification output word, and inferior high data form the 6th verification output word, and inferior low data form the 7th verification output word, and minimum data forms the 8th verification output word.
The 5th verification output word is positioned in the address of 4 data of capable the 1st data to the of check matrix S+1, the 6th verification output word is positioned in the address of 12 data of capable the 9th data to the of check matrix S+1, the 7th verification output word is positioned in the address of 8 data of capable the 5th data to the of check matrix S+1, the 8th verification output word is positioned in the address of 16 data of capable the 13rd data to the of check matrix S+ 1.
Judge whether N is less than or equal to 8, if N is less than 8, return to step 103 after making N+1; Otherwise, execution step 106.
Because sytem matrix consists of four sub-sytem matrixes, check matrix consists of four sub-check matrixes.Subsystem matrix and sub-check matrix all have 8 column datas, and when N=8 is that in subsystem matrix, every column data is all positioned in the address of sytem matrix, and in sub-check matrix, every column data is all positioned in the address of check matrix.
So far, the data in sytem matrix address and the data in check matrix address are the data after rate-matched.
By row, from the 1st, be listed as to the 32nd row, the successively data in output system matrix address; Then, by row, from the 33rd row to the 64th row, the data in output verification matrix address, obtain the data after rate-matched successively.
In addition, step 201 to the technical scheme of step 206 is also adapted to Turbo coding rate de-matching in LTE system.The implementation procedure of its technical scheme and Turbo code rate coupling is identical, and difference is in step 2031, and the position of initial row equals 0.
The above, be only preferred embodiment of the present invention, is not intended to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (9)
1. a method for Turbo code rate coupling/rate de-matching in LTE system, is characterized in that, the method comprises:
According to the data length K of encoding block, determine interlace mode;
The described data length K according to encoding block determines that interlace mode comprises, K is to 32 remainder numbers, and remainder is that 0 this encoding block belongs to interlace mode 1; Remainder is that 8 these encoding blocks belong to interlace mode 2; Remainder is that 16 these encoding blocks belong to interlace mode 3; Remainder is that 24 these encoding blocks belong to interlace mode 4;
By systematic bits stream, obtain sytem matrix, the first check bit stream P1 and the second check bit stream P2 alternately deposit and obtain check matrix, from the 1st row beginning every 8 of sytem matrix, classify a sub-sytem matrix as, from the 1st row beginning every 8 of check matrix, classify a sub-check matrix as;
From N=1, start and increase progressively by 1, until N=8, after extracting successively the N row of each subsystem matrix, according to interlace mode, calculate the sytem matrix address that this column data is corresponding, from N=1, start and increase progressively by 1, until N=8, according to interlace mode, calculate the check matrix address that this column data is corresponding after extracting successively the N row of every sub-check matrix;
In each extraction, after the word packing of selecting 4 systematic bits to flow, according to pre-defined rule, be placed in described sytem matrix address, after selecting the word of 4 P1 and the word of 4 P2 to pack, according to pre-defined rule, be placed in the address of described check matrix, this selection comprises S circulation, after the line number R that S equals subsystem matrix subtracts 1, divided by 4, round downwards, R equals after K adds 4 to round up divided by 32;
After the word packing of 4 systematic bits streams of described selection, according to pre-defined rule, be placed in described sytem matrix address and comprise,
Since the 0th system word, every 8 words, take out the word of bit stream, obtain the first system word, second system word, the 3rd system word and Quaternary system system word; The maximum data of getting respectively described four systems word forms the first system output word, and inferior high data form second system output word, and inferior low data form the 3rd system output word, and minimum data forms Quaternary system system output word;
Described the first system output word is positioned in the address of 4 data of capable the 1st data to the of described sytem matrix S, described second system output word is positioned in the address of 12 data of capable the 9th data to the of described sytem matrix S, described the 3rd system output word is positioned in the address of 8 data of capable the 5th data to the of described sytem matrix S, described Quaternary system system output word is positioned in the address of 16 data of capable the 13rd data to the of described sytem matrix S;
The address that is placed in described check matrix according to pre-defined rule after the packing of the word of 4 P1 of described selection and the word of 4 P2 comprises,
Order is taken out the 0th word and the 8th word from P1, is designated as successively the first check word and the second check word, and order is taken out the 1st word and the 9th word from P2, is designated as successively the 3rd check word and the 4th check word;
The maximum data of getting respectively the first check word to the four check words forms the first verification output word, and inferior high data form the second verification output word, and inferior low data form the 3rd verification output word, and minimum data forms the 4th verification output word;
Described the first verification output word is positioned in the address of 4 data of capable the 1st data to the of described check matrix S, described the second verification output word is positioned in the address of 12 data of capable the 9th data to the of described check matrix S, described the 3rd verification output word is positioned in the address of 8 data of capable the 5th data to the of described check matrix S, described the 4th verification output word is positioned in the address of 16 data of capable the 13rd data to the of described check matrix S;
Then, then order is from P1 the 16th word of taking-up and the 24th word, is designated as successively the 5th check word and the 6th check word, and order is taken out the 17th data and the 25th data from P2, is designated as successively the 7th check word and the 8th check word;
The maximum data of getting respectively the 5th check word to the eight check words forms the 5th verification output word, and inferior high data form the 6th verification output word, and inferior low data form the 7th verification output word, and minimum data forms the 8th verification output word;
Described the 5th verification output word is positioned in the address of 4 data of capable the 1st data to the of described check matrix S+1, described the 6th verification output word is positioned in the address of 12 data of capable the 9th data to the of described check matrix S+1, described the 7th verification output word is positioned in the address of 8 data of capable the 5th data to the of described check matrix S+1, described the 8th verification output word is positioned in the address of 16 data of capable the 13rd data to the of described check matrix S+1;
Press in row output system matrix address and check matrix address in data, obtain the bit stream after rate-matched/rate de-matching.
2. the method for Turbo code rate coupling/rate de-matching in LTE system according to claim 1, it is characterized in that, after the described N that extracts successively each subsystem matrix is listed as, according to interlace mode, calculating the sytem matrix address that this column data is corresponding comprises, according to interlace mode, determine interleaving index, in the N row that are offset successively each subsystem matrix by interleaving index, the address of each data obtains the middle offset address that this is listed as each data, then obtains sytem matrix address according to middle offset address described in interlace mode and N overall offset;
After the described N that extracts successively every sub-check matrix is listed as, according to interlace mode, calculating the check matrix address that this column data is corresponding comprises, according to interlace mode, determine interleaving index, in the N row that are offset successively every sub-check matrix by interleaving index, the address of each data obtains the middle offset address that this is listed as each data, then obtains check matrix address according to middle offset address described in interlace mode and N overall offset.
3. the method for Turbo code rate coupling/rate de-matching in LTE system according to claim 2, it is characterized in that, in the described N row that are offset successively each subsystem matrix by interleaving index, the address of each data obtains further comprising before middle offset address, the initial column position of computing system matrix, the original position of sytem matrix equals k
0,
n
cbfor the soft Buffer size of rate-matched, RV is redundancy version parameters.
4. the method for Turbo code rate coupling/rate de-matching in LTE system according to claim 3, is characterized in that, works as k
0be greater than 32, the initial column position of sytem matrix equals k
0',
5. the method for Turbo code rate coupling/rate de-matching in LTE system according to claim 2, it is characterized in that, describedly according to offset address in the middle of described in interlace mode and N overall offset, obtain sytem matrix address and comprise, according to interlace mode and N, determine overall offset amount, then according to middle offset address described in overall offset amount overall offset, obtain sytem matrix address;
Describedly according to offset address in the middle of described in interlace mode and N overall offset, obtain check matrix address and comprise, according to interlace mode and N, determine overall offset amount, then according to offset address in the middle of described in overall offset amount overall offset, obtain check matrix address.
6. the method for Turbo code rate coupling/rate de-matching in LTE system according to claim 5, it is characterized in that, describedly according to interlace mode and N, determine that overall offset amount comprises, by interlace mode, determine filling bit, deduct after filling bit when 32, with N the data of P1 and be less than or equal to 32, overall offset amount H equal 32 deduct after filling bit with N the data of P1 with.
7. the method for Turbo code rate coupling/rate de-matching in LTE system according to claim 5, it is characterized in that, describedly according to interlace mode and N, determine that overall offset amount comprises, by interlace mode, determine filling bit, deduct after filling bit when 32, with N the data of P1 and be greater than 32, overall offset amount H equals the poor of N data of P1 and filling bit.
8. the method for Turbo code rate coupling/rate de-matching in LTE system according to claim 1, is characterized in that, while there is remaining data after S circulation, gets a remaining data at every turn and is positioned in the address of described remaining data.
9. the method for Turbo code rate coupling/rate de-matching in LTE system according to claim 1, it is characterized in that, when N equals 8, further comprise, according to the unnecessary bit of interlace mode fill system data, according to interlace mode, fill the unnecessary bit of checking data.
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