CN104979320A - 用于与半导体器件的连接的引线 - Google Patents

用于与半导体器件的连接的引线 Download PDF

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CN104979320A
CN104979320A CN201510108593.8A CN201510108593A CN104979320A CN 104979320 A CN104979320 A CN 104979320A CN 201510108593 A CN201510108593 A CN 201510108593A CN 104979320 A CN104979320 A CN 104979320A
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lead
folder portion
wire
semiconductor device
device die
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洛尔夫·安科约科伯·格罗恩休斯
提姆·伯切尔
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Naizhiya Co Ltd
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NXP BV
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Abstract

披露了一种用于与半导体器件管芯的连接的引线,该引线包括夹部。夹部包括主面,主面具有自其上延伸的两个或多个凸起,用于与半导体器件管芯的接合垫的连接。

Description

用于与半导体器件的连接的引线
技术领域
本发明涉及一种用于与半导体器件管芯的连接的引线,以及涉及包括该引线的半导体元件。
背景技术
半导体元件典型地由半导体器件管芯、一个或多个引线、线接合构成,线接合用于由引线至器件管芯之间通过器件管芯上的金属接触来形成电性连接。用于高电流器件的线接合工艺中,并行地使用几个接合,缓慢且难于测试。此外,线接合可能导致不可靠的接触。进一步地,半导体元件的电气性能可能遭受由线接合带来的寄生电阻和感应系数的损害。在诸如开关模式电源的应用中的静电放电保护器件或瞬时电压抑制器件,或者在其他具有大的电流变化的应用中,可能发生由于感应系数而产生的大的电压尖脉冲。此外,在高电流应用(典型地在安培数量级)中,器件发热可能导致线接合的退化。
作为一种线接合的替代,引线可以包括夹部,用于接合到半导体器件管芯。这种结构被称为夹焊,相比于引线键合,可以实现半导体元件的电气性能和热力性能的提升,并实现更为可靠的接触。
当通过金属接触夹焊至半导体管芯时,焊料可用来完成电气以机械连接。如本领域所知的,焊料可以是包括一部分铅、锡和银粉以及其他诸如熔剂媒质的添加物的膏。然而,这种结构可能遇到几个问题,例如器件管芯和片之间不适当的对准可能导致短路,以及焊料层的厚度可能导致焊膏内部的空泡。在焊接过程中,例如回流过程(本领域所知)中所蒸发的气体无法脱离空泡,可能使得管芯相对于片发生移动,也会导致不对准。这种空泡还可能降低连接的机械和/或电气完整性。
图1a和1b示出了一种已知的引线1,其包括夹部2,夹部2接合至半导体器件管芯3。如图所示,夹部2包括主面8,在引线1固定到半导体器件管芯3时,主面8可直接相邻于半导体管芯3。夹部2包括接触部9,接触部9布置为利用适当的焊料材料机械地以及电气地连接到半导体器件管芯3上预形成的适当的金属接触(图未示)。
除了以上提及的问题以外,该结构以及其他已知的结构还可能遇到的问题是:半导体器件管芯和片之间的焊料连接的完整性只可能从侧面检查,从而使得生产能力降低。在大规模的生产过程中,使用例如显微镜来进行检查是有利的。此外,有调查发现,半导体器件管芯可能与夹部不正确地对准,这将可能导致半导体管芯的短路,进而使得半导体元件无法工作。
发明内容
根据本发明的一个方面,提供一种用于与半导体器件管芯的连接的引线,引线包括夹部,夹部包括主面,主面具有自其上延伸的两个或多个凸起,用于与半导体器件管芯的接合垫的连接。
本发明还涉及包括这种引线的半导体元件。
进一步地,本发明涉及这样一种半导体元件,其中该半导体元件为功率整流器件或瞬时电压抑制器件。
本发明的实施方式可涉及输送高电流的半导体元件,例如在5-20安培的范围内,并具有低正向电压。
附图说明
在附图和以下的说明中,相同的标记指代的是相同的特征。以下将结合附图对于本发明的实施方式进行进一步描述。
图1a为一种已知连接引线的平面视图;
图1b为一种已知连接引线的剖面视图;
图2a为一种实施方式的连接引线的平面视图;
图2b为一种实施方式的连接引线的剖面视图;
图2c为一种替代实施方式的连接引线的平面视图;
图3a为使用已知引线进行器件导通电阻的仿真;
图3b为使用本发明实施方式的引线进行器件导通电阻的仿真;
图4a为一种实施方式的连接引线的平面视图;
图4b为一种实施方式的连接引线的剖面视图。
具体实施方式
图2a和2b所示的分别是一种引线20的实施方式的底部和侧面视图,该引线20适用于与半导体器件管芯3相连接。引线20可包括夹部22和引线框架连接片24。引线框架连接片24布置为,其可以连接到引线框架片垫21,以允许电流通过夹部22自半导体器件管芯3流入外部源,或自外部源流入半导体器件管芯3。半导体器件管芯3可以使用任何适当的连接,例如焊料膏或导电粘合剂,以机械地和/或电气地与引线框架管芯垫23接触。
夹部22包括第一主面28和第二主面30。在引线20贴上半导体器件管芯3的接触部(也称为金属化部)时,第一主面28将最为接近并实质上面对半导体管芯3。可透过夹部22自第一主面28至第二主面30提供过孔26。
过孔26的作用是通风,其允许在焊接过程中在夹部22的第一主面28下累积的气体泄出。在焊接过程中将可能形成气体,并导致焊料材料内部形成气泡。在焊接过程之后,在焊接冷却后,这些气泡可能导致夹部22下方焊料材料中空泡的形成。这些空泡可能导致焊头不稳定,并进而导致半导体器件管芯3相对于夹部22的不对准。这种不对准可能导致半导体器件管芯3上的接触之间的短路,或者半导体器件管芯3无电连接。通过允许气体泄出,可以使得空泡最小化甚至消失。空泡还可能导致电气接触和热接触性能变差。
作为以上的在夹部中具有过孔26的结构的替代方案,夹部22可以采用分叉的形式。如图2c所示,夹部22自引线框架连接片24分叉地延伸开来。在这种结构中,夹部22可以由两个分支形成,在两个分支之间具有切开部分。这将使得在回流过程中产生的气体泄出增多,改善目视检查的切入,并且由于夹部22的剖面面积减小,施加在焊料层上的力也减小。该结构可以提升夹部22的柔性。柔性的提升可使得处于温度周期变化中延展和收缩的夹部的机械性能得以提升。可选地,可以预期的是,夹部22可以由三个或更多个分支构成,在各个分支之间具有切开部分。
过孔26或切开部分还可以使得从位于夹部22和半导体器件管芯3的接触部(图未示)之间的焊接连接的上方对其进行的目视检查变得简单。
第一主面28可包括几个凸起32、34,其自第一主面28向外沿着朝向半导体器件管芯3的接触部的方向在第一维度上延伸。在第二维度上,凸起32、34脊状延伸,呈现为似横穿第一主面28。在此情况下,凸起32、34彼此平行地延伸开来,过孔26位于其间。可替代地,过孔26或切开部分可以与凸起32、34中的一个或多个相交。在一种可选的结构中,各凸起可以配置为在夹部22上的某一点处概念上地彼此相交。该相交点为概念上的,是因为它可能会被过孔26或切开部分所中断。
凸起32、34的作用可以为:减小半导体器件管芯3的接触部与夹部22之间的距离。因此,通过熔化的焊料与凸起32、34之间的作用,半导体器件管芯3可以实现自对准。仅作为示例地,半导体器件管芯3的接触部与凸起之间的距离可以小于1μm。半导体器件管芯3与夹部之间的对准可以是由于熔化的焊料的表面张力。这种对准方式可以避免半导体器件管芯3相对于夹部22的不对准。例如,对于用在低封装高度结构中的半导体器件管芯3而言,通过保证焊料不会溢出到半导体器件管芯3的接触部以外的区域上,可以防止出现短路。进一步地,半导体器件管芯3可以与凸起32、34对准,从而相对于夹部而言不会出现倾斜,例如使半导体器件管芯3的角部与夹部22接触。
此外,凸起32、34的作用还可以限制焊接连接上的面积,焊接连接具有小厚度(典型地小于或等于10μm)焊料层40,焊料层40是用来形成与半导体器件管芯3的接触部的电气和机械接触所需要的。此外,若凸起32、34形成为呈类似脊状并平行,横穿夹部22的第一主面28可形成沟槽38,其将有利于焊接过程中气体的逸出。在夹部下没有凸起的第一主面28之间,焊料层40的厚度典型地在30μm至50μm量级。
为减少最终封装的半导体器件中模制成分(图未示)的分层,在引线20的引线框架连接片24中可以形成切口42。此外,夹部22可包括悬置部分46,其可以设置在夹部22的相对引线框架连接片24的远侧呈梯状。该悬置部分46可以防止模制成分中形成裂纹。
夹部22的面积应当足够大,以便在夹部和包括管芯角落的管芯表面之间得到较低的电阻。夹部的面积应当使得管芯的接触部至少有40%的面积被夹部覆盖。夹部的尺寸的相对于接触垫尺寸的比例上限应约为90%。这将使得半导体器件管芯3短路的可能性最小,并实现机械和/或电气的安全连接,并可进行对于焊接接合的检查。如图3b,其为表示管芯与夹部之间导通电阻的器件模拟(器件的正向电流为19.8安培,正向电压为0.44伏特,半导体器件管芯接触金属堆叠厚度为1.6μm)结果,其中显示,贴在管芯上的夹部从中心至角落大约有15mV的电压降。图3a所示的是已知的器件的模拟,与图3a所示的相比,包括了本发明实施方式的器件的导通电阻模拟的压降从35mV下降到15mV。
引线框架连接片24可以是前述的分叉形式。可选地,它也可以是不分开的。分叉设计可以适用在需要有单独的连接引线接合的情况。
引线20的夹部22和引线框架连接片24是由同一片材料整体地形成。该材料可以是任意合适的材料,以允许通过适当的焊接实现与半导体管芯的电学和机械连接。该材料可以是例如铜,其上具有银或锡镀层。该材料可以具有一定程度的柔性,以便其可以弹性地偏靠在半导体器件器件管芯3的接触部。
引线20可以由任意合适的工艺形成,例如冲压。凸起32、34可以由可以理解的任意合适的工艺形成,例如所谓的冲压或压模技术。在冲压或压模的情况下,脊32、34和凹痕38可以出现在夹部22的第二主面30上。
现在如图4a和图4b所示的,凸起32、34可以为浅凹形式,其自第一主面向外沿着朝向半导体器件管芯的接触部的方向在第一维度上延伸。浅凹可以是任意合适的形状,只要它们可以通过焊料层40接触半导体器件管芯3的接触部(图未示)。
围绕夹部22的周边可以形成一个或多个切开部分44。通过提供至少一个切开部分44,夹部22的柔性得以增强,从而防止焊料层在回流过程中的热循环中裂开。切开部分还可以在回流过程中使得气体逸出(或泄出)。切开部分还可以减轻回流过程之前的焊料分发。如以上所述的结构,还可以包括一个过孔,以进一步增强气体的泄出,并利于检查。在夹部22中和引线框架连接片24中还可以包括额外的过孔45,以通过检测引线框架连接片24下是否有不需要的材料,来进一步实现对于焊料层的目视检查。
该引线可用于可能发生大的电流变化的元件中。该引线还可以用于那些寄生感应系数需要被限制的元件中,例如瞬时电压抑制二极管、静电放电防护二极管,或者在开关模式电流中。
通过防止或减少在焊料层中的空泡,以及通过由于凸起32、34而形成的均匀且具有足够厚度的焊料层,可以减小在器件工作中由于热循环而可能产生的焊料层的裂缝。这将提升引线的夹部22至半导体器件管芯的焊接接合强度。例如,破坏焊接接合所需的切变力将会增大,特别地,即使在经过了数千个热循环之后,破坏接合所需的切变力也将会增大。
本发明的诸多方面在权利要求中进行了定义。任何对于独立和/或从属权利要求中的技术特征的结合都是可能的,并不需要明确在权利要求中说明。
本发明包括了明示或暗示的诸多新颖的特征或特征组合,其范围或其泛化范围无关乎其是否与权利要求中的技术方案相关,亦无关乎其减轻或解决了本发明所提出的任何或全部问题。申请人谨此说明,在本申请或其他派生的申请的后续过程中,可由上述的技术特征及/或其集合形成为新的权利要求。特别地,对于本发明的权利要求,独立权利要求中的特征可以与从属权利要求中的特征相结合;从属权利要求中的特征可以以任何合适的方式结合,并不一定如权利要求书中所记述的特定组合方式。
本申请上下文所述的各实施方式中的技术特征也可以在单一实施方式中组成其集合。反之亦然,为简化说明而在某一实施方式中描述的各个技术方案也可以分开形成为任意合适的单一实施方式或子集组合。
在权利要求中,置于括弧中的参考标号不应理解为构成权利要求的限制范围。

Claims (15)

1.一种用于与半导体器件管芯的连接的引线,其特征在于,引线包括夹部,夹部包括主面,主面具有自其上延伸的两个或多个凸起,用于与半导体器件管芯的接合垫的连接。
2.如权利要求1所述的引线,其特征在于:所述凸起形成为横穿夹部的主面而延伸的长脊。
3.如权利要求1所述的引线,其特征在于:所述夹部还包括至少一个穿过其延伸的过孔。
4.如权利要求3所述的引线,其特征在于:所述至少一个过孔与所述长脊相交。
5.如权利要求3或4所述的引线,其特征在于:所述至少一个过孔设置在凸起之间。
6.如权利要求1或3所述的引线,其特征在于:所述夹部是分叉的,以包括至少两个分支,并在其间具有切开部分,夹部的每个分支包括至少一个凸起。
7.如权利要求3至6所述的引线,其特征在于:所述过孔或切开部分设置为通风口。
8.如在先任一权利要求所述的引线,其特征在于:还包括分布于夹部周边的一个或多个切开部分。
9.如在先任一权利要求所述的引线,其特征在于:夹部设置为柔性的。
10.如在先任一权利要求所述的引线,其特征在于:夹部的区域的至少40%与半导体器件管芯的接触的区域重叠。
11.如在先任一权利要求所述的引线,其特征在于:还包括引线框架连接片,引线框架连接片在夹部的远侧。
12.如权利要求12所述的引线,其特征在于:还包括梯状构造,位于夹部的一端并远侧于引线框架连接片。
13.如权利要求11所述的引线,其特征在于:还包括在框架连接片和夹部中的过孔。
14.一种包括权利要求1至13所述的引线的半导体元件。
15.如权利要求14所述的半导体元件,其特征在于:所述半导体元件为功率整流器件或瞬时电压抑制器件。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107910308A (zh) * 2016-09-30 2018-04-13 英飞凌科技美国公司 用于半导体装置封装体的导电夹
CN108206163A (zh) * 2016-12-19 2018-06-26 安世有限公司 Ic封装件中夹布置的半导体器件和方法
CN110211942A (zh) * 2019-07-10 2019-09-06 广东气派科技有限公司 一种芯片封装用的铜夹和芯片封装结构
CN111326493A (zh) * 2018-12-17 2020-06-23 安世有限公司 用于半导体装置的引线框架组件
CN113594125A (zh) * 2020-05-01 2021-11-02 安世有限公司 半导体装置及其制造方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9640465B2 (en) 2015-06-03 2017-05-02 Infineon Technologies Ag Semiconductor device including a clip
KR102565034B1 (ko) * 2016-11-09 2023-08-09 주식회사 아모텍 기능성 컨택터
WO2018150553A1 (ja) * 2017-02-20 2018-08-23 新電元工業株式会社 電子装置
WO2019082345A1 (ja) * 2017-10-26 2019-05-02 新電元工業株式会社 半導体装置、及び、半導体装置の製造方法
US11211353B2 (en) * 2019-07-09 2021-12-28 Infineon Technologies Ag Clips for semiconductor packages
US11177197B2 (en) * 2019-09-25 2021-11-16 Texas Instruments Incorporated Semiconductor package with solder standoff
JP7414073B2 (ja) * 2019-10-15 2024-01-16 富士電機株式会社 半導体モジュール
US11545459B2 (en) 2021-01-22 2023-01-03 Infineon Technologies Ag Metal clip with solder volume balancing reservoir
KR20230168513A (ko) * 2022-06-07 2023-12-14 현대모비스 주식회사 파워모듈에 적용되는 메탈 클립
CN117542820A (zh) * 2022-08-02 2024-02-09 力特半导体(无锡)有限公司 用于电视装置的封装结构组件
CN117673053A (zh) * 2022-08-24 2024-03-08 力特半导体(无锡)有限公司 二合一引线框架封装件

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070114352A1 (en) * 2005-11-18 2007-05-24 Victor R Cruz Erwin Semiconductor die package using leadframe and clip and method of manufacturing
US20080093736A1 (en) * 2006-10-23 2008-04-24 Nec Electronics Corporation Semiconductor device
CN101593740A (zh) * 2008-05-30 2009-12-02 万国半导体股份有限公司 用于半导体器件封装的导电夹片
US20090321900A1 (en) * 2008-06-26 2009-12-31 Mitsubishi Electric Corporation Semiconductor device
CN101752329A (zh) * 2008-12-01 2010-06-23 万国半导体有限公司 带有堆积式互联承载板顶端散热的半导体封装及其方法
US20110076807A1 (en) * 2007-08-28 2011-03-31 Gomez Jocel P Self locking and aligning clip structure for semiconductor die package
US20110108968A1 (en) * 2006-05-04 2011-05-12 International Rectifier Corporation Semiconductor package with metal straps
CN102194788A (zh) * 2010-03-18 2011-09-21 万国半导体股份有限公司 多层引线框封装及其制备方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4085768B2 (ja) * 2002-10-08 2008-05-14 トヨタ自動車株式会社 上部電極、パワーモジュール、および上部電極のはんだ付け方法
CN101819955B (zh) * 2004-12-20 2011-09-28 半导体元件工业有限责任公司 具有增强散热性的半导体封装结构
JP2006190728A (ja) * 2005-01-04 2006-07-20 Mitsubishi Electric Corp 電力用半導体装置
US7683464B2 (en) * 2005-09-13 2010-03-23 Alpha And Omega Semiconductor Incorporated Semiconductor package having dimpled plate interconnections
US8581376B2 (en) * 2010-03-18 2013-11-12 Alpha & Omega Semiconductor Incorporated Stacked dual chip package and method of fabrication
JP5270614B2 (ja) * 2010-05-24 2013-08-21 三菱電機株式会社 半導体装置
TW201251140A (en) * 2011-01-31 2012-12-16 Cree Inc High brightness light emitting diode (LED) packages, systems and methods with improved resin filling and high adhesion
US8354733B2 (en) * 2011-03-04 2013-01-15 International Rectifier Corporation IGBT power semiconductor package having a conductive clip
JP2013161941A (ja) * 2012-02-06 2013-08-19 Renesas Electronics Corp 半導体装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070114352A1 (en) * 2005-11-18 2007-05-24 Victor R Cruz Erwin Semiconductor die package using leadframe and clip and method of manufacturing
US20110108968A1 (en) * 2006-05-04 2011-05-12 International Rectifier Corporation Semiconductor package with metal straps
US20080093736A1 (en) * 2006-10-23 2008-04-24 Nec Electronics Corporation Semiconductor device
US20110076807A1 (en) * 2007-08-28 2011-03-31 Gomez Jocel P Self locking and aligning clip structure for semiconductor die package
CN101593740A (zh) * 2008-05-30 2009-12-02 万国半导体股份有限公司 用于半导体器件封装的导电夹片
US20090321900A1 (en) * 2008-06-26 2009-12-31 Mitsubishi Electric Corporation Semiconductor device
CN101752329A (zh) * 2008-12-01 2010-06-23 万国半导体有限公司 带有堆积式互联承载板顶端散热的半导体封装及其方法
CN102194788A (zh) * 2010-03-18 2011-09-21 万国半导体股份有限公司 多层引线框封装及其制备方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107910308A (zh) * 2016-09-30 2018-04-13 英飞凌科技美国公司 用于半导体装置封装体的导电夹
CN108206163A (zh) * 2016-12-19 2018-06-26 安世有限公司 Ic封装件中夹布置的半导体器件和方法
CN111326493A (zh) * 2018-12-17 2020-06-23 安世有限公司 用于半导体装置的引线框架组件
CN110211942A (zh) * 2019-07-10 2019-09-06 广东气派科技有限公司 一种芯片封装用的铜夹和芯片封装结构
CN113594125A (zh) * 2020-05-01 2021-11-02 安世有限公司 半导体装置及其制造方法
CN113594125B (zh) * 2020-05-01 2023-03-03 安世有限公司 半导体装置及其制造方法

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