CN104979270A - Interconnection structure formation method - Google Patents
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- CN104979270A CN104979270A CN201410133367.0A CN201410133367A CN104979270A CN 104979270 A CN104979270 A CN 104979270A CN 201410133367 A CN201410133367 A CN 201410133367A CN 104979270 A CN104979270 A CN 104979270A
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Abstract
The invention provides an interconnection structure formation method. The method comprises that a metal layer is formed on a semiconductor substrate, a first mask layer is formed on the metal layer, wherein the first mask layer is internally provided with a first opening penetrating the first mask layer, a second mask layer is formed in the first opening, a third mask layer is formed on the second mask layer, and a second opening is formed in the metal layer after the metal layer is etched by the third mask layer; and after the third mask layer and the first mask layer are removed, the metal layer is etched taking the second mask layer as the mask so as to form the interconnection structure. According to the technical scheme provided by the invention, the thick metal layer is formed on the semiconductor substrate, then the interconnection structure is formed by etching the metal layer. Compared with the conventional scheme that a metal material is arranged to fill an opening formed in a dielectric layer so as to form the interconnection structure, the technical scheme provided by the invention can effectively increase the size of metal particles formed in the metal layer, so that when power is switched on, an electron scattering phenomenon due to over-small metal particles is reduced, and the electrical resistivity of the interconnection structure is lowered.
Description
Technical field
The present invention relates to technical field of semiconductors, especially relate to a kind of formation method of interconnection structure.
Background technology
Along with semiconductor technology evolves, the integrated level of device constantly increases, and the process node of semiconductor device constantly diminishes, also more and more higher to the requirement of semiconductor technology.
Semiconductor device is generally a sandwich construction, and components and parts are arranged at different interlayer dielectric layer (Interlayer Dielectric, ILD) surfaces, and the components and parts between different layers realize electrical connection by the interconnection structure being positioned at interlayer dielectric layer.
With reference to figure 1 and Fig. 2, show the schematic diagram of the formation method of a kind of interconnection structure of prior art, the formation method of described interconnection structure comprises:
As shown in Figure 1, form dielectric layer 11 over the semiconductor substrate 10, coverage mask layer 12 on dielectric layer 11 is mask etching dielectric layer 11 with described mask layer 12, forms the groove 13 for the formation of interconnection structure in dielectric layer 11.
Then with reference to shown in figure 2, the methods such as electroplating technology (ECP) are adopted in described groove 13, to fill the metal materials such as copper, to form interconnection structure 14.
But the resistivity of the metal material that prior art is formed in groove 13 is higher, have impact on interconnection structure performance.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of interconnection structure, thus reduces the resistivity of interconnection structure.
For solving the problem, the invention provides a kind of formation method of interconnection structure, comprising:
Semiconductor substrate is provided;
Form metal level on a semiconductor substrate;
Described metal level is formed the first mask layer, in described first mask layer, is formed with the first opening running through described first mask layer thickness;
The second mask layer is formed in the first opening of described first mask layer;
Described first mask layer forms the 3rd mask layer, and described 3rd mask layer covers described second mask layer completely;
With described 3rd mask layer for mask, the metal level of the first mask layer that removal the 3rd mask layer exposes and segment thickness, forms the second opening in described metal level;
Remove described 3rd mask layer;
Remove described first mask layer;
With described second mask layer for metal level described in mask etching, the metal level that thinning second mask layer exposes, makes the second open bottom metal level remove, to form interconnection structure on the semiconductor substrate.
Alternatively, the technique etching described metal level is dry etch process.
Alternatively, described dry etch process comprises: adopt the gas containing chlorine to be dry etching agent.
Alternatively, described dry etch process also comprises assist gas, described assist gas comprise in oxygen, hydrogen, nitrogen or argon gas one or more.
Alternatively, adopt chlorine to carry out in the step of dry etching, power is 100 ~ 2000w, bias voltage is 0 ~ 500w, air pressure is 1 ~ 500mtorr, and the flow of chlorine is 1 ~ 500sccm.
Alternatively, the step forming the second mask layer in the first opening of described first mask layer comprises:
In the first opening of described first mask layer, fill full described second mask layer, and described second mask layer covers described first mask surface;
After described 3rd mask layer of removal, before removing described first mask layer, described formation method also comprises: remove the second mask layer on described first mask layer, until expose described first mask layer.
Alternatively, the technique of the second mask layer removed on described first mask layer is chemical mechanical milling tech.
Alternatively, the step forming metal level on a semiconductor substrate comprises: adopt electroplating technology to form described metal level.
Alternatively, the material of described first mask layer is copper nitride.
Alternatively, the technique removing described first mask layer is wet-etching technology.
Alternatively, described wet-etching technology adopts hydrogen chloride solution to be wet etchant.
Alternatively, between described first mask layer and Semiconductor substrate, also barrier layer is comprised.
Alternatively, the material on described barrier layer is silica.
Alternatively, described metal level is layers of copper.
Alternatively, described formation method also comprises: in the second opening of described metal level, fill interlayer dielectric layer.
Alternatively, the material of described interlayer dielectric layer is low-K dielectric material or super low-K dielectric material.
Compared with prior art, technical scheme of the present invention has the following advantages:
The present invention first forms metal level on a semiconductor substrate, interconnection structure is formed afterwards by etching sheet metal, the scheme that metal material forms interconnection structure is filled in the existing groove formed in dielectric layer, the thickness of metal level is not by the restriction of thickness of dielectric layers, Semiconductor substrate can form the larger metal level of thickness, and the larger metal level of thickness has the metal grain (grain) of large-size, crystal grain intersection interface (grain boundary) between the metal grain of large-size is less, thus electron scattering phenomenon can be reduced, and then reduce the resistivity of interconnection structure.
Further, described first mask layer adopts copper nitride to be material, metal layer material is copper, when follow-up employing wet-etching technology removes copper nitride, copper nitride and copper have higher etching selection ratio, and the etch-rate of copper nitride is far longer than the etch rate of copper, thus when removal the first mask layer, effectively can reduce the damage of metal level, thus improve the performance of the interconnection structure of follow-up formation.
Further, after formation interconnection structure, in the second opening in metal level on the semiconductor substrate, fill full interlayer dielectric layer.Groove is formed by etching interlayer dielectric layer compared to existing, backward interlayer dielectric layer groove in fill metal material and form the technical scheme of interconnection structure, the present invention is without the need to arranging etching interlayer dielectric layer to form the operation of groove, thus decrease the damage of etch step to interlayer dielectric layer, improve the performance of semiconductor device of follow-up formation.
Accompanying drawing explanation
Fig. 1 and Fig. 2 is the structural representation of each step in the formation method of a kind of interconnection structure of prior art;
Fig. 3 ~ Figure 11 is the structural representation of formation method one embodiment of interconnection structure of the present invention.
Embodiment
As stated in the Background Art, the resistivity of the metal material of the interconnection structure that prior art is formed is higher, thus affects performance of semiconductor device, is difficult to meet semiconductor device development requirement.
Analyze its reason, in existing interconnection structure preparation technology, by filling the mode of metal material in the groove offered in dielectric layer with the interconnection structure formed, in metal material forming process, dielectric layer defines the formation space of metal material, the thickness of the metal material formed is less, make the size of metal grain in the metal material of formation less, after interconnection structure energising, easily there is electron scattering at the intersection interface place of described metal grain in electronics, thus adds the resistivity of interconnection structure.
In order to solve the problem, the invention provides a kind of formation method of interconnection structure, comprising: Semiconductor substrate is provided; Form metal level on a semiconductor substrate; Described metal level is formed the first mask layer, in described first mask layer, is formed with the first opening running through described first mask layer thickness; The second mask layer is formed in the first opening of described first mask layer; Described first mask layer forms the 3rd mask layer, and described 3rd mask layer covers described second mask layer completely; With described 3rd mask layer for mask, the metal level of the first mask layer that removal the 3rd mask layer exposes and segment thickness, forms the second opening in described metal level; Remove described 3rd mask layer; Remove described first mask layer; With described second mask layer for metal level described in mask etching, the metal level that thinning second mask layer exposes, makes the second open bottom metal level remove, to form interconnection structure on the semiconductor substrate.
The present invention first forms metal level on a semiconductor substrate, interconnection structure is formed afterwards by etching sheet metal, the scheme that metal material forms interconnection structure is filled in the existing groove formed in dielectric layer, the thickness of metal level is not by the restriction of thickness of dielectric layers, Semiconductor substrate can form the larger metal level of thickness, and the larger metal level of thickness has the metal grain (grain) of large-size, crystal grain intersection interface (grain boundary) between the metal grain of large-size is less, thus electron scattering phenomenon can be reduced, and then reduce the resistivity of interconnection structure.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Fig. 3 ~ Figure 11 is the structural representation of formation method one embodiment of interconnection structure of the present invention.
Shown in first reference diagram 3, the formation method of the interconnection structure that the present embodiment provides comprises:
Semiconductor substrate 20 is provided.
In the present embodiment, described Semiconductor substrate 20 comprises: semiconductor base or semiconductor base and be formed in semiconductor base or the semiconductor components and devices of semiconductor substrate surface.Described semiconductor components and devices comprises cmos device, and described cmos device comprises transistor, memory, capacitor or electric part, and the electric interconnection structure for making described semiconductor components and devices be electrically connected.
Described semiconductor base is silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator (SOI) substrate, germanium on insulator (GOI) substrate, glass substrate or III-V substrate, and described semiconductor base materials does not limit protection scope of the present invention.
Please continue to refer to Fig. 3, described Semiconductor substrate 20 forms metal level 21.The thickness of described metal level 21 is H1.
In the present embodiment, the formation process of described metal level 21 is electroplating technology.
Alternatively, described metal level 21 is layers of copper.Its formation process specifically comprises: first adopt physical gas-phase deposition (Physical Vapor Diposition, PVD) in described Semiconductor substrate 20, one deck copper seed layer (not shown) is formed, afterwards described Semiconductor substrate 20 is placed in electroplating bath, adopt copper electroplating technology, the basis of described copper seed layer is continued form metallic copper, thus form described metal level 21.
Adopt electroplating technology effectively can improve the efficiency forming metallic copper, certainly, in other embodiments, can directly adopt PVD technique in described Semiconductor substrate 20, directly form the layers of copper of specific thicknesses.It is all protection scope of the present invention.
Compare and the technique forming metallic copper traditionally in the groove of dielectric layer, in the present embodiment, described Semiconductor substrate 20 is directly formed the technique of layers of copper, in the forming process of layers of copper, larger growing space (as improved the thickness forming metal level 21) is provided to copper crystal grain, thus make to form larger-size metal grain in metal level 21, larger metal grain can reduce electron scattering phenomenon, thus reduces the resistivity of the interconnection structure of follow-up formation.
Shown in figure 4, described layers of copper 21 is formed the first mask layer 23, first mask layer 23 there is the first opening 31 running through described first mask layer 23 thickness.
In the present embodiment, the material of described first mask layer 23 is copper nitride (Cu3N).When follow-up employing wet-etching technology removes copper nitride, copper nitride and copper have higher etching ratio, the etch-rate of copper nitride is far longer than the etch rate of copper, thus when removal the first mask layer 23, effectively can reduce the damage of metal level, thus improve the performance of the interconnection structure of follow-up formation.
Alternatively, in the present embodiment, before described metal level 21 is formed described first mask layer 23, first on described metal level 21, form barrier layer 22, on described barrier layer 22, form described first mask layer 23 afterwards.Described barrier layer 22 effectively can reduce the atoms permeating phenomenon between described layers of copper 21 and the first mask layer 23.
In the present embodiment, the material on described barrier layer 22 is silica.
Particularly, the step forming described first mask layer 23 comprises: in Semiconductor substrate 20, form layer of mask material, described layer of mask material is formed the first photoresist layer, after exposure imaging technique, in described first photoresist layer, forms the first patterns of openings; Afterwards, etch described layer of mask material and barrier layer 22 along described first patterns of openings, in described layer of mask material and barrier layer 22, form the first opening 31, the layer of mask material with described first opening 31 forms the first mask layer 23.
Then with reference to shown in figure 5, in the first opening 31 of described first mask layer 23, the second mask layer 24 is formed.
In the present embodiment, the formation process of described second mask layer 24 comprises, and fills described second mask layer 24, until described second mask layer 24 covers described first mask layer 23 in the first opening 31 of described first mask layer 23.
In the present embodiment, the material of described second mask layer 24 can be spin-on oxide (Spin-on Oxide).Particularly, the spin-on oxide in the present embodiment can adopt DUO(Deep Ultraviolet Oxide), DUO is the polymer based on siloxanes.The method of spin coating can be adopted to form described second mask layer 24.
In conjunction with reference to shown in figure 6, form the 3rd mask layer 25 on the surface of described second mask layer 24, described 3rd mask layer 25 covers the second mask layer 24 of the first opening 31 being positioned at described first mask layer 23 completely.The second patterns of openings 32 running through described 3rd mask layer 25 thickness is formed, the second mask layer 24 of described second patterns of openings 32 exposed portion in described 3rd mask layer 25.
In the present embodiment, the material of described 3rd mask layer 25 is photoresist, and form the technique of described second patterns of openings 32 for development, exposure technology, it is the mature technology of this area, does not repeat them here.
Then with reference to shown in figure 7, with described 3rd mask layer 25 for mask, etch described second mask layer 24, first mask 23 along described second patterns of openings 32, barrier layer 22 and described metal level 21, in described metal level 21, form the second opening 211.
In the present embodiment, the degree of depth of described second opening 211 is H2, and the interconnection structure horizontal component that described second opening 211 is follow-up formation and vertical portion provide difference in height.
In the present embodiment, etch described second mask layer 24, first mask layer 23, the technique of barrier layer 22 and described metal level 21 is dry etch process.
Described dry etch process specifically comprises: adopt the gas containing chlorine (Cl2) to etch described metal level 21, the power of etching is 100 ~ 2000w, bias voltage is 0 ~ 500w, air pressure is 1 ~ 500mtorr, wherein, the flow of chlorine is 1 ~ 500sccm.
Further, described etching gas also can comprise assist gas, described assist gas comprise in oxygen (O2), hydrogen (H2), nitrogen (N2) or argon gas (Ar) one or more.Wherein, the flow of described oxygen is 0 ~ 200sccm, and the flow of nitrogen is 0 ~ 500sccm, and the flow of hydrogen is 0 ~ 1000sccm, and the flow of argon gas is 0 ~ 500sccm.
Shown in figure 8, form described second opening 211 in described metal level 21 after, remove the 3rd mask layer 25; Remove the second mask layer 24 above described first mask layer 23 afterwards, retain the second mask layer 241 in described first mask layer 23, expose the surface of the second mask layer 241 and described first mask layer 23.
In the present embodiment, the technique removing described 3rd mask layer 25 is chosen as wet-etching technology, or cineration technics; The technique removing the second mask layer 24 above described first mask layer 22 is chosen as chemical mechanical milling tech (CMP).Above-mentioned technique is the mature technology of this area, does not repeat them here.
Shown in figure 9, after exposing the surface of the second mask layer 241 being positioned at described first opening 31, remove described first mask layer 23 and barrier layer 22, expose described metal level 21, described second mask layer 241 is raised in described metal level 21 surface.
In the present embodiment, the technique removing described first mask layer 23 and barrier layer 22 is wet-etching technology.
In the present embodiment, the wet-etching technology removing described first mask layer 23 adopts hydrogen chloride (HCl) solution to be wet etching reagent.
In the present embodiment, the material of described first mask layer 23 is copper nitride, the material on barrier layer 22 is silica, second mask layer 241 is DUO, adopt hydrogen chloride to be in the wet-etching technology of wet etchant, copper nitride, silica, copper and DUO have larger etching selection ratio, copper nitride and the etch rate of silica be far longer than the etch rate of copper and DUO, wherein, described copper nitride is greater than 3000 with the etch rate ratio of copper.Thus, when removing described first mask layer 23, the damage of metal level 21 and DUO can effectively be reduced.
In conjunction with reference to shown in figure 9 and Figure 10, after described first mask layer 23 of removal, with remaining described second mask layer 241 for mask, etch the described metal level 21 that described second mask layer 241 exposes, with the thickness of thinning metal level 21, until remove the metal level in described second opening 211, expose described Semiconductor substrate 20, in described Semiconductor substrate 20, remaining metal level forms interconnection structure 213.
In the present embodiment, the technique etching described metal level 21 is dry etch process.
Described dry etch process specifically comprises: adopt the gas containing chlorine (Cl2) to be dry etching agent, the power of etching is 100 ~ 2000w, bias voltage is 0 ~ 500w, air pressure is 1 ~ 500mtorr, and wherein, the flow of chlorine is 1 ~ 500sccm.Further, described etching gas also can comprise assist gas, described assist gas comprise in oxygen (O2), hydrogen (H2), nitrogen (N2) or argon gas (Ar) one or more.Wherein, the flow of described oxygen is 0 ~ 200sccm, and the flow of nitrogen is 0 ~ 500sccm, and the flow of hydrogen is 0 ~ 1000sccm, and the flow of argon gas is 0 ~ 500sccm.
In above-mentioned etch step, eliminate the metal level of the second opening 211 being originally positioned at metal level 21, be thinned the metal level that all the other second mask layers 241 expose, thinning rear remaining metal level is the metal level that horizontal component 2132, second mask layer 241 of interconnection structure 213 covers is the vertical component 2131 of interconnection structure 213.
In the present embodiment, the thickness of described interconnection structure 213 horizontal component 2132 is the difference that H3, H3 are roughly H1 and H2.(combining with reference to figure 3 and Fig. 7).
In conjunction with reference to shown in Figure 11, after forming described interconnection structure 213, remove remaining described second mask layer 241.
In the present embodiment, the technique removing described second mask layer 241 is wet-etching technology.Adopt wet-etching technology when removing described second mask layer 241, the damage of metal level 21 can be reduced.
Particularly, in the present embodiment, the wet etchant removing described second mask layer 241 is CLK888 solution.
After described second mask layer 241 of removal, fill interlayer dielectric layer 40, to realize the insulation of interconnection structure 213 to described second opening 211.
Particularly, during the interlayer dielectric layer 40 of formation, the material of interlayer dielectric layer also can be covered in the surface of described 213, follow-uply can remove unnecessary inter-level dielectric layer material by techniques such as CMP, to expose the surface of described interconnection structure 213.
In the present embodiment, described dielectric layer 40 be chosen as the conventional dielectric material such as silica.Alternatively, the material of described dielectric layer 40 is low-K dielectric material (K value is less than 3) or super low-K dielectric material (K value is less than 2.6), as having the materials such as the silica of the carbon dope of loose structure, thus reduce the parasitic capacitance of the interconnection structure of the semiconductor device of follow-up formation, reduce RC delays (RC Delay) effect occurred when signal transmits in interconnection structure.The preparation technology of described interlayer dielectric layer 40 is the maturation process of this area, does not repeat them here.
Need to illustrate it is noted that with reference to shown in figure 6, in this example, described second mask layer 24 fills the first opening 31 of full described first mask layer 23, and covers described first mask layer 23, and described 3rd mask layer 25 is covered in described second mask layer 24 surface.
In another embodiment of the present invention, described second mask layer 24 can be partially filled described first opening 31 or just fill described first opening 31 completely, and does not cover the first mask layer 24.Directly can form the 3rd mask layer 25 on the surface of described first mask layer 24 afterwards.These simply change all in protection scope of the present invention.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (16)
1. a formation method for interconnection structure, is characterized in that, comprising:
Semiconductor substrate is provided;
Form metal level on a semiconductor substrate;
Described metal level is formed the first mask layer, in described first mask layer, is formed with the first opening running through described first mask layer thickness;
The second mask layer is formed in the first opening of described first mask layer;
Described first mask layer forms the 3rd mask layer, and described 3rd mask layer covers described second mask layer completely;
With described 3rd mask layer for mask, the metal level of the first mask layer that removal the 3rd mask layer exposes and segment thickness, forms the second opening in described metal level;
Remove described 3rd mask layer;
Remove described first mask layer;
With described second mask layer for metal level described in mask etching, the metal level that thinning second mask layer exposes, makes the second open bottom metal level remove, to form interconnection structure on the semiconductor substrate.
2. the formation method of interconnection structure as claimed in claim 1, it is characterized in that, the technique etching described metal level is dry etch process.
3. the formation method of interconnection structure as claimed in claim 2, it is characterized in that, described dry etch process comprises: adopt the gas containing chlorine to be dry etching agent.
4. the formation method of interconnection structure as claimed in claim 3, it is characterized in that, described dry etch process also comprises assist gas, described assist gas comprise in oxygen, hydrogen, nitrogen or argon gas one or more.
5. the formation method of interconnection structure as claimed in claim 3, is characterized in that, adopt chlorine to carry out in the step of dry etching, power is 100 ~ 2000w, bias voltage is 0 ~ 500w, air pressure is 1 ~ 500mtorr, and the flow of chlorine is 1 ~ 500sccm.
6. the formation method of interconnection structure as claimed in claim 1, it is characterized in that, the step forming the second mask layer in the first opening of described first mask layer comprises: in the first opening of described first mask layer, fill full described second mask layer, and described second mask layer covers described first mask surface;
After described 3rd mask layer of removal, before removing described first mask layer, described formation method also comprises: remove the second mask layer on described first mask layer, until expose described first mask layer.
7. the formation method of interconnection structure as claimed in claim 6, it is characterized in that, the technique removing the second mask layer on described first mask layer is chemical mechanical milling tech.
8. the formation method of interconnection structure as claimed in claim 1, it is characterized in that, the step forming metal level on a semiconductor substrate comprises: adopt electroplating technology to form described metal level.
9. the formation method of interconnection structure as claimed in claim 1, it is characterized in that, the material of described first mask layer is copper nitride.
10. the formation method of interconnection structure as claimed in claim 1, it is characterized in that, the technique removing described first mask layer is wet-etching technology.
The formation method of 11. interconnection structures as claimed in claim 10, is characterized in that, described wet-etching technology adopts hydrogen chloride solution to be wet etchant.
The formation method of 12. interconnection structures as claimed in claim 1, is characterized in that, between described first mask layer and Semiconductor substrate, also comprise barrier layer.
The formation method of 13. interconnection structures as claimed in claim 12, is characterized in that, the material on described barrier layer is silica.
The formation method of 14. interconnection structures as claimed in claim 1, it is characterized in that, described metal level is layers of copper.
The formation method of 15. interconnection structures as claimed in claim 1, it is characterized in that, described formation method also comprises: in the second opening of described metal level, fill interlayer dielectric layer.
The formation method of 16. interconnection structures as claimed in claim 15, is characterized in that, the material of described interlayer dielectric layer is low-K dielectric material or super low-K dielectric material.
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| CN103515308A (en) * | 2012-06-27 | 2014-01-15 | 南亚科技股份有限公司 | Copper interconnect structure and method for fabricating thereof |
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| CN1885522A (en) * | 2005-06-22 | 2006-12-27 | 旺宏电子股份有限公司 | Wire manufacturing method and structure |
| US20080318437A1 (en) * | 2007-06-20 | 2008-12-25 | Kim Chan Bae | Method for manufacturing semiconductor device utilizing low dielectric layer filling gaps between metal lines |
| CN102569168A (en) * | 2010-12-23 | 2012-07-11 | 无锡华润上华半导体有限公司 | Manufacturing method of metal interconnection line |
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