CN104143528A - Inter-connection structure forming method - Google Patents
Inter-connection structure forming method Download PDFInfo
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- CN104143528A CN104143528A CN201310170457.2A CN201310170457A CN104143528A CN 104143528 A CN104143528 A CN 104143528A CN 201310170457 A CN201310170457 A CN 201310170457A CN 104143528 A CN104143528 A CN 104143528A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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Abstract
Disclosed is an inter-connection structure forming method. The method comprises the steps that a semiconductor substrate is provided; an interlayer dielectric layer, a dielectric hard mask layer and a metal hard mask layer are sequentially formed on the semiconductor substrate from bottom to top, wherein the interlayer dielectric layer is made of low-k materials or ultralow-k materials; a first opening is formed in the metal hard mask layer and penetrates through the metal hard mask layer; the remaining metal hard mask layer is adopted as a mask, and the dielectric hard mask layer and the interlayer dielectric layer are etched until an etching structure is formed in the interlayer dielectric layer, wherein the etching structure comprises either a through hole or a groove or the combination of the through hole and the groove; the etching structure is filled with a sacrificial layer; the remaining metal hard mask layer and the sacrificial layer are removed in sequence; the etching structure is filled with metal materials. According to the inter-connection structure forming method, the shape and appearance of a formed metal inter-connection line or metal plug or two-mosaic structure are good, and the performance of a semiconductor device comprising the formed metal inter-connection line or metal plug or two-mosaic structure is good.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of formation method of interconnection structure.
Background technology
Along with very lagre scale integrated circuit (VLSIC) high integration and high performance demand are increased gradually, semiconductor technology is towards the even more technology node development of small-feature-size of 65nm, and the arithmetic speed of chip is obviously subject to the impact that resistance capacitance that metallic conduction causes postpones.
On the one hand, in order to improve the performance of integrated circuit, utilize the copper with advantages such as low-resistivity, good deelectric transferred abilities to replace aluminium as the metal interconnecting wires in semiconductor, can reduce metal interconnected line resistance.
On the other hand, utilize low-k materials or super low-k materials as the interlayer dielectric layer of metal interconnecting wires, can effectively reduce electric capacity.
The metal interlamination medium layer that copper dual-damascene technology collocation low-k materials forms is current most popular interconnection structure process combination, and it can effectively improve the phenomenon that resistance capacitance postpones, and will become the standard interconnect technology of semiconductor technology of future generation.
In existing technique, a kind of formation method of copper dual-damascene structure comprises: Semiconductor substrate is provided, and forms successively from the bottom to top interlayer dielectric layer, medium hard mask layer and metal hard mask layer in described Semiconductor substrate; In described metal hard mask layer, form the first opening that runs through its thickness, the position of described the first opening and shape are corresponding with position and the shape of follow-up formation copper metal interconnecting wires respectively; In described the first opening, form photoresist layer, and form the second opening that runs through its thickness in described photoresist layer, the position of described the second opening and shape are corresponding with position and the shape of follow-up formation copper metal plug respectively; Take metal hard mask layer as mask, the photoresist layer that comprises the second opening, medium hard mask layer and interlayer dielectric layer are carried out to etching, to exposing described Semiconductor substrate, to form groove and the through hole that is positioned at beneath trenches in described interlayer dielectric layer; By wet etching, remove described metal hard mask layer; On described through hole, groove and groove metal hard mask layer around, form copper metal material; Adopt chemical mechanical milling tech to carry out planarization to described copper metal material and dielectric layer hard mask layer, to exposing described interlayer dielectric layer, to form the dual-damascene structure that comprises copper metal interconnecting wires and copper metal plug.
Yet, when the copper dual-damascene structure that above-mentioned technique is formed checks, find: the pattern of the copper dual-damascene structure that forms is poor, and comprises the poor-performing of the semiconductor device of formed copper dual-damascene structure.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of interconnection structure, makes the pattern of formed interconnection structure better, improves the performance of the semiconductor device that comprises formed interconnection structure.
For addressing the above problem, the invention provides a kind of formation method of interconnection structure, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, form successively from the bottom to top interlayer dielectric layer, medium hard mask layer and metal hard mask layer, the material of described interlayer dielectric layer is low-k materials or super low-k materials;
In described metal hard mask layer, form the first opening, described the first opening runs through described metal hard mask layer;
The remaining described metal hard mask layer of take is mask, medium hard mask layer and interlayer dielectric layer described in etching, until form etching structure in described interlayer dielectric layer, described etching structure comprises a kind of or its combination in through hole and groove;
In described etching structure, fill full sacrifice layer;
Remove successively remaining described metal hard mask layer and described sacrifice layer;
In described etching structure, fill full metal material.
Optionally, the material of described metal hard mask layer is titanium nitride, copper nitride or aluminium nitride.
Optionally, the method for removing described metal hard mask layer is wet etching, and the solution of described wet etching is the mixed solution of hydrogen peroxide and acid solution, and described acid solution comprises one or more in hydrofluoric acid, hydrochloric acid and sulfuric acid.
Optionally, the material of described sacrifice layer is bottom anti-reflective material.
Optionally, the method for removing described sacrifice layer is dry etching, and the gas of described dry etching comprises nitrogen or oxygen-containing gas.
Optionally, the material of described sacrifice layer is siliceous antireflection material.
Optionally, the method for removing described sacrifice layer is wet etching, and the solution of described wet etching is the mixed solution of propylene glycol monomethyl ether and propylene glycol monomethyl ether acetate, or is a kind of solution in propylene glycol monomethyl ether, propylene glycol monomethyl ether acetate and CLK888.
Optionally, the material of described sacrifice layer is amorphous carbon.
Optionally, the method for removing described sacrifice layer is cineration technics.
Optionally, the material of described sacrifice layer is that DOU(DOU is a kind of semi-conducting material of Honeywell company), the method of removing described sacrifice layer is wet etching, and the solution of described wet etching is that CLK888(CLK888 is a kind of etching agent of Mallinckrodt Baker company).
Optionally, described etching structure comprises through hole and groove; The remaining described metal hard mask layer of take is mask, medium hard mask layer and interlayer dielectric layer described in etching, until form etching structure in described interlayer dielectric layer, comprise: in described the first opening, form photoresist layer, in described photoresist layer, be formed with the second opening that runs through described photoresist layer thickness; Take described metal hard mask layer and photoresist layer as mask, described interlayer dielectric layer is carried out to etching, to the interlayer dielectric layer of the second opening below residue predetermined thickness; Remove described photoresist layer; Take described metal hard mask layer as mask, and interlayer dielectric layer described in etching, until expose described Semiconductor substrate.
Compared with prior art, technical scheme of the present invention has the following advantages:
Form etching structure in interlayer dielectric layer after; in described interlayer dielectric layer, form the full sacrifice layer of filling in etching structure; in order to protect described interlayer dielectric layer in removing metal hard mask layer process; then remove successively described metal hard mask layer and sacrifice layer; finally in formed etching structure, fill full metal material, to form dual-damascene structure, metal interconnecting wires or the metal plug being formed by metal interconnecting wires and metal plug.In removing metal hard mask layer process; described sacrifice layer can effectively be protected the interlayer dielectric layer being positioned on etching structure sidewall; make the pattern of formed dual-damascene structure, metal interconnecting wires or metal plug better, improved the performance of the semiconductor device that comprises dual-damascene structure, metal interconnecting wires or metal plug.
Accompanying drawing explanation
Fig. 1 to Fig. 8 is the schematic diagram of formation method first embodiment of interconnection structure of the present invention;
Fig. 9 to Figure 12 is the schematic diagram of formation method second embodiment of interconnection structure of the present invention.
Embodiment
Inventor finds through research, it is poor that existing technique forms copper metal plug pattern, the poor-performing that comprises the semiconductor device of copper dual-damascene structure is mainly caused by following reason: in order to reduce the k value of interlayer dielectric layer, conventionally the low-k materials of employing loose structure or super low-k materials are as interlayer dielectric layer, and while removing described metal hard mask layer by wet etching, etching solution easily sees through through hole and interlayer dielectric layer and reacts, destroy described interlayer dielectric layer, and formed through hole and groove are deformed, affected the pattern of the copper dual-damascene structure that forms, also affected the performance of the semiconductor device that comprises copper dual-damascene structure.
Similarly, by above-mentioned technique, form copper metal interconnecting wires or copper metal plug, or when the dual-damascene structure by above-mentioned technique formation other materials, metal interconnecting wires or metal plug, also having the problems referred to above.
For this reason; the invention provides a kind of formation method of interconnection structure; form etching structure in interlayer dielectric layer after; in described interlayer dielectric layer, form the full sacrifice layer of filling in etching structure; described sacrifice layer can be protected described interlayer dielectric layer in removing metal hard mask layer process, avoids the removal technique of metal hard mask layer to cause damage to interlayer dielectric layer.After removing metal hard mask layer, remove sacrifice layer, in etching structure, fill full metal material, form the dual-damascene structure, metal interconnecting wires or the metal plug that by metal interconnecting wires and metal plug, are formed.In removing metal hard mask layer process, because interlayer dielectric layer can not sustain damage, the dual-damascene structure that forms, metal interconnecting wires or metal plug pattern are better, comprise that the performance of semiconductor device of formed dual-damascene structure, metal interconnecting wires or metal plug is better.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
The first embodiment
The present embodiment take that to form dual-damascene structure (being that etching structure comprises groove and through hole simultaneously) be example, and the formation method of interconnection structure of the present invention is described.
With reference to figure 1, Semiconductor substrate 200 is provided, and in described Semiconductor substrate 200, form successively from the bottom to top etching stop layer 202a, interlayer dielectric layer 204a, medium hard mask layer 206a and metal hard mask layer 208.
In the present embodiment, the material of described Semiconductor substrate 200 can well known to a person skilled in the art other materials for monocrystalline silicon, monocrystalline germanium or monocrystalline germanium silicon, silicon-on-insulator, III-V group element compound, monocrystalline silicon carbide etc.
In addition, in described Semiconductor substrate 200, also can be formed with device architecture (not shown), described device architecture can be the device architecture forming in semiconductor FEOL, such as MOS transistor etc.
In the present embodiment, the material of described etching stop layer 202a is to can be silica, silicon nitride, silicon oxynitride, carborundum and containing one or several the combination in carbonitride of silicium, in order to form the stop-layer in groove and via process as etching, avoid etching technics to cause damage to described Semiconductor substrate 200.The material of described interlayer dielectric layer 204a is low-k materials or super low-k materials.The method that forms described interlayer dielectric layer 204a can be chemical vapor deposition method.The material of described medium hard mask layer 206a can be silica, silicon nitride, silicon oxynitride, carborundum and containing one or several the combination in carbonitride of silicium; in order to improve the adhesiveness between the metal hard mask layer 208 of interlayer dielectric layer 204a and follow-up formation; and as the protective layer of interlayer dielectric layer 204a; stop metallic atom in metal hard mask layer 208 to diffuse in interlayer dielectric layer 204a; avoid the k value of interlayer dielectric layer 204a to impact, prevent electric leakage.The method that forms described medium hard mask layer 206a can be chemical vapor deposition method.The material of described metal hard mask layer 208 can be titanium nitride, copper nitride or aluminium nitride.The method that forms described metal hard mask layer 208 is chemical vapor deposition method.
Continuation, with reference to figure 1, forms the first opening 210 in metal hard mask layer 208, and the position of described the first opening 210 and shape are corresponding with position and the shape of metal interconnecting wires in follow-up formation dual-damascene structure respectively.
Concrete, can adopt photoresist layer is mask, and described metal hard mask layer 208 is carried out to etching, forms described the first opening 210.Its concrete technique that forms is well known to those skilled in the art, and does not repeat them here.
With reference to figure 2, at the interior formation photoresist layer 212 of the first opening 210 described in Fig. 1, in described photoresist layer 212, be formed with the second opening 214 that runs through described photoresist layer 212 thickness.
In the present embodiment, the position of described the second opening 214 and shape are corresponding with position and the shape of metal plug in follow-up formation dual-damascene structure respectively.Formation comprises that the method for the photoresist layer 212 of the second opening 214 is well known to those skilled in the art, and does not repeat them here.
With reference to figure 3, take metal hard mask layer described in Fig. 2 208 and photoresist layer 212 is mask, and medium hard mask layer 206a, interlayer dielectric layer 204a are carried out to etching, to the interlayer dielectric layer 204a of the second opening 214 belows residue predetermined thickness; Then remove described photoresist layer 212; Again then, the described metal hard mask layer 208 of take is mask, continues interlayer dielectric layer 204a described in etching, until expose described etching stop layer 202a, to form groove 216 and be positioned at the through hole 218 below groove 216 in described interlayer dielectric layer 204b.
In the present embodiment, the method for medium hard mask layer 206a, interlayer dielectric layer 204a being carried out to etching is dry etching, and as anisotropic dry etch, its concrete etching technics is well known to those skilled in the art, and does not repeat them here.The method of removing described photoresist layer 212 can be cineration technics.
It should be noted that, take metal hard mask layer described in Fig. 2 208 and photoresist layer 212, it is mask, when medium hard mask layer 206a, interlayer dielectric layer 204a are carried out to etching, the thickness of the interlayer dielectric layer 204a of the second opening 214 remaining predetermined thickness in below is corresponding with the degree of depth of follow-up formed groove 216.
Also it should be noted that, in forming groove 216 and through hole 218 processes, the medium hard mask layer 206b that is positioned at hard mask layer 208 belows is not removed.
With reference to figure 4, at groove described in Fig. 3 216 and the full sacrifice layer 220 of the interior filling of through hole 218.
In the present embodiment, the material of described sacrifice layer 220 can be bottom anti-reflective material, amorphous carbon, siliceous antireflection material or DOU.At the full sacrifice layer 220 of groove 216 and the interior filling of through hole 218, can comprise the steps: described groove 216 and through hole 218 in, by medium hard mask layer 206b and metal hard mask layer 208, enclose in the opening forming above groove 216 and groove 216 around metal hard mask layer 208 on form sacrifice layer; Removal is positioned at the sacrifice layer on metal hard mask layer 208.
In the present embodiment, can remove the method that is positioned at the sacrifice layer on metal hard mask layer 208 is chemical mechanical milling tech, also can be dry etch process.When removing by dry etch process the sacrifice layer being positioned on metal hard mask layer 208, described dry etching gas can be nitrogen or oxygen-containing gas.
With reference to figure 5, remove metal hard mask layer 208 described in Fig. 4.
In the present embodiment, the method for removing described metal hard mask layer 208 can be wet etching, and the solution of described wet etching is the mixed solution of hydrogen peroxide and acid solution, and described acid solution comprises one or more in hydrofluoric acid, hydrochloric acid and sulfuric acid.Because the upper surface of interlayer dielectric layer 204b is covered by described medium hard mask layer 206b, and interlayer dielectric layer 204b on groove 216 and through hole 218 sidewalls is sacrificed 220, layer and covers, can avoid the solution of wet etching to cause damage to interlayer dielectric layer 204b, also can avoid the groove 216 that caused by the solution consumption of wet etching because of interlayer dielectric layer 204b and through hole 218 distortion, the pattern of the groove that forms 216 and through hole 218 better.
With reference to figure 6, remove sacrifice layer 220 described in Fig. 5, again expose the groove 216 and the through hole 218 that are arranged in described interlayer dielectric layer 204b.
In the present embodiment, when the material of sacrifice layer 220 is bottom anti-reflective material (BARC), the method for removing sacrifice layer 220 can be wet etching, dry etching or cineration technics.When adopting wet etching to remove described sacrifice layer 220, the solution of wet etching can be the mixed solution of propylene glycol monomethyl ether and propylene glycol monomethyl ether acetate, or is a kind of solution in propylene glycol monomethyl ether, propylene glycol monomethyl ether acetate and CLK888.When adopting dry etching to remove described sacrifice layer 220, the gas of described dry etching can be nitrogen or oxygen-containing gas.
When the material of sacrifice layer 220 is amorphous carbon, the method for removing described sacrifice layer 220 also can be cineration technics.
When the material of sacrifice layer 220 is siliceous antireflection material (Si-ARC), the method of removing sacrifice layer 220 can be wet etching, the solution of described wet etching can be the mixed solution of propylene glycol monomethyl ether and propylene glycol monomethyl ether acetate, or be only propylene glycol monomethyl ether, a kind of solution in propylene glycol monomethyl ether acetate and CLK888.
When the material of described sacrifice layer 220 is DOU, the method for removing described sacrifice layer 220 can be wet etching, and the solution of described wet etching can be CLK888.
In removing sacrifice layer 220 processes, because the etching gas of dry etching in above-mentioned technique is not, the gas of the solution of wet etching or cineration technics can cause damage to interlayer dielectric layer 204b, make the pattern of formed groove 216 and through hole 218 better.
With reference to figure 7, remove the etching stop layer 202a that is positioned at through hole 218 bottoms in Fig. 6, to exposing described Semiconductor substrate 200, to form through hole 219, and residue is positioned at through hole 219 etching stop layer 202b around.
In the present embodiment, remove the method be positioned at through hole 218 bottom etching stop layer 202a and can be dry etching and also can be wet etching.As adopting wet etching removal to be positioned at through hole 218 bottom etching stop layer 202a, the solution of described wet etching can be phosphoric acid solution.Due to the sluggish of phosphoric acid solution and described interlayer dielectric layer 204b, it can be ignored to the damage of interlayer dielectric layer 204b.
With reference to figure 8, in groove described in Fig. 7 216 and through hole 219, fill full metal material, to form respectively metal interconnecting wires 222 and metal plug 224, the common formation dual-damascene structure of described metal interconnecting wires 222 and metal plug 224.
In the present embodiment, described metal material can be copper, and the method that forms copper metal material can be physical gas-phase deposition.Form metal interconnecting wires 222 and metal plug 224 can comprise the steps: groove described in Fig. 7 216 and through hole 219 in and groove 216 around medium hard mask layer 206 on form copper metal material; Adopt chemical mechanical milling tech to carry out planarization to described copper metal material and medium hard mask layer 206, to exposing described interlayer dielectric layer 204b, form copper metal interconnecting wires 222 and copper metal plug 224.
In other embodiments, also can in described groove 216 and through hole 219, fill full other metal materials (as: tungsten, aluminium etc.), to form metal interconnecting wires and the metal plug of other materials, the present invention is not restricted this.
In the present embodiment, fill full metal material in groove 216 and through hole 219 before, first remove and be positioned at groove 216 metal hard mask layer 208 around, the depth-to-width ratio of groove 216 and the depth-to-width ratio of through hole 219 have been reduced, be reduced in the difficulty of filling metal material in groove 216 and through hole 219, improved groove 216 and through hole 219 filling effects.And, the removal technique of metal hard mask layer 208 can not cause damage to dual-damascene structure interlayer dielectric layer 204b around, make the pattern of formed groove 216 and through hole 219 better, and then form and comprise that the dual-damascene structure pattern of metal interconnecting wires 222 and metal plug 224 is also better, effectively improved the performance of the semiconductor device that comprises formed dual-damascene structure.
The second embodiment
The metal plug (being that etching structure only comprises through hole) that the present embodiment be take in single mosaic technology is example, formation method to interconnection structure of the present invention describes, the formation method of metal interconnecting wires (corresponding etching structure only comprises groove) and the formation method of metal plug are similar, at this, do not describe in detail.
With reference to figure 9, Semiconductor substrate 300 is provided, in described Semiconductor substrate 300, form successively from the bottom to top etching stop layer 302a, interlayer dielectric layer 304, medium hard mask layer 306 and metal hard mask layer 308, and form and to run through the first opening (not shown) of described metal hard mask layer 308 and to run through medium hard mask layer 306 and the through hole (not shown) of interlayer dielectric layer 304 simultaneously, then in described through hole, fill full sacrifice layer 312.
In the present embodiment, the material of described Semiconductor substrate 300, etching stop layer 302a, interlayer dielectric layer 304, medium hard mask layer 306, metal hard mask layer 308 and sacrifice layer 312, formation technique please refer to the first embodiment, at this, do not describe in detail.
In other embodiments, also can omit described etching stop layer 302a, in described Semiconductor substrate 300, directly form described interlayer dielectric layer 304.
With reference to Figure 10, remove metal hard mask layer 308 described in Fig. 9.
In the present embodiment, the method for removing metal hard mask layer 308 please refer to the first embodiment, does not repeat them here.Owing to being positioned at interlayer dielectric layer 304 on through-hole side wall, being sacrificed 312, layer and covering, and be positioned at interlayer dielectric layer 304 surfaces on interlayer dielectric layer 304 around through hole, by described medium hard mask layer 306, covered, can avoid the removal technique of metal hard mask layer 308 to cause damage to interlayer dielectric layer 304, improve the performance of formed semiconductor device.
With reference to Figure 11, remove successively sacrifice layer described in Figure 10 312, be positioned at the etching stop layer 302a of sacrifice layer 312 belows, form the through hole 314 that runs through described interlayer dielectric layer 304 and etching stop layer 302b.Specifically can comprise the steps: first to remove sacrifice layer 312 described in Figure 10; Take medium hard mask layer 306 as mask again, and the 302a of etching stop layer described in etching Figure 10, to exposing described Semiconductor substrate 300.
In the present embodiment, the method for removing described sacrifice layer 312 and being positioned at sacrifice layer 312 below etching stop layer 302a please refer to the corresponding steps of the first embodiment.When removing sacrifice layer 312, the etching stop layer 302a that is positioned at sacrifice layer 312 belows can effectively protect Semiconductor substrate 300 to avoid damage.
With reference to Figure 12, in through hole described in Figure 11 314, fill full metal material, form copper metal plug 316.Its specifically can comprise the steps: in through hole described in Figure 10 314 and through hole 314 medium hard mask layer 306 around on form copper metal material; Adopt chemical mechanical milling tech to carry out flatening process to copper metal material and medium hard mask layer 306, to exposing described interlayer dielectric layer 304, form copper metal plug 316.
In the present embodiment, while removing metal hard mask layer 308, interlayer dielectric layer 304 is not caused to damage, and when guaranteeing through hole 314 filling effects, the pattern that makes to be formed at through hole 314 in interlayer dielectric layer 304 is better, and then make the pattern of formed metal plug 316 better, improved the performance of the semiconductor device that comprises formed metal plug 316.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with claim limited range.
Claims (14)
1. a formation method for interconnection structure, is characterized in that, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, form successively from the bottom to top interlayer dielectric layer, medium hard mask layer and metal hard mask layer, the material of described interlayer dielectric layer is low-k materials or super low-k materials;
In described metal hard mask layer, form the first opening, described the first opening runs through described metal hard mask layer;
The remaining described metal hard mask layer of take is mask, medium hard mask layer and interlayer dielectric layer described in etching, until form etching structure in described interlayer dielectric layer, described etching structure comprises a kind of or its combination in through hole and groove;
In described etching structure, fill full sacrifice layer;
Remove successively remaining described metal hard mask layer and described sacrifice layer;
In described etching structure, fill full metal material.
2. the formation method of interconnection structure as claimed in claim 1, is characterized in that, the material of described metal hard mask layer is titanium nitride, copper nitride or aluminium nitride.
3. the formation method of interconnection structure as claimed in claim 2, it is characterized in that, the method of removing described metal hard mask layer is wet etching, the solution of described wet etching is the mixed solution of hydrogen peroxide and acid solution, and described acid solution comprises one or more in hydrofluoric acid, hydrochloric acid and sulfuric acid.
4. the formation method of interconnection structure as claimed in claim 1, is characterized in that, the material of described sacrifice layer is bottom anti-reflective material.
5. the formation method of interconnection structure as claimed in claim 4, is characterized in that, the method for removing described sacrifice layer is dry etching, and the gas of described dry etching comprises nitrogen or oxygen-containing gas.
6. the formation method of interconnection structure as claimed in claim 1, is characterized in that, the material of described sacrifice layer is siliceous antireflection material.
7. the formation method of the interconnection structure as described in claim 4 or 6, it is characterized in that, the method of removing described sacrifice layer is wet etching, the solution of described wet etching is the mixed solution of propylene glycol monomethyl ether and propylene glycol monomethyl ether acetate, or is a kind of solution in propylene glycol monomethyl ether, propylene glycol monomethyl ether acetate and CLK888.
8. the formation method of interconnection structure as claimed in claim 1, is characterized in that, the material of described sacrifice layer is amorphous carbon.
9. the formation method of the interconnection structure as described in claim 4 or 8, is characterized in that, the method for removing described sacrifice layer is cineration technics.
10. the formation method of interconnection structure as claimed in claim 1, is characterized in that, the material of described sacrifice layer is DOU, and the method for removing described sacrifice layer is wet etching, and the solution of described wet etching is CLK888.
The formation method of 11. interconnection structures as claimed in claim 1, is characterized in that, the material of described medium hard mask layer is silica, silicon nitride, silicon oxynitride, carborundum and containing one or several the combination in carbonitride of silicium.
The formation method of 12. interconnection structures as claimed in claim 1, it is characterized in that, form interlayer dielectric layer in described Semiconductor substrate before, also comprise: in described Semiconductor substrate, form etching stop layer, the material of described etching stop layer is silica, silicon nitride, silicon oxynitride, carborundum and containing one or several the combination in carbonitride of silicium.
The formation method of 13. interconnection structures as claimed in claim 1, is characterized in that, described metal material is copper.
The formation method of 14. interconnection structures as claimed in claim 1, is characterized in that, described etching structure comprises through hole and groove; The remaining described metal hard mask layer of take is mask, medium hard mask layer and interlayer dielectric layer described in etching, until form etching structure in described interlayer dielectric layer, comprise: in described the first opening, form photoresist layer, in described photoresist layer, be formed with the second opening that runs through described photoresist layer thickness; Take described metal hard mask layer and photoresist layer as mask, described interlayer dielectric layer is carried out to etching, to the interlayer dielectric layer of the second opening below residue predetermined thickness; Remove described photoresist layer; Take described metal hard mask layer as mask, and interlayer dielectric layer described in etching, until expose described Semiconductor substrate.
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| CN108281427A (en) * | 2017-01-06 | 2018-07-13 | 中芯国际集成电路制造(上海)有限公司 | Flush memory device and its manufacturing method |
| CN112201620A (en) * | 2020-10-27 | 2021-01-08 | 合肥晶合集成电路股份有限公司 | Forming method of metal interconnection structure |
| CN116598194A (en) * | 2023-07-17 | 2023-08-15 | 致真存储(北京)科技有限公司 | Hard mask manufacturing method and memory |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108155145A (en) * | 2016-12-02 | 2018-06-12 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacturing method |
| CN108281427A (en) * | 2017-01-06 | 2018-07-13 | 中芯国际集成电路制造(上海)有限公司 | Flush memory device and its manufacturing method |
| CN112201620A (en) * | 2020-10-27 | 2021-01-08 | 合肥晶合集成电路股份有限公司 | Forming method of metal interconnection structure |
| CN112201620B (en) * | 2020-10-27 | 2024-02-02 | 合肥晶合集成电路股份有限公司 | Forming method of metal interconnection structure |
| CN116598194A (en) * | 2023-07-17 | 2023-08-15 | 致真存储(北京)科技有限公司 | Hard mask manufacturing method and memory |
| CN116598194B (en) * | 2023-07-17 | 2023-09-29 | 致真存储(北京)科技有限公司 | Hard mask manufacturing method and memory |
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