CN104978290B - Multi-channel serial line receiving system - Google Patents
Multi-channel serial line receiving system Download PDFInfo
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- CN104978290B CN104978290B CN201410138629.2A CN201410138629A CN104978290B CN 104978290 B CN104978290 B CN 104978290B CN 201410138629 A CN201410138629 A CN 201410138629A CN 104978290 B CN104978290 B CN 104978290B
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- phase
- circuit
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- clock signal
- data recovery
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Abstract
Multi-channel serial line receiving system provided by the invention includes a clock generating circuit and multiple data receiving channels.The clock generating circuit provides a basic clock signal.The plurality of data receiving channel each receives an input signal and the basic clock signal, and each self-contained phase detecting circuit, multistage a digital clock pulse data recovery circuit and a phase-adjusting circuit.The phase detecting circuit is sampled the input signal with clock signal according to a sampling, to produce signal after a sampling.The multistage digital clock pulse data recovery circuit imposes a digital clock pulse data recovery program to signal after the sampling, to produce a phase adjustment information.The phase-adjusting circuit adjusts the phase of the basic clock signal according to the phase adjustment information, to produce the sampling clock signal.
Description
Technical field
The present invention is related to signal receiving interface, and the circuit frame especially with multi-channel serial line signal receiving interface
Structure is related.
Background technology
With the progress of electronic related technologies, various types of display devices are more and more popularized.Such as television system, computer
The various electronic installations such as system, projector, digital camera, Disc player, mobile phone, or even game machine, nothing are not required to
Want good audio-visual transmission interface.Display port (DisplayPort, DP) be current newest multimedia reception interface it
One.
The front-end functionality block of display port (DP) receiving circuit is presented in Fig. 1.As shown in figure 1, share four pairs of differential images
Data-signal Data#0, Data#1, Data#2, Data#3 input DP receivers, and are respectively provided to analog front circuit
110A~110D.Signal after analog front circuit 110A~110D preliminary treatments is each provided to simulation clock pulse data
(Analog Clock Data Recovery, ACDR) circuit 120A~120D is replied, carries out clock pulse data recovery program, then
Multiplexing is solved into de-multiplexer 130A~130D.
In addition to display port (DP) interface, separately there are several multi-channel serial line (multi-lane serial
Link) the signal receiving interface of formula, such as Serial Advanced Technology attachment (Serial Advanced Technology
Attachment, SATA) and the interconnection of quick perimeter component (Peripheral Component Interconnect Express,
PCIE), also using the circuit framework being similar to shown in Fig. 1.As known to persons of ordinary skill in the technical field of the present invention, mould
The chip area of plan clock pulse data recovery (ACDR) circuit is big and power is high, can jointly cause the whole of such receiving system
Body price and power consumption rise.
The content of the invention
To solve the above problems, the present invention proposes a kind of new multi-channel serial line receiving system, by utilization
Track frequency and the multistage digital clock pulse data recovery circuit of phase it can simulate clock pulse data recovery (ACDR) electricity to substitute simultaneously
Road.It should be noted that idea of the invention can be applicable to various multi-channel serial lines (multi-lane serial link)
The receiving system of formula, its category are not limited with display port (DP) interface.
A specific embodiment according to the present invention be a kind of receiving system, wherein including a clock generating circuit and more
Individual data receiving channel.The clock generating circuit is provided for a basic clock signal.The plurality of data receiving channel is each
An input signal and the basic clock signal are received, and each self-contained phase detecting circuit, a multistage digital clock pulse data are returned
Compound circuit and a phase-adjusting circuit.The phase detecting circuit is to be taken the input signal with clock signal according to a sampling
Sample, to produce signal after a sampling.The multistage digital clock pulse data recovery circuit is to impose a number to signal after the sampling
Word clock pulse data recovery program, to produce a phase adjustment information.The phase-adjusting circuit is to receive phase adjustment letter
Breath and the basic clock signal, and the phase of the basic clock signal is adjusted according to the phase adjustment information, to produce the sampling
With clock signal, used for the phase detecting circuit.
A specific embodiment according to the present invention be a kind of receiving system, wherein including a clock generating circuit and more
Individual data receiving channel.The clock generating circuit is provided for a basic clock signal.The plurality of data receiving channel, each
An input signal and the basic clock signal, and each self-contained phase detecting circuit are received, to according to a sampling clock pulse
Signal samples the input signal, to produce signal after a sampling；One second order digital clock pulse data recovery circuit, includes a ratio
Circuit, for zooming in and out processing to signal after the sampling, produce a phase error signal；One integrating circuit, for being taken to this
Signal carries out Integral Processing after sample, produces a frequency error signal；One adder, for by the frequency error signal and the phase
Error signal is added, and the phase adjustment information generating circuit of a signal errors signal one is produced, for according to the signal errors signal
Determine a phase adjustment information；And a phase-adjusting circuit, to receive the phase adjustment information and the basic clock signal,
And the phase of the basic clock signal is adjusted according to the phase adjustment information, to produce the sampling clock signal, for the phase
Circuit is detected to use.
Brief description of the drawings
For the above objects, features and advantages of the present invention can be become apparent, the tool below in conjunction with accompanying drawing to the present invention
Body embodiment elaborates, wherein：
The front-end functionality block of display port (DP) receiving circuit is presented in Fig. 1.
Fig. 2 is the functional block diagram of the multi-channel serial line receiving system in one embodiment of the invention.
Fig. 3 is the second order digital clock pulse data recovery circuit example illustrated in one embodiment of the invention.
Fig. 4 is the function block of the multi-channel serial line receiving system in another embodiment of the present invention
Figure.
Fig. 5 is to implement example in detail according to one kind of the clock pulse adjustment circuit of the present invention.
Component label instructions in figure：
110A~110D：Analog front circuit
120A~120D：De-multiplexer
130A~130D：Simulate clock pulse data recovery circuit
200、400：Multi-channel serial line receiving system
210、410：Clock generating circuit
221~224,421~424：Data receiving channel
221A~224A, 421A~424A：Analog front circuit
221B~224B, 421B~424B：Phase detecting circuit
221C~224C, 421C~424C：De-multiplexer
221D~224D, 421D~424D：Multistage digital clock pulse data recovery circuit
221E~224E, 421E~424E：Phase-adjusting circuit
291、491：Basic clock signal
292、492：Sampling clock signal
293、493：Signal after sampling
294：Input signal
310：Integrating circuit
320：Ratio circuit
330：Phase adjustment information generating circuit
340：Adder
411：Local oscillated signal generator
412：Multiplexer
413：Phase-frequency detector
414：Multiplexer
415：Clock pulse adjustment circuit
416：Lock detecting circuit
415A：Current pump
415B：Low pass filter
415C：Voltage controlled oscillator
Embodiment
A specific embodiment according to the present invention is a kind of multi-channel serial line receiving system, its functional block diagram
As shown in Figure 2.In practice, multi-channel serial line receiving system 200 can be incorporated into television system, computer screen, throwing
In a variety of electronic installations such as shadow machine, it can also be individually present.It is some below to illustrate by taking the specification of display port (DP) interface as an example, but
Persons of ordinary skill in the technical field of the present invention is it is understood that idea of the invention can be applicable to various multi-channel serial lines
The receiving system of formula, its category are not limited with display port (DP) interface.
As shown in Fig. 2 multi-channel serial line receiving system 200 includes a clock generating circuit 210 and more numbers
According to receiving channel (221~224).It should be noted that although in Fig. 2 using the quantity of data receiving channel equal to four situation as
Example, but scope of the invention not limited to this.Clock generating circuit 210 is providing a basic clock signal 291.In practical application
In, basic clock signal 291 can be a square-wave signal with fixed frequency, and its frequency can be set equal to or close to one
Sampling frequency, that is, the frequency of the input signal to sampled data receiving channel 221~224.For example, clock pulse produces
Circuit 210 can include a phase-locked loop and a local oscillated signal generator.Shaken caused by the local oscillated signal generator
Swing signal and be provided to phase-locked loop, as the input signal of phase-frequency detector therein, vibrated this by phase-locked loop
Signal frequency multiplication simultaneously locks.
Each self-contained analog front circuit (221A~224A) of data receiving channel 221~224, a phase detecting circuit
(221B~224B), a de-multiplexer (221C~224C), a multistage digital clock pulse data recovery circuit (221D~224D) and
One phase-adjusting circuit (221E~224E).Connect if multi-channel serial line receiving system 200 is a display port (DP)
Receive circuit, input analog front circuit 221A~224A respectively be four couples of differential image data signals Data#0, Data#1,
Data#2、Data#3.Each self-contained sample circuits of phase detecting circuit 221B~224B and a phase decision circuitry (are not painted
Show).Illustrate by taking data receiving channel 221 as an example, phase detecting circuit 221B can be provided according to phase-adjusting circuit 221E
Sampling clock signal 292 be inputted signal 294 and sample, to produce signal 293 after a sampling.Then, by solving multiplexing
Device 221C, signal 293 by solution multiplexing and is transferred to multistage digital clock pulse data recovery circuit 221D after sampling.
Then, multistage digital clock pulse data recovery circuit 221D be responsible for signal after sampling 293 is imposed one it is digital when rapid pulse
According to program is replied, to produce a phase adjustment information.More particularly, multistage digital clock pulse data recovery circuit 221D can judge
The phase of current sampling clock signal 292 determines how to adjust sampling clock signal accordingly to be advanced or backward
292 phase, the quality of signal 293 after sampling could be lifted.Phase-adjusting circuit 221E is receiving the phase adjustment information
With basic clock signal 291, and the phase of basic clock signal 291 is adjusted according to the phase adjustment information, used with producing sampling
Clock signal 292, used for phase detecting circuit 221B.It should be noted that phase-adjusting circuit 221B Detailed Operation mode
Known to persons of ordinary skill in the technical field of the present invention, not repeated in this.
In an embodiment, multistage digital clock pulse data recovery circuit 221D~224D is respectively second order as shown in Figure 3
Digital clock pulse data recovery circuit.Second order digital clock pulse data recovery circuit in the present embodiment includes an integrating circuit 310, one
Ratio circuit 320, a phase adjustment information generating circuit 330 and an adder 340.This second order digital clock pulse data recovery electricity
Include phase component (phase component) and frequency content simultaneously in signal 293 after the sampling that road receives
(frequency component).Integrating circuit 310 is used for the frequency of trace signals, eliminates frequency error.In detail, product
Signal after sampling 293 is carried out Integral Processing by parallel circuit 310, and frequency content is converted into phase component, produces frequency error letter
Number.Signal after sampling 293 is zoomed in and out processing by ratio circuit 320, produces phase error signal.Adder 340 misses frequency
Difference signal is added with phase error signal, is produced signal errors signal, is made to include frequency in the phase component of signal errors signal
Error.Finally, phase adjustment information generating circuit 330 is according to the signal errors signal deciding phase adjustment information.It must illustrate
It is that in an embodiment according to the present invention, multistage digital clock pulse data recovery circuit 221D~224D exponent number is not limited with two,
Its internal detailed embodiment is not also limited with that shown in Figure 3.In addition, each multistage digital clock pulse data recovery circuit (221D
~224D) exponent number need not be identical.Different from the single-order numeral clock pulse data recovery circuit for the phase for being only capable of trace signals,
Multistage digital clock pulse data recovery circuit can trace signals simultaneously frequency and phase, therefore when can solve known single order numeral
Arteries and veins data recovery circuit is only capable of providing phasing message, the shortcomings that can not correcting frequency, when being also able to offer and being closer to simulation
The effect of arteries and veins data recovery circuit.In practice, multi-channel serial line receiving system 200 can provide as shown in Figure 1 show
Show the function of port (DP) receiving circuit.Compared to simulation clock pulse data recovery circuit, multistage digital clock pulse data recovery circuit
It is advantageous in that chip area is smaller, and power consumption is relatively low.
Significantly, since multistage digital clock pulse data recovery circuit 221D~224D has the frequency of energy trace signals
The characteristic of rate, even if signal Data#0, Data#1, Data#2, Data#3 frequency are not quite similar, in phase-adjusting circuit 221E
In the case that~224E shares a basic clock signal 291 caused by clock generating circuit 210, data receiving channel 221~
224 remain to each complete arteries and veins data recovery program at that time, without using four groups of clock generating circuits respectively.In other words, it is more
Channel serial line receiving system 200 can be applied to the different situation of frequency of multiple input signals.
Another specific embodiment according to the present invention is also a kind of multi-channel serial line receiving system, its function side
Block figure is depicted in Fig. 4.Multi-channel serial line receiving system 400 includes a clock generating circuit 410 and multiple data
Receiving channel (421~424).Clock generating circuit 410 in this example includes a local oscillated signal generator more than 411, one
Work device 412, a phase-frequency detector 413, a multiplexer 414, a clock pulse adjustment circuit 415 and a lock detecting circuit 416.
One kind that clock pulse adjustment circuit 415 is presented in Fig. 5 implements example in detail.In this example, clock pulse adjustment circuit 415 includes an electric current
Pump 415A, a low pass filter 415B and a voltage controlled oscillator 415C.
When multi-channel serial line receiving system 400 is in first mode, it is local that multiplexer 412 is switched to connection
The output end of oscillator signal generator 411 and an input of phase-frequency detector 413, and the company of being switched to of multiplexer 414
Connect the output end of phase-frequency detector 413 and the input of clock pulse adjustment circuit 415.In that case, voltage controlled oscillator
415C output end is fed back to another input of phase-frequency detector 413, thus makes phase-frequency detector 413 and electricity
Flow pump 415A, low pass filter 415B, voltage controlled oscillator 415C and form a phase-locked loop, and local oscillated signal production can be locked
The oscillator signal that raw device 411 exports, that is, a basic clock signal 491 is produced according to the oscillator signal.Compare Fig. 4 and Fig. 2 can
Find out, multi-channel serial line receiving system 400 in the first mode is equivalent to the multi-channel serial line letter in Fig. 2
Number reception system 200.
When multi-channel serial line receiving system 400 is in second mode, local oscillated signal generator 411 and phase
Position adjustment circuit 421E is deactivated, and multiplexer 412 is switched to connect analog front circuit 421A output end and phase frequency
The input of detector 413.In addition, multistage digital clock pulse data recovery circuit 422D~424D is all each single for one by reorganization state
Exponent number word clock pulse data recovery circuit (such as can be by the ratio circuit 310 disabled in Fig. 3 or integrating circuit 320 is equivalent reaches
Into）.In a second mode, multiplexer 414 is switched to connect first output end and the clock pulse adjustment of phase-frequency detector 413
The input of circuit 415.According to display port (DP) specification, the differential image data signals of four couple when having one section at the beginning
Between be clock signal.In other words, analog front circuit 421A output signal can be clock signal for some time at the beginning.
In that case, voltage controlled oscillator 415C output end is fed back to another input of phase-frequency detector 413, thus
Phase-frequency detector 413 and clock pulse adjustment circuit 415 is formed a phase-locked loop, and analog front circuit 421A can be locked
The clock signal of output.
Detection circuit 416 to be locked judges to have met a locking condition in the phase-locked loop that (such as to fall into one pre- for output frequency
Determine in scope), lock detecting circuit 416 just by multiplexer 414 switch to connection phase detecting circuit 421B output end and when
Arteries and veins adjustment circuit 415, make phase detecting circuit 421B and current pump 415A, low pass filter 415B, voltage controlled oscillator 415C structures
Into a simulation clock pulse data recovery circuit, to produce basic clock signal 491.It should be noted that the phase adjustment electricity being deactivated
Basic clock signal 491 directly can be transferred to phase detecting circuit 421B by road 421E, as sampling clock signal 492, and
Phase detecting circuit 421B output signal 493 will be directly transmitted to rear end after de-multiplexer 421C solution multiplexings
Circuit.In a second mode, the phase-frequency detector 413 not played a role can be deactivated.Above-mentioned simulation clock pulse data recovery
Circuit is the simulation clock pulse data recovery circuit 130A being equivalent in Fig. 1.
As shown in Fig. 2 basic clock signal 491 is also provided to remaining each phase-adjusting circuit (422E~424E), make
To produce the basic clock signal of sampling clock signal.The tune provided according to digital clock pulse data recovery circuit 422D~424D
Whole information, the phase of each self-adjusting basis clock signals 491 of phase-adjusting circuit 422E~424E, a sampling used time is produced respectively
Arteries and veins signal.In display port (DP) configuration, digital clock pulse data recovery circuit 430B~430D effect is in Fig. 3 is substituted
Simulation clock pulse data recovery circuit 320B~320D.Compare Fig. 1 and Fig. 4 can be seen that, it is more logical using above-mentioned signal mode of connection
The serial line receiving system 400 in road is equivalent to a display port (DP) receiving circuit, three signals after difference is only that
Treatment channel is to substitute simulation clock pulse data recovery with digital clock pulse data recovery.
The second mode of multi-channel serial line receiving system 400 is applied to signal Data#0, Data#1, Data#
2nd, the roughly the same situation of Data#3 frequency.In that case, it is switched to single-order numeral clock pulse data recovery circuit
Digital clock pulse data recovery circuit 422D~424D needs only provide for the function of the phase of trace signals.
Although the present invention is disclosed as above with preferred embodiment, so it is not limited to the present invention, any this area skill
Art personnel, without departing from the spirit and scope of the present invention, when a little modification and perfect, therefore the protection model of the present invention can be made
Enclose to work as and be defined by what claims were defined.
Claims (3)
1. a kind of multi-channel serial line receiving system, comprising：
One clock generating circuit, to provide a basic clock signal；And
Multiple data receiving channels, an input signal and the basic clock signal are each received, and it is each self-contained：
One phase detecting circuit, to be sampled the input signal with clock signal according to a sampling, to believe after the sampling of generation one
Number；
One multistage digital clock pulse data recovery circuit, to impose a digital clock pulse data recovery program to signal after the sampling,
To produce a phase adjustment information；And
One phase-adjusting circuit, to receive the phase adjustment information and the basic clock signal, and believed according to the phase adjustment
Breath adjusts the phase of the basic clock signal, to produce the sampling clock signal, is used for the phase detecting circuit；
The clock generating circuit includes a phase-locked loop and a local oscillated signal generator；
The phase-locked loop includes a phase-frequency detector；When the multi-channel serial line receiving system is in one second mould
Formula, the local oscillated signal generator are deactivated, and this of the specific data receiving channel of one in the plurality of data receiving channel is more
Exponent number word clock pulse data recovery circuit is deactivated, and remaining respectively the multistage digital clock pulse data recovery circuit by reorganization state is one single
Exponent number word clock pulse data recovery circuit；When the multi-channel serial line receiving system is in the second mode, the phase is frequently
Rate detector receives the input signal first, and after meeting a locking condition after the phase-locked loop, the phase-frequency detector is stopped
With, and the phase-locked loop changes with the phase detecting circuit link in the specific data receiving channel, rapid pulse when forming a simulation
According to reflex circuit, to produce the basic clock signal；When the multi-channel serial line receiving system is in the second mode,
The phase-adjusting circuit in the specific data receiving channel is deactivated, the basis caused by the simulation clock pulse data recovery circuit
Clock signal is provided to the phase detecting circuit in the specific data receiving channel, as the sampling clock signal, and
The basic clock signal is also provided to remaining respectively phase-adjusting circuit.
2. multi-channel serial line receiving system as claimed in claim 1, it is characterised in that rapid pulse when this is multistage digital
It is a second order digital clock pulse data recovery circuit according to reflex circuit.
3. multi-channel serial line receiving system as claimed in claim 1, it is characterised in that the phase-locked loop includes one
Phase-frequency detector；When the multi-channel serial line receiving system is in a first mode, the phase-frequency detector
A local oscillated signal caused by the local oscillated signal generator is received, and the phase-locked loop is according to the local oscillated signal
Produce the basic clock signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410138629.2A CN104978290B (en) | 2014-04-08 | 2014-04-08 | Multi-channel serial line receiving system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410138629.2A CN104978290B (en) | 2014-04-08 | 2014-04-08 | Multi-channel serial line receiving system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104978290A CN104978290A (en) | 2015-10-14 |
| CN104978290B true CN104978290B (en) | 2018-04-06 |
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|---|---|---|---|
| CN201410138629.2A Expired - Fee Related CN104978290B (en) | 2014-04-08 | 2014-04-08 | Multi-channel serial line receiving system |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499479A (en) * | 2002-11-12 | 2004-05-26 | ���ǵ�����ʽ���� | Sampling phase device for regulating digital displaying device and its regulation method |
| CN101320982A (en) * | 2007-06-06 | 2008-12-10 | 智原科技股份有限公司 | Time sequence reply parameter generation circuit and signal receiving circuit |
| CN102035553A (en) * | 2010-11-15 | 2011-04-27 | 中兴通讯股份有限公司 | Parallel analog-to-digital conversion device and method for controlling deflection of analog-to-digital conversion channels |
| CN103209146A (en) * | 2012-01-11 | 2013-07-17 | 瑞昱半导体股份有限公司 | Signal Equilibrium Apparatus And Method Thereof |
| CN103546403A (en) * | 2012-07-11 | 2014-01-29 | 联咏科技股份有限公司 | Clock data recovery circuit and clock data recovery method |
-
2014
- 2014-04-08 CN CN201410138629.2A patent/CN104978290B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499479A (en) * | 2002-11-12 | 2004-05-26 | ���ǵ�����ʽ���� | Sampling phase device for regulating digital displaying device and its regulation method |
| CN101320982A (en) * | 2007-06-06 | 2008-12-10 | 智原科技股份有限公司 | Time sequence reply parameter generation circuit and signal receiving circuit |
| CN102035553A (en) * | 2010-11-15 | 2011-04-27 | 中兴通讯股份有限公司 | Parallel analog-to-digital conversion device and method for controlling deflection of analog-to-digital conversion channels |
| CN103209146A (en) * | 2012-01-11 | 2013-07-17 | 瑞昱半导体股份有限公司 | Signal Equilibrium Apparatus And Method Thereof |
| CN103546403A (en) * | 2012-07-11 | 2014-01-29 | 联咏科技股份有限公司 | Clock data recovery circuit and clock data recovery method |
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| CN104978290A (en) | 2015-10-14 |
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