CN104378114B - A kind of method for realizing that multipath A/D converter is synchronous - Google Patents
A kind of method for realizing that multipath A/D converter is synchronous Download PDFInfo
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- CN104378114B CN104378114B CN201410571383.8A CN201410571383A CN104378114B CN 104378114 B CN104378114 B CN 104378114B CN 201410571383 A CN201410571383 A CN 201410571383A CN 104378114 B CN104378114 B CN 104378114B
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Abstract
The invention belongs to radar RF signal collection technical field, discloses a kind of method for realizing that multipath A/D converter is synchronous.It comprises the following steps：Configuration multipath A/D converter works in multiple channel test pattern；Multipath A/D converter generates data difference pair and with road clock differential pair, is sent by the data difference pair of each passage and with road clock differential pair to fpga chip；Fpga chip draws corresponding single-ended clock signal and single ended data signal；To delay value corresponding to each data bit configuration of each passage single ended data signal, according to delay value corresponding to the configuration of each data bit of each passage single ended data signal, the signal of each data bit of each passage single ended data signal is subjected to delay process；Serioparallel exchange is carried out to each passage single ended data signal after delay process, obtains corresponding parallel data；According to the phase relation between each channel parallel data, each channel parallel data are subjected to phase alignment.
Description
Technical field
The invention belongs to radar RF signal collection technical field, more particularly to one kind realizes that multipath A/D converter is same
The method of step, it is mainly used in the analog-to-digital conversion of radar radiofrequency signal.
Background technology
Because where the advantage of radar itself (round-the-clock, without environmental requirement etc.), radar imaging technology has obtained widely
Concern and research.Radar imaging technology can be applied to the complex conditions such as night, rainy day, compensate for many of optical imagery not
Foot.
The first step of the collection of radar signal as radar imaging technology, is played vital in whole image forming job
Effect.The quality of the radar echo signal quality collected directly decides the quality for being ultimately imaged result, higher resolution ratio
Higher sampling precision, faster sample rate and bigger sampling bandwidth are needed with higher quality.
It is A/D conversion chips that radar signal, which gathers most important part, i.e. ADC (Analog to Digital
Converter).The higher multi-channel high-speed ADC chips of sample rate generally support multiple-working mode in the industry at present, and with can
DLL, such as the EV10AQ190/EV10AQ190A of E2V companies, support 1 passage, 2 passages, 4 passages and test pattern, tool
There is configurable SPI interface.
For multi-channel high-speed ADC, or multi-disc single channel high-speed ADC is used simultaneously, the phase between its passage is matched somebody with somebody in ADC
May be asynchronous after the completion of putting, this will have a huge impact to imaging results.
The content of the invention
It is an object of the invention to propose a kind of method for realizing that multipath A/D converter is synchronous.
To realize above-mentioned technical purpose, the present invention, which adopts the following technical scheme that, to be achieved.
A kind of method for realizing that multipath A/D converter is synchronous comprises the following steps：
Step 1, multipath A/D converter is configured using fpga chip, it is worked in multiple channel test pattern；It is more logical
The port number of road analog-digital converter is N, and N number of passage of the port number of multipath A/D converter is expressed as the 1st passage extremely
N channel；
Step 2, when multipath A/D converter works in multiple channel test pattern, data difference pair corresponding to generation and with
Road clock differential pair, multipath A/D converter is by the data difference pair of each passage with each passage with road clock differential pair
Send to fpga chip；I-th passage is converted to the i-th passage single-ended clock signal by fpga chip with road clock differential pair, and i takes
1 to N；Fpga chip is by the data difference of the i-th passage to being converted to the i-th passage single ended data signal；
Step 3, fpga chip is to delay value, FPGA corresponding to each data bit configuration of the i-th passage single ended data signal
Chip delay value according to corresponding to configuring each data bit of the i-th passage single ended data signal, by the i-th passage single ended data signal
Each data bit signal carry out delay process；
Step 4, fpga chip carries out serioparallel exchange to the i-th passage single ended data signal after delay process, and it is logical to obtain i-th
Road parallel data；
Step 5, fpga chip enters each channel parallel data according to the phase relation between each channel parallel data
Row phase alignment, draw the parallel data after phase alignment.
Beneficial effects of the present invention are：1) present invention utilizes the IODELAYE modules of fpga chip to multi-channel high-speed ADC
Data carry out fine delay in each passage of (analog-digital converter), avoid in each passage data bit unjustified and burr occur and show
As；2) present invention carries out logic alignment operation to data between multi-channel high-speed ADC (analog-digital converter) each passage, makes each logical
The Phase synchronization of track data, avoid impacting radar imagery result.
Brief description of the drawings
Fig. 1 is that a kind of hardware of method for realizing that multipath A/D converter is synchronous of the present invention realizes structural representation；
Fig. 2 is that a kind of hardware of method for realizing that multipath A/D converter is synchronous of the present invention realizes FPGA cores in structure
The internal structure block diagram of piece；
Fig. 3 is the electricity of ISERDES_Master modules and ISERDES_Slaver modules in each passage ISERDES modules
Even schematic diagram；
Fig. 4 is each inter-channel phase synchronous method schematic flow sheet of the present invention.
Embodiment
The invention will be further described below in conjunction with the accompanying drawings：
With reference to Fig. 1, the hardware for a kind of method for realizing that multipath A/D converter is synchronous of the present invention realizes that structure is shown
It is intended to.In the embodiment of the present invention, the configuration interface of fpga chip electrical connection multipath A/D converter (multi-channel high-speed ADC),
For configuring the mode of operation of multipath A/D converter, be at multiple channel test pattern, normal mode of operation or other
Pattern.For example, it is SPI interface to configure interface.The port number of multipath A/D converter is expressed as N, for multichannel mould
N number of passage (passage 1 to passage N in corresponding diagram 1) of the port number of number converter, each passage is electrically connected by data-interface
The data-interface of fpga chip, each passage electrically connect the clock interface of fpga chip by clock interface, for FPGA cores
Piece sends differential data pair and differential clocks pair.
With reference to Fig. 2, the hardware for a kind of method for realizing that multipath A/D converter is synchronous of the present invention is realized in structure
The internal structure block diagram of fpga chip.A kind of method for realizing that multipath A/D converter is synchronous of the present invention includes following step
Suddenly：
Step 1, multipath A/D converter is configured using fpga chip, it is worked in multiple channel test pattern.It is more logical
The port number of road analog-digital converter is expressed as N, and N number of passage of the port number of multipath A/D converter is expressed as the 1st and led to
Road is to N channel.Specifically, configuration interface of the fpga chip to multipath A/D converter sends corresponding configuration signal,
Multipath A/D converter is set to work in multiple channel test pattern.
Step 2, when multipath A/D converter works in multiple channel test pattern, data difference pair corresponding to generation and with
Road clock differential pair.Multipath A/D converter is according to the sequential logic with road clock and data, by each passage by data
Differential pair and sent with road clock differential pair to fpga chip.Fpga chip will be come from more logical using its internal logical resource
The passage of road analog-digital converter i-th is converted to the i-th passage single-ended clock signal with road clock differential pair, and i takes 1 to N.It is same with this
When, fpga chip is using its internal logical resource, by the data difference from the passage of multipath A/D converter i-th to conversion
For the i-th passage single ended data signal.In the embodiment of the present invention, it is in the form of LVDS logic levels with road clock and data
It is existing.
For example, be internally provided with the i-th passage in fpga chip and turn single-ended block with road clock difference, the i-th passage with
Road clock difference turn single-ended block electrical connection multipath A/D converter the i-th channel clock interface, for by the i-th passage with
Road clock differential pair is converted to the i-th passage single-ended clock signal.The i-th channel data difference, which is internally provided with, in fpga chip turns single
End module, the i-th channel data difference turn the i-th channel data interface of single-ended block electrical connection multipath A/D converter, are used for
By the data difference of the i-th passage to being converted to the i-th passage single ended data signal.
It is single-ended to the i-th passage after fpga chip Zai Jiangsui roads clock differential pair is converted to the i-th passage single-ended clock signal
Clock signal carries out m scaling down processings, obtains the i-th passage sub-frequency clock signal, and 1<m<8.
Step 3, fpga chip is to delay value, FPGA corresponding to each data bit configuration of the i-th passage single ended data signal
Chip delay value according to corresponding to configuring each data bit of the i-th passage single ended data signal, by the i-th passage single ended data signal
Each data bit signal carry out delay process.
For example, be provided with the i-th passage IODELAYE modules in fpga chip, the i-th passage IODELAYE modules it is defeated
Enter the output end that end the i-th channel data difference of electrical connection turns single-ended block, for receiving the i-th passage single ended data signal.I-th is logical
Road IODELAYE modules receive the i-th passage sub-frequency clock signal while the i-th passage single ended data signal is received.
In the embodiment of the present invention, the effect of the i-th passage IODELAYE modules is the every of the i-th passage single ended data signal of fine setting
Phase relation between individual data bit.I-th passage IODELAYE modules have three kinds of mode of operations："FIXED"、"VARIABLE"
With " VAR_LOADABLE ", " FIXED " pattern is used in of the invention, under " FIXED " pattern, the i-th passage IODELAYE
Delay between the input and output of module is fixed value, and the fixed value is by being configured to the correspondences of the i-th passage IODELAYE modules
The delay value of IDELAY_VALUE ports determines.
In the embodiment of the present invention, the delay of the corresponding IDELAY_VALUE ports of the i-th passage IODELAYE modules is configured to
The unit of value is tap；Need the tap values (how many individual tap) of delay being configured to IODELAYE corresponding IDELAY_ when in use
VALUE ports, in the fpga chip of different series, the scopes of IDELAY_VALUE port values be it is different, every 1 tap with it is defeated
Enter the reference clock frequency f of the i-th passage IODELAYE modulesrefRelevant, physical relationship is as follows：
1tap=1/ (32 × 2 × fref)
It should be noted that if stringent synchronization between each data bit of the i-th passage single ended data signal, matches somebody with somebody
The each IDELAY_VALUE ports delay value put to the i-th passage IODELAYE modules is 0tap.
Step 4, fpga chip is gone here and there to the i-th passage single ended data signal (showing as serial data) after delay process
And change, obtain the i-th channel parallel data.
For example, with reference to Fig. 2, the i-th passage ISERDES modules are provided with fpga chip.I-th passage ISERDES moulds
The input of block is electrically connected the output end of the i-th passage IODELAYE modules and the i-th passage turns single-ended mould with road clock difference
The output end of block, for the i-th passage single ended data signal and the i-th passage single-ended clock signal after reception delay processing.I-th is logical
Road ISERDES modules reception delay processing after the i-th passage single ended data signal and the i-th passage single-ended clock signal it is same
When, receive the i-th passage sub-frequency clock signal.
In the embodiment of the present invention, the i-th passage ISERDES modules according to serioparallel exchange be actually needed determine exampleization one or
Two ISERDES primitive, each ISERDES examples primitive could support up 1:6 string and data conversion.If after actual requirement conversion
Parallel data bit wide it is wider, then need two ISERDES primitive of exampleization, and it is ISERDES_Master moulds to configure one of them
Block (Master patterns), another is ISERDES_Slaver modules (Slave patterns).Reference picture 3, it is the i-th passage ISERDES
The schematic diagram that is electrically connected of ISERDES_Master modules and ISERDES_Slaver modules in module.For ISERDES_Master moulds
Block and ISERDES_Slaver modules, Q1 ports to Q6 ports are provided with each module, D ports, CLK ends are provided with each module
Mouth, CLKDIV ports, SHIFTIN1 ports, SHIFTIN2 ports, SHIFTOUT1 ports and SHIFTOUT2 ports.ISERDES_
The CLK ports of the CLK ports electrical connection ISERDES_Slaver modules of Master modules, ISERDES_Master modules
CLKDIV ports electrically connect the CLKDIV ports of ISERDES_Slaver modules, the SHIFTOUT1 of ISERDES_Master modules
Port electrically connects the SHIFTIN1 ports of ISERDES_Slaver modules, the SHIFTOUT2 ports of ISERDES_Master modules
Electrically connect the SHIFTIN2 ports of ISERDES_Slaver modules.
For example, as the model EV10AQ190A of multipath A/D converter, the highest of the multipath A/D converter
Sample clock frequency is 2.5GHz, and the sample rate of each passage can arrive 1.25Gsps, and the data of the multipath A/D converter are equal
Fpga chip is transferred to LVDS signal ddr modes, therefore every passage is 625MHz with road clock frequency, the clock frequency is not
Beneficial to processing of the data in fpga chip, it is therefore desirable to it will be divided (m=4) with road clock four, and two ISERDES originals of exampleization
Language.The clock and its four frequency-dividing clocks are inputted to the CLK ports and CLKDIV ports of ISERDES modules respectively, will be delayed micro-
The D ports of data input ISERDES_Master after tune, by 1:Data after 8 serioparallel exchanges are from two ISERDES Q ends
Mouth output, the clock frequency from the output of Q ports is 156.25MHz.
Step 5, fpga chip enters each channel parallel data according to the phase relation between each channel parallel data
Row phase alignment, draw the parallel data after phase alignment.
Specifically, multipath A/D converter generally supports test pattern, when multipath A/D converter works in
During multiple channel test pattern, each passage of multipath A/D converter need not input analog signal, and it is special to circulate output
The integer sequence of measured length.For example, model EV10AQ190A multipath A/D converter automatic cycle output 0~1023.
Reference picture 4, for each inter-channel phase synchronous method schematic flow sheet of the present invention.Fpga chip by each passage simultaneously
The process that row data carry out phase alignment includes following sub-step：
(5.1) parallel data of each passage is converted to the system number of respective channel 10 by fpga chip, then relatively more each
The size of the system number of passage 10.If each system number of passage 10 is identical, then it is assumed that each channel parallel data have been alignd, and are performed
Sub-step (5.4)；Otherwise, using the passage of numerical value minimum (delay of numerical value minimum specification front-end path is most long) as reference channel,
Rest channels carry out phase alignment by standard of the reference channel, now, jump to sub-step (5.2).
(5.2) difference of remaining each system number of passage 10 of current time and the system number of reference channel 10 is calculated, if its
The remaining system number of any passage 10 and the absolute value of the difference of the system number of reference channel 10 are more than given threshold, then are back to sub-step
(5.1)；Otherwise, according to the difference of the system number of respective channel 10 and the system number of reference channel 10, show that respective channel is logical with reference
Phase relation between road, then, jump to sub-step (5.3).In the embodiment of the present invention, given threshold is 6 to 8.
(5.3) phase relation between the respective channel and reference channel that are drawn according to sub-step (5.2), by respective channel
Parallel data be delayed after corresponding time and export, then perform sub-step (5.4)
(5.4) multipath A/D converter is configured to normal mode of operation, multipath A/D converter starts to input
Analog signal carry out analog-to-digital conversion, now the phase close alignment between each channel data.
The hardware specific implementation method of step 5 is exemplified below, alignment of data module, data are provided with fpga chip
The input of alignment module is electrically connected the parallel data output end (ISERDES_Master of each passage ISERDES modules
The Q ports of module and ISERDES_Slaver modules), the input of alignment of data module is electrically connected each passage
The sub-frequency clock signal output end of ISERDES modules, alignment of data module are used to receive the parallel of each passage ISERDES modules
The sub-frequency clock signal of data and each passage ISERDES modules.
Alignment of data module is carried out each channel parallel data according to the phase relation between each channel parallel data
Phase alignment.Alignment of data module electrically connects the IDELAY_VALUE ports of each passage IODELAYE modules, in sub-step
(5.3) in, the phase relation between respective channel and reference channel that alignment of data module is drawn according to sub-step (5.2), match somebody with somebody
Put the delay value of the IDELAY_VALUE ports of each passage IODELAYE modules, respective channel IODELAYE modules are by input
Single ended data signal enters line delay output.
Step 6, after step 5, (it is, for example, the repetition letter that radar provides when fpga chip receives outer triggering signal
Number) when, when writing corresponding to generation can signal, fpga chip according to when writing can signal, to the parallel data progress after phase alignment
Caching.
For example, fpga chip is provided with energy generation module when writing, and energy generation module is used to receive external trigger when writing
Signal, can signal during for writing corresponding to being produced according to outer triggering signal.Fpga chip is provided with fifo module, fifo module
Be electrically connected when writing can the output end of generation module and the output end of data alignment module, when being write for receiving can signal, with
And the sub-frequency clock signal from alignment of data module.Fifo module is according to energy signal when writing, to after phase alignment and line number
According to being cached, fifo module writes clock frequency of the clock for the parallel data after phase alignment, and reading clock then can basis
Actual requirement configures
Obviously, those skilled in the art can carry out the essence of various changes and modification without departing from the present invention to the present invention
God and scope.So, if these modifications and variations of the present invention belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising including these changes and modification.
Claims (4)
- A kind of 1. method for realizing that multipath A/D converter is synchronous, it is characterised in that comprise the following steps：Step 1, multipath A/D converter is configured using fpga chip, it is worked in multiple channel test pattern；Multichannel mould The port number of number converter is N, and N number of passage of the port number of multipath A/D converter is expressed as the 1st passage and led to N Road；Step 2, when multipath A/D converter works in multiple channel test pattern, data difference pair corresponding to generation and during with road Clock differential pair, multipath A/D converter send the data difference pair of each passage with each passage with road clock differential pair To fpga chip；I-th passage is converted to the i-th passage single-ended clock signal by fpga chip with road clock differential pair, i take 1 to N；Fpga chip is by the data difference of the i-th passage to being converted to the i-th passage single ended data signal；Step 3, fpga chip is to delay value, fpga chip corresponding to each data bit configuration of the i-th passage single ended data signal According to delay value corresponding to the configuration of each data bit of the i-th passage single ended data signal, by the every of the i-th passage single ended data signal The signal of individual data bit carries out delay process；Step 4, fpga chip carries out serioparallel exchange to the i-th passage single ended data signal after delay process, obtains the i-th passage simultaneously Row data；Step 5, each channel parallel data are carried out phase by fpga chip according to the phase relation between each channel parallel data Position alignment, draws the parallel data after phase alignment.
- A kind of 2. method for realizing that multipath A/D converter is synchronous as claimed in claim 1, it is characterised in that the step 5 specific sub-step is：(5.1) parallel data of each passage is converted to the system number of respective channel 10 by fpga chip, then more each passage The size of 10 system numbers；If each system number of passage 10 is identical, sub-step (5.4) is performed；Otherwise, by the minimum passage of numerical value As reference channel, sub-step (5.2) is jumped to；(5.2) difference of remaining each system number of passage 10 of current time and the system number of reference channel 10 is calculated, if remaining is appointed The system number of one passage 10 and the absolute value of the difference of the system number of reference channel 10 are more than given threshold, then are back to sub-step (5.1)；Otherwise, according to the difference of the system number of respective channel 10 and the system number of reference channel 10, show that respective channel is logical with reference Phase relation between road, then, jump to sub-step (5.3)；(5.3) phase relation between the respective channel and reference channel that are drawn according to sub-step (5.2), by respective channel and Row data delay exports after the corresponding time, then performs sub-step (5.4)；(5.4) multipath A/D converter is configured to normal mode of operation, multipath A/D converter starts the mould to input Intend signal and carry out analog-to-digital conversion.
- 3. a kind of method for realizing that multipath A/D converter is synchronous as claimed in claim 2, it is characterised in that in sub-step (5.2) in, the given threshold is 6 to 8.
- 4. a kind of method for realizing that multipath A/D converter is synchronous as claimed in claim 1, it is characterised in that in step 5 Afterwards, when fpga chip receives outer triggering signal, energy signal, fpga chip can be believed according to when writing when being write corresponding to generation Number, the parallel data after phase alignment is cached.
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