CN104978290A - Multichannel serial wired signal receiving system - Google Patents
Multichannel serial wired signal receiving system Download PDFInfo
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- CN104978290A CN104978290A CN201410138629.2A CN201410138629A CN104978290A CN 104978290 A CN104978290 A CN 104978290A CN 201410138629 A CN201410138629 A CN 201410138629A CN 104978290 A CN104978290 A CN 104978290A
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Abstract
The invention provides a multichannel serial wired signal receiving system, which comprises a clock generation circuit and a plurality of data receiving channels, wherein the clock generation circuit provides a basic clock signal; the data receiving channels independently receive an input signal and the basic clock signal and independently comprise a phase detection circuit, a multi-order digital clock data reply circuit and a phase regulation circuit; the phase detection circuit samples the input signal according to a clock signal used for sampling so as to generate a post-sampling signal; the multi-order digital clock data reply circuit applies a data clock data reply program to the sampled signal to generate phase regulation information; and the phase regulation circuit regulates the phase of the basic clock signal according to the phase regulation information to generate the clock signal used for the sampling.
Description
Technical field
The present invention is relevant to Signal reception interface, and especially relevant to the circuit framework of multi-channel serial line Signal reception interface.
Background technology
Along with the progress of electronic related technologies, various types of display device is more and more universal.Such as television system, computer system, projector, digital camera, Disc player, mobile phone, and even the various electronic installation such as game machine, need good audio-visual transmission interface invariably.Display port (DisplayPort, DP) is one of current up-to-date multimedia reception interface.
Fig. 1 presents the front-end functionality block of display port (DP) receiving circuit.As shown in Figure 1, have four and DP receiver is inputted to differential image data signals Data#0, Data#1, Data#2, Data#3, and be provided to analog front circuit 110A ~ 110D respectively.Signal after analog front circuit 110A ~ 110D rough handling is provided to simulation clock pulse data recovery (Analog Clock Data Recovery separately, ACDR) circuit 120A ~ 120D, carry out clock pulse data recovery program, enter de-multiplexer 130A ~ 130D subsequently and separate multiplex (MUX).
Except display port (DP) interface, separately there is the Signal reception interface of several multi-channel serial lines (multi-lane seriallink) formula, such as Serial Advanced Technology attachment (Serial Advanced TechnologyAttachment, and quick peripheral assembly interconnect (Peripheral Component InterconnectExpress SATA), PCIE), also employing is similar to the circuit framework shown in Fig. 1.Known to persons of ordinary skill in the technical field of the present invention, the chip area of simulation clock pulse data recovery (ACDR) circuit is large and power is high, and the overall price of this type of receiving system and power consumption can be made jointly to increase.
Summary of the invention
For solving the problem, the present invention proposes a kind of new multi-channel serial line receiving system, and the multistage digital clock pulse data recovery circuit by track frequency while of utilization energy and phase place replaces simulation clock pulse data recovery (ACDR) circuit.Should be noted that, concept of the present invention can be applicable to the receiving system of various multi-channel serial line (multi-lane serial link) formula, and its category is not limited with display port (DP) interface.
A specific embodiment according to the present invention is a kind of receiving system, wherein comprises a clock generating circuit and multiple data receiving channel.This clock generating circuit provides a basic clock signal.The plurality of data receiving channel receives an input signal and this basic clock signal separately, and each self-contained phase detecting circuit, multistage digital clock pulse data recovery circuit and a phase-adjusting circuit.This phase detecting circuit is in order to be sampled by this input signal according to a sampling clock signal, to produce signal after a sampling.This multistage digital clock pulse data recovery circuit is in order to impose a digital clock pulse data recovery program to signal after this sampling, to produce a phase place adjustment information.This phase-adjusting circuit receives this phase place adjustment information and this basic clock signal, and adjust the phase place of this basic clock signal according to this phase place adjustment information, to produce this sampling clock signal, for this phase detecting circuit.
A specific embodiment according to the present invention is a kind of receiving system, wherein comprises a clock generating circuit and multiple data receiving channel.This clock generating circuit provides a basic clock signal.The plurality of data receiving channel, separately receives an input signal and this basic clock signal, and each self-contained phase detecting circuit, in order to be sampled by this input signal according to a sampling clock signal, to produce signal after a sampling; One second order digital clock pulse data recovery circuit, comprises a ratio circuit, for carrying out convergent-divergent process to signal after this sampling, produces a phase error signal; One integrating circuit, for carrying out Integral Processing to signal after this sampling, produces a frequency error signal; One totalizer, for this frequency error signal and this phase error signal being added, producing a signal errors signal one phase place adjustment information and producing circuit, for according to this signal errors signal deciding one phase place adjustment information; And a phase-adjusting circuit, in order to receive this phase place adjustment information and this basic clock signal, and adjust the phase place of this basic clock signal according to this phase place adjustment information, to produce this sampling clock signal, for this phase detecting circuit.
Accompanying drawing explanation
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is elaborated, wherein:
Fig. 1 presents the front-end functionality block of display port (DP) receiving circuit.
Fig. 2 is the functional block diagram according to the multi-channel serial line receiving system in one embodiment of the invention.
Fig. 3 illustrates the second order digital clock pulse data recovery circuit example according in one embodiment of the invention.
Fig. 4 be according to another embodiment of the present invention in the functional block diagram of multi-channel serial line receiving system.
Fig. 5 implements example in detail according to the one of clock pulse Circuit tuning of the present invention.
In figure, element numbers illustrates:
110A ~ 110D: analog front circuit
120A ~ 120D: de-multiplexer
130A ~ 130D: simulation clock pulse data recovery circuit
200,400: multi-channel serial line receiving system
210,410: clock generating circuit
221 ~ 224,421 ~ 424: data receiving channel
221A ~ 224A, 421A ~ 424A: analog front circuit
221B ~ 224B, 421B ~ 424B: phase detecting circuit
221C ~ 224C, 421C ~ 424C: de-multiplexer
221D ~ 224D, 421D ~ 424D: multistage digital clock pulse data recovery circuit
221E ~ 224E, 421E ~ 424E: phase-adjusting circuit
291,491: basic clock signal
292,492: sampling clock signal
293,493: signal after sampling
294: input signal
310: integrating circuit
320: ratio circuit
330: phase place adjustment information produces circuit
340: totalizer
411: local oscillated signal generator
412: multiplexer
413: phase-frequency detector
414: multiplexer
415: clock pulse Circuit tuning
416: lock detecting circuit
415A: current pump
415B: low-pass filter
415C: voltage controlled oscillator
Embodiment
A specific embodiment according to the present invention is a kind of multi-channel serial line receiving system, and its functional block diagram as shown in Figure 2.In practice, multi-channel serial line receiving system 200 can be incorporated in the multiple electronic installations such as television system, computer screen, projector, also can independently exist.Some illustrates for the specification of display port (DP) interface below, but persons of ordinary skill in the technical field of the present invention can understand, concept of the present invention can be applicable to the receiving system of various multi-channel serial line-connection type, and its category is not limited with display port (DP) interface.
As shown in Figure 2, multi-channel serial line receiving system 200 comprises a clock generating circuit 210 and multiple data receiving channel (221 ~ 224).Should be noted that, although equal the situation of four for the quantity of data receiving channel in Fig. 2, category of the present invention is not limited thereto.Clock generating circuit 210 is in order to provide a basic clock signal 291.In practical application, basic clock signal 291 can be the square-wave signal that has fixed frequency, and its frequency can be set equal to or close to a sampling frequency, namely in order to the frequency of the input signal of sampled data receiving cable 221 ~ 224.For example, clock generating circuit 210 can comprise a phase-locked loop and a local oscillated signal generator.The oscillator signal that this local oscillated signal generator produces is provided to phase-locked loop, as the input signal of phase-frequency detector wherein, this oscillator signal frequency multiplication is locked by phase-locked loop.
The each self-contained analog front circuit (221A ~ 224A) of data receiving channel 221 ~ 224, a phase detecting circuit (221B ~ 224B), a de-multiplexer (221C ~ 224C), multistage digital clock pulse data recovery circuit (221D ~ 224D) and a phase-adjusting circuit (221E ~ 224E).If multi-channel serial line receiving system 200 is a display port (DP) receiving circuit, what input analog front circuit 221A ~ 224A respectively is four to differential image data signals Data#0, Data#1, Data#2, Data#3.The each self-contained sample circuit of phase detecting circuit 221B ~ 224B and a phase place decision circuitry (not illustrating).Illustrate for data receiving channel 221, its input signal 294 samples by the sampling clock signal 292 that phase detecting circuit 221B can provide according to phase-adjusting circuit 221E, to produce signal 293 after a sampling.Then, by de-multiplexer 221C, after sampling, signal 293 is separated multiplex (MUX) and is passed to multistage digital clock pulse data recovery circuit 221D.
Subsequently, multistage digital clock pulse data recovery circuit 221D is responsible for imposing a digital clock pulse data recovery program, to produce a phase place adjustment information to signal 293 after sampling.More particularly, multistage digital clock pulse data recovery circuit 221D can judge that the phase place of current sampling clock signal 292 is as advanced or backward, and determine the phase place how adjusting sampling clock signal 292 accordingly, the quality of the rear signal 293 of sampling could be promoted.Phase-adjusting circuit 221E in order to receive this phase place adjustment information and basic clock signal 291, and adjusts the phase place of basic clock signal 291 according to this phase place adjustment information, to produce sampling clock signal 292, for phase detecting circuit 221B.Should be noted that, the Detailed Operation mode of phase-adjusting circuit 221B, known to persons of ordinary skill in the technical field of the present invention, does not repeat in this.
In an embodiment, multistage digital clock pulse data recovery circuit 221D ~ 224D is second order digital clock pulse data recovery circuit as shown in Figure 3 separately.Second order digital clock pulse data recovery circuit in the present embodiment comprises integrating circuit 310, ratio circuit 320, phase place adjustment information and produces circuit 330 and a totalizer 340.Include phase component (phase component) and frequency content (frequency component) in signal 293 after the sampling that this second order digital clock pulse data recovery circuit receives simultaneously.Integrating circuit 310, for the frequency of trace signals, eliminates frequency error.In detail, signal 293 after sampling is carried out Integral Processing by integrating circuit 310, and frequency content is converted to phase component, produces frequency error signal.Signal 293 after sampling is carried out convergent-divergent process by ratio circuit 320, produces phase error signal.Frequency error signal and phase error signal are added by totalizer 340, produce signal errors signal, make to comprise frequency error in the phase component of signal errors signal.Finally, phase place adjustment information produces circuit 330 according to this signal errors signal deciding phase place adjustment information.Should be noted that, in an embodiment according to the present invention, the exponent number of multistage digital clock pulse data recovery circuit 221D ~ 224D is not limited with two, and its inner detailed embodiment is not also limited with that shown in Figure 3.In addition, the exponent number of each multistage digital clock pulse data recovery circuit (221D ~ 224D) need not be identical.Being different from only can the single-order numeral clock pulse data recovery circuit of phase place of trace signals, multistage digital clock pulse data recovery circuit can the frequency of trace signals and phase place simultaneously, therefore known single order numeral clock pulse data recovery circuit can be solved and only phase correction message can be provided, cannot the shortcoming of emending frequency, also provided comparatively close to the effect of simulation clock pulse data recovery circuit.In practice, multi-channel serial line receiving system 200 can provide the function of display port (DP) receiving circuit as shown in Figure 1.Compared to simulation clock pulse data recovery circuit, the benefit of multistage digital clock pulse data recovery circuit is that chip area is less, and power consumption is lower.
It should be noted that, there is due to multistage digital clock pulse data recovery circuit 221D ~ 224D the characteristic of the frequency of energy trace signals, even if the frequency of signal Data#0, Data#1, Data#2, Data#3 is not quite similar, when phase-adjusting circuit 221E ~ 224E shares one basic clock signal 291 of clock generating circuit 210 generation, data receiving channel 221 ~ 224 still can complete its clock pulse data recovery program separately, and does not need to use four groups of clock generating circuits respectively.Easy speech it, multi-channel serial line receiving system 200 can be applied to the different situation of the frequency of multiple input signal.
Also be a kind of multi-channel serial line receiving system according to another specific embodiment of the present invention, its functional block diagram is illustrated in Fig. 4.Multi-channel serial line receiving system 400 comprises a clock generating circuit 410 and multiple data receiving channel (421 ~ 424).Clock generating circuit 410 in this example comprises local oscillated signal generator 411, multiplexer 412, phase-frequency detector 413, multiplexer 414, clock pulse Circuit tuning 415 and a lock detecting circuit 416.The one that Fig. 5 presents clock pulse Circuit tuning 415 implements example in detail.In this example, clock pulse Circuit tuning 415 comprises a current pump 415A, a low-pass filter 415B and a voltage controlled oscillator 415C.
When multi-channel serial line receiving system 400 is in first mode, multiplexer 412 is switched to and connects the output terminal of local oscillated signal generator 411 and an input end of phase-frequency detector 413, and multiplexer 414 is switched to the connection output terminal of phase-frequency detector 413 and the input end of clock pulse Circuit tuning 415.In that case, the output terminal of voltage controlled oscillator 415C is by another input end of feedbacking to phase-frequency detector 413, thus phase-frequency detector 413 and current pump 415A, low-pass filter 415B, voltage controlled oscillator 415C is made to form a phase-locked loop, and the oscillator signal that local oscillated signal generator 411 exports can be locked, that is produce a basic clock signal 491 according to this oscillator signal.Comparison diagram 4 and Fig. 2 can find out, multi-channel serial line receiving system 400 is in a first mode equivalent to the multi-channel serial line receiving system 200 in Fig. 2.
When multi-channel serial line receiving system 400 is in the second pattern, local oscillated signal generator 411 and phase-adjusting circuit 421E are deactivated, and multiplexer 412 is switched to the output terminal of connecting analog front-end circuit 421A and the input end of phase-frequency detector 413.In addition, multistage digital clock pulse data recovery circuit 422D ~ 424D is a single-order numeral clock pulse data recovery circuit (such as can by the ratio circuit 310 in inactive Fig. 3 or integrating circuit 320 is equivalent reaches) by reorganization state all separately.In a second mode, first multiplexer 414 is switched to and connects the output terminal of phase-frequency detector 413 and the input end of clock pulse Circuit tuning 415.According to display port (DP) specification, the differential image data signals of this four couple can be clock signal at the beginning for some time.Easy speech it, the output signal of analog front circuit 421A can be clock signal at the beginning for some time.In that case, the output terminal of voltage controlled oscillator 415C is by another input end of feedbacking to phase-frequency detector 413, thus make phase-frequency detector 413 and clock pulse Circuit tuning 415 form a phase-locked loop, and the clock signal of analog front circuit 421A output can be locked.
Testing circuit 416 to be locked judges that this phase-locked loop has met a locking condition (such as output frequency falls in a preset range), multiplexer 414 is just switched to the output terminal and clock pulse Circuit tuning 415 that connect phase detecting circuit 421B by lock detecting circuit 416, phase detecting circuit 421B and current pump 415A, low-pass filter 415B, voltage controlled oscillator 415C is made to form a simulation clock pulse data recovery circuit, to produce basic clock signal 491.Should be noted that, basic clock signal 491 directly can be passed to phase detecting circuit 421B by the phase-adjusting circuit 421E be deactivated, as sampling clock signal 492, and the output signal 493 of phase detecting circuit 421B is after de-multiplexer 421C separates multiplex (MUX), just directly back-end circuit can be passed to.In a second mode, the phase-frequency detector 413 do not played a role can be deactivated.Namely above-mentioned simulation clock pulse data recovery circuit is equivalent to the simulation clock pulse data recovery circuit 130A in Fig. 1.
As shown in Figure 2, basic clock signal 491 is also provided to all the other each phase-adjusting circuits (422E ~ 424E), as the basic clock signal producing sampling clock signal.According to the adjustment information that digital clock pulse data recovery circuit 422D ~ 424D provides, the phase place of phase-adjusting circuit 422E ~ 424E each self-adjusting basis clock signal 491, produces a sampling clock signal respectively.In display port (DP) configuration, the effect of digital clock pulse data recovery circuit 430B ~ 430D is to replace the simulation clock pulse data recovery circuit 320B ~ 320D in Fig. 3.Comparison diagram 1 and Fig. 4 can find out, adopt above-mentioned signal mode of connection, namely multi-channel serial line receiving system 400 is equivalent to a display port (DP) receiving circuit, and difference is only that rear three signal processing channels replace simulation clock pulse data recovery with digital clock pulse data recovery.
Second pattern of multi-channel serial line receiving system 400 is applicable to the roughly the same situation of the frequency of signal Data#0, Data#1, Data#2, Data#3.In that case, the digital clock pulse data recovery circuit 422D ~ 424D being switched to single-order numeral clock pulse data recovery circuit only needs the function of the phase place providing trace signals.
Although the present invention discloses as above with preferred embodiment; so itself and be not used to limit the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when doing a little amendment and perfect, therefore protection scope of the present invention is when being as the criterion of defining with claims.
Claims (9)
1. a multi-channel serial line receiving system, comprises:
One clock generating circuit, in order to provide a basic clock signal; And
Multiple data receiving channel, receives an input signal and this basic clock signal separately, and each self-contained:
One phase detecting circuit, in order to be sampled by this input signal according to a sampling clock signal, to produce signal after a sampling;
One multistage digital clock pulse data recovery circuit, in order to impose a digital clock pulse data recovery program to signal after this sampling, to produce a phase place adjustment information; And
One phase-adjusting circuit, in order to receive this phase place adjustment information and this basic clock signal, and adjusts the phase place of this basic clock signal, to produce this sampling clock signal, for this phase detecting circuit according to this phase place adjustment information.
2. multi-channel serial line receiving system as claimed in claim 1, it is characterized in that, this multistage digital clock pulse data recovery circuit is a second order digital clock pulse data recovery circuit.
3. multi-channel serial line receiving system as claimed in claim 1, it is characterized in that, this clock generating circuit comprises a phase-locked loop and a local oscillated signal generator.
4. multi-channel serial line receiving system as claimed in claim 3, it is characterized in that, this phase-locked loop comprises a phase-frequency detector; When this multi-channel serial line receiving system is in a first mode, this phase-frequency detector receives the local oscillated signal that this local oscillated signal generator produces, and this phase-locked loop produces this basic clock signal according to this local oscillated signal.
5. multi-channel serial line receiving system as claimed in claim 3, it is characterized in that, this phase-locked loop comprises a phase-frequency detector; When this multi-channel serial line receiving system is in one second pattern, this local oscillated signal generator is deactivated, this multistage digital clock pulse data recovery circuit of a particular data receiving cable in the plurality of data receiving channel is deactivated, and all the other respectively this multistage digital clock pulse data recovery circuit is reorganized state is a single-order numeral clock pulse data recovery circuit; When this multi-channel serial line receiving system is in this second pattern, first this phase-frequency detector receives this input signal, meet after a locking condition until this phase-locked loop, this phase-frequency detector is deactivated, and this phase-locked loop changes and links with this phase detecting circuit in this particular data receiving cable, form a simulation clock pulse data recovery circuit, to produce this basic clock signal; When this multi-channel serial line receiving system is in this second pattern, this phase-adjusting circuit in this particular data receiving cable is deactivated, this basic clock signal that this simulation clock pulse data recovery circuit produces is provided to this phase detecting circuit in this particular data receiving cable, as this sampling clock signal, and this basic clock signal is also provided to all the other respectively these phase-adjusting circuits.
6. a multi-channel serial line receiving system, comprises:
One clock generating circuit, in order to provide a basic clock signal; And
Multiple data receiving channel, receives an input signal and this basic clock signal separately, and each self-contained:
One phase detecting circuit, in order to be sampled by this input signal according to a sampling clock signal, to produce signal after a sampling;
One second order digital clock pulse data recovery circuit, comprises:
One ratio circuit, for carrying out convergent-divergent process to signal after this sampling, produces a phase error signal;
One integrating circuit, for carrying out Integral Processing to signal after this sampling, produces a frequency error signal;
One totalizer, for this frequency error signal and this phase error signal being added, produces a signal errors signal; And
One phase place adjustment information produces circuit, for according to this signal errors signal deciding one phase place adjustment information; And
One phase-adjusting circuit, in order to receive this phase place adjustment information and this basic clock signal, and adjusts the phase place of this basic clock signal, to produce this sampling clock signal, for this phase detecting circuit according to this phase place adjustment information.
7. multi-channel serial line receiving system as claimed in claim 6, it is characterized in that, this clock generating circuit comprises a phase-locked loop and a local oscillated signal generator.
8. multi-channel serial line receiving system as claimed in claim 7, it is characterized in that, this phase-locked loop comprises a phase-frequency detector; When this multi-channel serial line receiving system is in a first mode, this phase-frequency detector receives the local oscillated signal that this local oscillated signal generator produces, and this phase-locked loop produces this basic clock signal according to this local oscillated signal.
9. multi-channel serial line receiving system as claimed in claim 7, it is characterized in that, this phase-locked loop comprises a phase-frequency detector; When this multi-channel serial line receiving system is in one second pattern, this local oscillated signal generator is deactivated, this ratio circuit in this second order digital clock pulse data recovery circuit in the plurality of data receiving channel and this integrating circuit one of them be deactivated; When this multi-channel serial line receiving system is in this second pattern, first this phase-frequency detector receives this input signal, meet after a locking condition until this phase-locked loop, this phase-frequency detector is deactivated, and this phase-locked loop changes and links with this phase detecting circuit in this particular data receiving cable, form a simulation clock pulse data recovery circuit, to produce this basic clock signal; When this multi-channel serial line receiving system is in this second pattern, this phase-adjusting circuit in this particular data receiving cable is deactivated, this basic clock signal that this simulation clock pulse data recovery circuit produces is provided to this phase detecting circuit in this particular data receiving cable, as this sampling clock signal, and this basic clock signal is also provided to all the other respectively these phase-adjusting circuits.
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| CN201410138629.2A CN104978290B (en) | 2014-04-08 | 2014-04-08 | Multi-channel serial line receiving system |
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| CN201410138629.2A CN104978290B (en) | 2014-04-08 | 2014-04-08 | Multi-channel serial line receiving system |
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| CN1499479A (en) * | 2002-11-12 | 2004-05-26 | ���ǵ�����ʽ���� | Sampling phase device for regulating digital displaying device and its regulation method |
| CN101320982A (en) * | 2007-06-06 | 2008-12-10 | 智原科技股份有限公司 | Time sequence reply parameter generation circuit and signal receiving circuit |
| CN102035553A (en) * | 2010-11-15 | 2011-04-27 | 中兴通讯股份有限公司 | Parallel analog-to-digital conversion device and method for controlling deflection of analog-to-digital conversion channels |
| CN103209146A (en) * | 2012-01-11 | 2013-07-17 | 瑞昱半导体股份有限公司 | Signal Equilibrium Apparatus And Method Thereof |
| CN103546403A (en) * | 2012-07-11 | 2014-01-29 | 联咏科技股份有限公司 | Clock data recovery circuit and clock data recovery method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499479A (en) * | 2002-11-12 | 2004-05-26 | ���ǵ�����ʽ���� | Sampling phase device for regulating digital displaying device and its regulation method |
| CN101320982A (en) * | 2007-06-06 | 2008-12-10 | 智原科技股份有限公司 | Time sequence reply parameter generation circuit and signal receiving circuit |
| CN102035553A (en) * | 2010-11-15 | 2011-04-27 | 中兴通讯股份有限公司 | Parallel analog-to-digital conversion device and method for controlling deflection of analog-to-digital conversion channels |
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