CN104955765A - MEMS device manufacturing method - Google Patents

MEMS device manufacturing method Download PDF

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Publication number
CN104955765A
CN104955765A CN201380071919.3A CN201380071919A CN104955765A CN 104955765 A CN104955765 A CN 104955765A CN 201380071919 A CN201380071919 A CN 201380071919A CN 104955765 A CN104955765 A CN 104955765A
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Prior art keywords
amorphous carbon
carbon film
manufacture method
insulating support
support layer
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CN201380071919.3A
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CN104955765B (en
Inventor
林声圭
金暎洙
金熙渊
姜敏浩
吴在燮
李贵鲁
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Korea Advanced Institute of Science and Technology KAIST
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Korea Advanced Institute of Science and Technology KAIST
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00555Achieving a desired geometry, i.e. controlling etch rates, anisotropy or selectivity
    • B81C1/00595Control etch selectivity
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2203/00Basic microelectromechanical structures
    • B81B2203/01Suspended structures, i.e. structures allowing a movement
    • B81B2203/0109Bridges
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00Manufacture or treatment of microstructural devices or systems
    • B81C2201/01Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0102Surface micromachining
    • B81C2201/0105Sacrificial layer
    • B81C2201/0109Sacrificial layers not provided for in B81C2201/0107 - B81C2201/0108
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00Manufacture or treatment of microstructural devices or systems
    • B81C2201/01Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0128Processes for removing material
    • B81C2201/013Etching
    • B81C2201/0133Wet etching

Abstract

An MEMS device manufacturing method using an amorphous carbon film as a sacrificial layer is provided. According to an embodiment of the present invention, a lower structure is formed. An amorphous carbon film is formed as a sacrificial layer on the lower structure. An upper structure including a sensor structure is formed on the amorphous carbon film. The amorphous carbon film is removed so that the lower structure and the upper structure are spaced apart from each other.

Description

MEMS manufacture method
Technical field
The present invention relates to semiconductor devices, particularly relate to MEMS (MEMS:Micro ElectroMechanical Systems-microelectromechanical systems) device and manufacture method thereof.
Background technology
In general, MEMS refers to element parts, sensor, actuator, electronic circuit integrated to the device on a silicon substrate, as current product sold, comprise printer head, pressure sensor, acceleration transducer, free gyroscope, DMD (projecting apparatus) etc.
Major part utilizes semiconductor procedures and makes, but because semiconductor integrated circuit is with the program making of processing plane, need three-dimensional shape be formed, comprise sacrifice layer (sacrificial layer) etching program do not used in the making of semiconductor integrated circuit.This program be use sacrifice layer and works film and on a silicon substrate pattern structure thing apperance and eliminate sacrifice layer and make the method for works.As the sacrifice layer in this fixing lower electrode or the space between substructure thing and superstructure, generally use silica gel or organic matter and polyimides (Polyimide).
Summary of the invention
(technical problem that will solve)
But, during this MEMS in the past makes, if during using silica gel as sacrifice layer, although and etching selectivity between oxide-film is outstanding, but the etching selectivity between the metal such as nitride film or tungsten is also bad, if using polyimides as sacrifice layer, a large amount of impurity can be contained, during subsequent technique, main stripping (Lift off) method that low temperature carries out and the problem causing quality to reduce of using.
The object of the invention is to, in order to solve comprise as described in multiple problem points of problem points, a kind of MEMS and manufacture method are provided, there is the outstanding etching selectivity between the inorganic matter of multiple kind, the thickness of film easily can be adjusted according to device, in performance and apperance, more outstanding than MEMS in the past, semiconductor technology in the past can also be applied flexibly.But this technical problem is exemplary, scope of the present invention is therefore not limited.(means of dealing with problems)
MEMS manufacture method according to a viewpoint of the present invention is provided.Described MEMS manufacture method, comprises, following steps: the step forming substructure thing; As sacrifice layer, described substructure thing forms the step of amorphous carbon film; Described amorphous carbon film is formed the step of insulating support layer; Described insulating support layer forms etching protective film, once etches described insulating support layer and described amorphous carbon film, through described insulating support layer and described amorphous carbon film and form the step of the multiple vias exposing described substructure thing; Described insulating support layer is formed the step comprising the superstructure of sensor construction; Form the step of at least one through hole of through described insulating support layer; And eliminate whole described amorphous carbon film by described multiple through hole, make the step that described substructure thing and described superstructure are arranged mutually isolatedly.
According to described manufacture method, the step of described formation amorphous carbon film can utilize chemical vapour deposition (CVD) (CVD) to realize.
According to described manufacture method, the step of described elimination amorphous carbon film can comprise dry-etching mode.And then described dry-etching mode can utilize oxygen O 2plasma (Plasma) realizes.
According to described manufacture method, the step of described formation superstructure, also comprises: the step forming insulating support layer on described amorphous carbon film.
According to described manufacture method, after the step of the multiple via of described formation, also comprise: on described multiple lower electrode, form multiple metal anchors and make the step that it is connected with described multiple lower electrode by described multiple via.
According to described manufacture method, the step of described formation superstructure, also comprises: the step forming absorbed layer on described insulating support layer.
According to described manufacture method, described substructure thing, can comprise: for controlling the readable integrated circuit (ROIC) of described sensor construction.
According to described manufacture method, described sensor construction can comprise infrared ray sensor.
According to described manufacture method, described through described insulating support layer and described amorphous carbon film and form the step of the multiple vias exposing described substructure thing, realize by a photoetching process.(effect of invention)
A kind of MEMS can be presented according to one embodiment of the invention constituted as described, with the inorganic matter of multiple kind, also there is outstanding etching selectivity, the thickness of film easily can be adjusted according to device, in performance and apperance, more outstanding than MEMS in the past, semiconductor technology in the past can be applied flexibly.Certainly, scope of the present invention is not limited to this effect.
Accompanying drawing explanation
Fig. 1 to Fig. 6 is the profile diagrammatically illustrating MEMS according to one embodiment of the invention and manufacture method thereof.
Fig. 7 is the profile of the MEMS diagrammatically illustrating according to another embodiment of the present invention and manufacture.
Fig. 8 to Figure 11 is the profile of the manufacture method of the MEMS illustrated according to another embodiment of the present invention.
Detailed description of the invention
Below, embodiments of the present invention will be described in detail with reference to the accompanying drawings.But the present invention is not subject to the restriction of the embodiment of following discloses, can be rendered as different variforms, following examples just in order to the present invention discloses complete, intactly inform category of the present invention to the people with general knowledge.Further, in order to the facility illustrated, likely expand or reduce the size of inscape in accompanying drawing.
Fig. 1 to Fig. 6 is the profile diagrammatically illustrating MEMS according to one embodiment of the invention and manufacture method thereof.
With reference to Fig. 1, substructure thing 12 can be provided.Such as, substructure thing 12 can comprise suitable logical circuit, such as readable integrated circuit (Read Out Integrated Circuit; ROIC).Readable integrated circuit by forming cmos element and manufacturing on substrate.And then substructure thing 12 also can comprise: the insulating barrier 15 on substrate and the lower electrode 14b on insulating barrier 15 and reflecting layer 14c.
Lower electrode 14b connects loop element in logical circuit and sensor element with can be used for electrical resistance.Lower electrode 14b can be formed highlightedly or be formed with metal level landfill after formation channel patterns in insulating barrier 15 on insulating barrier 15.Reflecting layer 14c can be used for being reflected into the light being mapped to substructure thing 12.Especially, realize the method for embedding of lower electrode 14b and reflecting layer 14c after forming channel patterns if be used in insulating barrier 15 with metal level landfill, when amorphous carbon film described later is formed according to chemical vapour deposition (CVD), highly beneficial in flattening.
With reference to Fig. 2, sacrifice layer 16 can be formed on substructure thing 12.Sacrifice layer 16 for supporting superstructure described later (23 of Fig. 6) on substructure thing 12, but finally can be eliminated at least partially or all.Such as, sacrifice layer 16 can comprise amorphous carbon film.
Such as, this sacrifice layer 16 can utilize chemical vapour deposition (CVD) (Chemical Vapor Deposition; CVD) formed.Amorphous carbon film 16 can according to multiple technologies evaporation, but because of cost benefit and membrane property adjustable, plasma enhanced chemical vapor evaporation (plasmaen hanced CVD can be used; PECVD) method etc.In plasma enhanced chemical vapor deposition, the helium of gas and argon etc. can be started to importing the material that comprises aqueous or vaporous carbonization hydrogen in carrier gas (carrier gas) and importing in chamber as plasma.Plasma is disseminated to the CH-free radical generating filter gas in chamber, is tied to the substrate surface being positioned at chamber with filtering the CH-free-radical chemistry of gas and forms a-C:H film on a surface of a substrate.In one embodiment of the invention, as above-mentioned, can be used in the method for embedding realizing lower electrode 14b and reflecting layer 14c after forming channel patterns in insulating barrier 15 with metal level landfill, at this moment, the sacrifice layer 16 be made up of amorphous carbon film is without the need to implementing the other flattening process as CMP.If evaporation amorphous carbon film on uneven lower metal structures thing also flattens amorphous carbon film by CMP, because the adhesion between metal and amorphous carbon film is bad, can produce and peel off (peeling).
Therefore, the rear technique (back-end process) such as the formation process of this sacrifice layer 16 and the metal wiring technique of semiconductor element can and deposit.That is, sacrifice layer 16 can utilize be not MEMS technology semiconductor element in the past manufacture time utilize rear technique and formed.Therefore, after substructure thing 12 is formed, be directly suitable for applicable most technology and carry out sacrifice layer 16 and smithcraft afterwards in technique after semiconductor in the past, thus can manufacturing cost be reduced and be easy to a large amount of production.
On the contrary, if use the material such as polyimides to form sacrifice layer 16, because of the problem such as absorption again of moisture, will use because being not easily suitable for high-temperature technology in follow-up metal evaporation technique is not stripping (Lift off) the mode evaporation metal of CVD mode.At this moment, stepcoverage is not outstanding, and the inside of metal can retain a large amount of impurity.
But, in this embodiment, in mesophilic range, CVD can be used in about 200 DEG C to 600 DEG C and forms sacrifice layer 16 with amorphous carbon film.At this moment, CVD can be utilized afterwards to perform metal evaporation technique.The stepcoverage (Step Coverage) of CVD is outstanding, outstanding in the apperance and electrical characteristic of distribution, can improve the reliability of metal evaporation technique.
In addition, consider that the isolation distance of substructure thing 12 and superstructure and elimination are afterwards born, suitably can select the thickness of sacrifice layer 16.Such as, as in the MEMS structure of this embodiment, the thickness of sacrifice layer 16 can be selected in the scope of 0.5 to 5 μm.Just, this scope can be not limited in another embodiment and select the thickness of sacrifice layer 16.
Optionally, sacrifice layer 16 can form insulating support layer 17.Such as, CVD can be utilized and form insulating support layer 17 with oxide-film.
With reference to Fig. 3, patterning insulating support layer 17 and sacrifice layer 16 according to a photoetching process and the sacrifice layer 16d and insulating support layer 17a with multiple via 19 can be formed simultaneously.Such as, multiple via 19 utilizes photoetching and forms photoetching agent pattern, this photoetching agent pattern is etching protective film and etches formation insulating support layer 17 and sacrifice layer 16 simultaneously.Such as, multiple via 19 can be formed as exposing multiple lower electrode 14b, multiple lower electrode 14b can be utilized as the passage be connected with superstructure afterwards.If sacrifice layer 16 is made up of organic polyimides, in order to form multiple via 19, according to the 1st photoetching process after etch sacrificial layer 16, to etch insulating support layer 17 according to the 2nd photoetching process in addition.This is because outgas (outgassing) can be there is in the polyimides exposed according to described 1st photoetching process, before described 2nd photoetching process, also need the other technique covering the part exposing polyimides.But, according to the manufacture method provided in embodiments of the invention, because sacrifice layer 16 is made up of amorphous carbon film, the problem of above-mentioned outgas can not be produced, therefore, without the need to preventing exposing of amorphous carbon film in etch process, disposable according to a photoetching process, etch insulating support layer 17 and sacrifice layer 16 simultaneously.Sacrifice layer 16 not only to be prevented the problem points such as the impurity above-mentioned moisture reabsorption, bad stepcoverage, subsequent technique from polyimides by inventor instead of amorphous carbon film, and then, utilize the characteristic of amorphous carbon film and formed in the technique of multiple via 19, the number of times of photoetching process is reduced to 1 time from 2 times and has reduced manufacturing expense widely.
With reference to Fig. 4, form multiple metal anchors 21 and can be connected with multiple lower electrode 14b by multiple via 19.Such as, utilize CVD and on the multiple lower electrode 14b exposed by multiple via 19, form metal level, by patterning this and form multiple metal anchors 21.As this metal level, it can be tungsten (W) layer etc.This multiple metal anchors 21 can utilize blank card, and multiple lower electrode 14b electrical resistance is connected to superstructure.
With reference to Fig. 5, superstructure can be formed on sacrifice layer 16d.Such as, the result thing forming multiple metal anchors 21 forms absorbed layer 22, absorbed layer 22 is formed sensor construction 23.Absorbed layer 22 patternable is for comprising multiple hole.Such as, absorbed layer 22 can comprise and can absorb ultrared metal.
Sensor construction 23 can comprise the multiple sensors for MEMS structure, such as infrared ray sensor, UV sensor, x-ray sensors, laser sensor etc.Such as, infrared ray sensor can comprise resistive element, thermocouple etc.The situation comprising the bolometer (bolometer) of resistive element is, the material that resistance changes according to absorbed infrared ray degree, such as noncrystalline silica gel, barium oxide etc.
With reference to Fig. 6, the 2nd insulating support layer 25 can be formed on sensor construction 23.Such as, the 2nd insulating support layer 25 can comprise oxide-film.
Then, multiple through holes 27 of through 2nd insulating support layer 25, sensor construction 23, absorbed layer 22 and insulating support layer 17a can be formed.Such as, multiple through hole 27 can utilize photoetching technique and form photoetching agent pattern, etches formation the 2nd insulating support layer 25, sensor construction 23, absorbed layer 22 and insulating support layer 17a with this photoetching agent pattern for etching protective film.The number of multiple through hole 27 is considered the etching speed of sacrifice layer 16d and suitably can be selected from one or scope more than it.The shape of multiple through hole 27 can be deformed into various shape, can realize cantilever (cantilever) pattern according to multiple through hole 27.
Then, eliminate sacrifice layer 16d by this multiple through hole 27 and limit empty space C.The space C of this sky makes infrared ray be reflected by reflecting layer 14c and back into being mapped to sensor construction 23, thus contributes to improving infrared ray absorbing efficiency.
Such as, when sacrifice layer 16d is amorphous carbon film, Wet-type etching or dry-etching can be utilized and etch sacrificial layer 16d.Just, if utilize Wet-type etching, static friction (stiction) can occur, but dry-etching can not produce this problem.Such as, dry-etching can utilize oxygen O 2plasma (Plasma) and realizing.
The MEMS of such formation can comprise substructure thing 12 and comprise the superstructure of sensor construction 23.The space C of sky eliminating sacrifice layer 16,16d can be had between substructure thing 12 and sensor construction 23.Sensor construction 23 is connected to multiple lower electrode 14b to electrical resistance by multiple metal anchors 21.Accordingly, sensor construction 23 is mutually structurally connected as readable integrated circuit with the logical circuit of substructure thing 12 and forms MEMS.This MEMS can comprise multiple sensors structure, such as infrared ray sensor, UV sensor, x-ray sensors, laser sensor etc.
Fig. 7 is the profile diagrammatically illustrating the MEMS manufactured according to another embodiment of the present invention.
With reference to Fig. 7, in the 1st substrate 12a, lower electrode 14 can be formed.Lower electrode 14 by injecting the impurity of the 2nd conductivity type and heat-treating the 1st substrate 12a and formed in the 1st substrate 12a of the 1st conductivity type.Here, the 1st conductivity type and the 2nd conductivity type can be respectively N-shaped and p-type, or in contrast.Further, in variant embodiment, also can not form lower electrode 14 in the 1st substrate 12a, and outstanding to be arranged on the 1st substrate 12a.
Amorphous carbon film pattern 16c can be formed on a part of 1st substrate 12a.And, on the remainder of the 1st substrate 12a, there is not amorphous carbon film pattern 16c.Such as, amorphous carbon film pattern 16c can be formed as exposing at least partially of the 1st substrate 12a being positioned at the upper side of lower electrode 14 and the periphery of lower electrode 14.Amorphous carbon film pattern 16c is furnished with the 2nd substrate 18a and upper electrode 20.Upper electrode 20 can be arranged to the position relative with lower electrode 14.Therefore, lower electrode 14 can be arranged to according to upper electrode 20 and amorphous carbon film pattern 16c and isolate.Certainly, amorphous carbon film pattern 16c can not be mingled with between lower electrode 14 and upper electrode 20.
In order to the facility illustrated, by the above-mentioned works called after substructure thing comprising the 1st substrate 12a and/or lower electrode 14, the works called after superstructure of the 2nd substrate 18a and/or upper electrode 20 will be comprised.At this moment, superstructure and substructure thing can be arranged to according to amorphous carbon film pattern 16c and isolate.
As previously mentioned, on the 1st substrate 12a and amorphous carbon film pattern 16c, superstructure can be arranged.Superstructure, except the 2nd substrate 18a and upper electrode 20, also can comprise solder joints layer 24 and packaging cover layer 26.2nd substrate 18a is equivalent to device layer in MEMS.The thickness of device layer can be adjusted arbitrarily, can have a variform structure.And the 2nd substrate 18a can comprise upper electrode 20, upper electrode 20 injects the material of the 2nd conductivity type at the set position of the 2nd substrate 18a, heat-treats and formed the 2nd substrate 18a.Upper electrode 20 can be formed at through amorphous carbon film pattern 16c and the position relative with lower electrode 14.
Upper electrode 20 is equivalent to the thickness d 1 of amorphous carbon film pattern 16c with the isolation distance of lower electrode 14.Therefore, upper electrode 20 can be formed as can changing its position on lower electrode 14.
Be respectively the upper electrode 20 of conductive plate and lower electrode 14 mutually side by side relatively time, the value that the area of capacitivity and relative two electrodes that the electric capacity between two electrodes can be similar to the medium turned between two electrodes is directly proportional and isolation distance d1 between two electrodes is inversely proportional to.If two electrodes relatively up and down and/or left and right there is relative movement, the interval between two electrodes or the area of overlap can change and cause static capacity to change.Therefore, if export the change of this static capacity for electrical resistance signal, the relative displacement between two electrodes can be measured.
2nd substrate 18a can arrange packaging cover layer 26.Packaging cover layer 26 plays the effect from outer protection MEMS.The inside 28 of packaging cover layer 26 is salable and maintain vacuum.Solder joints layer 24 can be mingled with between 2nd substrate 18a and packaging cover layer 26.Solder joints layer 24 can comprise in gold, silver, copper, tin, indium and silica gel at least more than one.
And then, MEMS also comprises through electrode 32, through 1st substrate 12a and/or amorphous carbon film pattern 16c and being connected with making lower electrode 14 and/or upper electrode 20 and external electrical, the bottom surfaces of the 1st substrate 12a also comprises electric conductivity pad 34, with through electrode 32 electrical resistance be connected.According to profile direction, illustrate upper electrode 20 and be separated with the 2nd substrate 18a in Fig. 1 of profile, but in fact have and be interconnected and the structure supported, therefore through electrode 32 can be connected to electrical resistance with upper electrode 20.The conductive material of through electrode 32 is formed, the materials such as such as copper, tungsten and aluminium.
Such as, the MEMS according to this embodiment can be utilized as gyro sensor, but the scope of this embodiment is not limited thereto.
Fig. 8 to Figure 11 is the profile of the manufacturing process of the MEMS diagrammatically illustrated according to another embodiment of the present invention.
With reference to Fig. 8, first prepare the 1st substrate 12.1st substrate 12 can be silicon substrate, can comprise multiple semiconductor substance, such as IV race semiconductor, Group III-V compound semiconductor or II-VI group oxide semiconductor.Such as, IV race semiconductor, except silica gel, also comprises germanium or silica gel-germanium.The kind of substrate can be made up of gallium-arsyl plate, ceramic substrate, quartz base plate and display glass substrate etc.
Secondly, in the 1st substrate 12, inject impurity, the 1st substrate 12 is heat-treated and forms lower electrode 14.If inject impurity and form lower electrode 14, lower electrode 14 can not protrude in the upper side of the 1st substrate 12 and be formed in the 1st substrate 12.The lower electrode 14 of such formation has the grade (level) identical with the upper side of the upper side of lower electrode 14 and the 1st substrate 12.In addition, in the embodiment of distortion, lower electrode 14 can be arranged on the 1st substrate 12a outstanding.
The technique injecting impurity can comprise ion implantation technology or doping process.Inject the technique of impurity, can use as PH 3, AsH 3deng N-shaped impurity source or BF 3, BCl 3etc. p-type impurity source.At this moment, lower electrode 14 can have the characteristic of the outstanding conductor of conduction.
Substrate 12a can be formed amorphous carbon film and as sacrifice layer.With reference to Fig. 9, amorphous carbon film 16 can be formed on the 1st substrate 12 that inside forms lower electrode 14.Formed in the step of described amorphous carbon film 16, can chemical vapour deposition (CVD) be utilized and form amorphous carbon film 16.Amorphous carbon film 16 can according to multiple technologies evaporation, but because of cost benefit and membrane property adjustable, plasma enhanced chemical vapor evaporation (PECVD) method etc. can be used.
The temperature implementing this chemical vapour deposition (CVD) is 200 DEG C to 600 DEG C.Such as, if by argon with being diluent gas, substrate temperature reduces to low temperature when evaporation, 300 DEG C according to appointment.The lower temperature for the treatment of substrate can reduce the heat load (thermal budget) of program, can protect the device be formed on substrate when alloy moves.Further, technique is realized at identical with technique after semiconductor temperature.Therefore, it is possible to make full use of the technology used in semiconductor technology in the past, manufacturing cost can be reduced.
With reference to Figure 10, superstructure can be formed on the 1st substrate 12 and amorphous carbon film 16.Superstructure can comprise the 2nd substrate 18a and upper electrode 20.2nd substrate 18a can be silicon substrate etc.2nd substrate 18a is equivalent to device layer in MEMS.By the joint of silicon substrate and/or slimming (thinning) and at random the thickness of adjusting device layer, such as, can have the scope of 10 μm to 100 μm.Then, the 2nd substrate 18a implements exposure, etching and cleaning.Such as, described etch process is implemented by so-called DeepRIE (Reactive Ion Etching-reactive ion etching) mode.
2nd substrate 18a can comprise the set works of variform.Such as, inject impurity to the set position of the 2nd substrate 18a and the 2nd substrate 18a heat-treated and forms upper electrode 20.The technique injecting impurity can comprise ion implantation technology or doping process.In addition, the technique injecting impurity can use as PH 3, AsH 3deng N-shaped impurity source or BF 3, BCl 3etc. p-type impurity source.
The step forming superstructure also can comprise: the step of evaporation tungsten according to chemical vapour deposition (CVD).Tungsten evaporation according to chemical vapour deposition (CVD) can utilize WF 6/ H 2mist and generating.WF 6can reduce according to silica gel, hydrogen and silane (silane), if contact with silica gel, selective reaction from the reduction reaction of silica gel.Hydrogen reduction reaction by forming plug-in unit on karyogenesis layer evaporation tungsten rapidly, silane (silane) reduction reaction have sooner evaporation rate and obtaining than tungsten crystal grain size less in hydrogen reduction reaction.Good according to stepcoverage (step coverage) characteristic of the W film of this reaction formation, compare other materials, resistance components is low, can be utilized as important conductor material.
With reference to Figure 10 to Figure 11, a part for the amorphous carbon film 16 be mixed between lower electrode 14 and upper electrode 20 can be eliminated and form amorphous carbon film pattern 16b.The technique eliminating a part for amorphous carbon film 16 can at least one in superstructure, such as, eliminates, can utilize Wet-type etching and/or dry-etching after forming the 2nd substrate 18a.Such as, one in dry-etching mode can be utilized to be oxygen O 2plasma (Plasma) and optionally eliminate the part of amorphous carbon film 16.If utilize oxygen O 2plasma (Plasma), and between a greater variety of inorganic matter, there is outstanding etching selectivity, also easily adjust film thickness.Therefore, lower electrode 14 is easy to adjust the isolation distance between upper electrode 20, is easy to the uniformity guaranteeing static capacity, can guarantees the stable action of MEMS.
In addition, superstructure, except the 2nd substrate 18a and upper electrode 20, also can comprise solder joints layer 24 and packaging cover layer 26.Packaging cover layer 26 could be adhered on the 2nd substrate 18a, and the inside 28 of packaging cover layer 26 is salable and maintain vacuum, can be mingled with solder joints layer 24 between the 2nd substrate 18a and packaging cover layer 26.The material forming solder joints layer 24 can comprise in gold, silver, copper, tin, indium and silica gel at least more than one and form.Such as, solder joints layer 24 can be made up of the solder alloy of the multiple binary systems such as copper/tin, gold/indium, gold/tin, gold/silica gel, copper/gold/tin or ternary system.
As previously mentioned, MEMS according to technological thought of the present invention forms amorphous carbon film pattern on silica gel substrate as sacrifice layer, the tungsten evaporation process according to chemical vapour deposition (CVD) can be used, stepcoverage (Step Coverage) is outstanding, can be produced on the outstanding device of the apperance of distribution or electrical characteristic aspect.Further, realize technique in the temperature identical with technique after semiconductor, the technology used in semiconductor technology in the past can be made full use of.
The present invention is with reference to being illustrated with illustrated embodiment in accompanying drawing, but this is exemplary, and the people in the art with general knowledge can understand other embodiments can carrying out various deformation and equalization thus.Therefore, real technical protection scope of the present invention should specify according to the technological thought of Patent right requirement scope.

Claims (12)

1. a MEMS manufacture method, is characterized in that, comprises, following steps:
Form the step of substructure thing;
As sacrifice layer, described substructure thing forms the step of amorphous carbon film;
Described amorphous carbon film is formed the step of insulating support layer;
Described insulating support layer forms etching protective film, once etches described insulating support layer and described amorphous carbon film, through described insulating support layer and described amorphous carbon film and form the step of the multiple vias exposing described substructure thing;
Described insulating support layer is formed the step comprising the superstructure of sensor construction;
Form the step of at least one through hole of through described insulating support layer; And
Eliminate whole described amorphous carbon film by described multiple through hole, make the step that described substructure thing and described superstructure are arranged mutually isolatedly.
2. MEMS manufacture method according to claim 1, is characterized in that,
Form the step of described amorphous carbon film, utilize chemical vapour deposition technique (CVD) to realize.
3. MEMS manufacture method according to claim 2, is characterized in that,
The temperature performing described chemical vapour deposition (CVD) is 200 DEG C to 600 DEG C.
4. MEMS manufacture method according to claim 1, is characterized in that,
The step eliminating described amorphous carbon film comprises dry-etching mode.
5. MEMS manufacture method according to claim 4, is characterized in that,
Described dry-etching mode utilizes oxygen O 2plasma (Plasma) and realizing.
6. MEMS manufacture method according to claim 1, is characterized in that,
The step of described formation superstructure, also comprises: the step forming insulating support layer on described amorphous carbon film.
7. MEMS manufacture method according to claim 1, is characterized in that,
After the step of the multiple via of described formation, also comprise: on described multiple lower electrode, form multiple metal anchors and make the step that it is connected with described multiple lower electrode by described multiple via.
8. MEMS manufacture method according to claim 6, is characterized in that,
The step of described formation superstructure, also comprises: the step forming absorbed layer on described insulating support layer.
9. MEMS manufacture method according to claim 1, is characterized in that,
Described substructure thing, comprising: for controlling the readable integrated circuit (ROIC) of described sensor construction.
10. MEMS manufacture method according to claim 8, is characterized in that,
Described sensor construction comprises infrared ray sensor.
11. MEMS manufacture methods according to claim 1, is characterized in that,
The thickness of described sacrifice layer is 0.5 to 5 μm of scope.
12. MEMS manufacture methods according to claim 1, is characterized in that,
Described through described insulating support layer and described amorphous carbon film and form the step of the multiple vias exposing described substructure thing, realize by a photoetching process.
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