CN102180441A - Micro electromechanical device and manufacturing method thereof - Google Patents
Micro electromechanical device and manufacturing method thereof Download PDFInfo
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- CN102180441A CN102180441A CN 201110082536 CN201110082536A CN102180441A CN 102180441 A CN102180441 A CN 102180441A CN 201110082536 CN201110082536 CN 201110082536 CN 201110082536 A CN201110082536 A CN 201110082536A CN 102180441 A CN102180441 A CN 102180441A
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Abstract
The invention provides a micro electromechanical device and a manufacturing method thereof. The manufacturing method comprises the following steps of: providing a base plate and a semiconductor substrate, wherein a control circuit is formed on the semiconductor substrate; forming a base plate sacrificial layer on the base plate; forming a semiconductor material layer on the base plate sacrificial layer; forming an interlayer dielectric layer covering the control circuit on the semiconductor substrate, wherein an interconnection structure electrically connected with the control circuit is formed on the interlayer dielectric layer; performing a bonding process to bond the interlayer dielectric layer and the semiconductor material layer together; removing the base plate sacrificial layer, and separating the base plate and the semiconductor material layer; and manufacturing the micro electromechanical device electrically connected with the interconnection structure on the semiconductor substrate by using the semiconductor material layer. The embodiment of the invention improves the integration level of the micro electromechanical device to meet the requirement on portability in application.
Description
Technical field
The embodiment of the invention relates to technical field of semiconductors, particularly microelectromechanicdevices devices and preparation method thereof.
Background technology
MEMS (Micro Electro Mechanical System, microelectromechanicdevices devices) technology is meant the technology that micrometer/nanometer (micro/nanotechnology) material is designed, processes, makes, measures and controls.MEMS is the microsystem that is integrated into an integral unit by mechanical component, optical system, driver part, electric-control system.The MEMS technology is applied in the making of micro electro mechanical device usually, and described micro electro mechanical device comprises: position sensor, whirligig or inertial sensor, described inertial sensor is acceleration transducer, gyroscope and sound transducer for example.
Prior art utilizes the MEMS technology to make micro electro mechanical device on a Semiconductor substrate, utilize the CMOS technology on second half conductive substrate, to make control circuit then, utilize lead frame (Leadframe) that control circuit is electrically connected with micro electro mechanical device then, thereby form microelectromechanicdevices devices.Therefore, existing microelectromechanicdevices devices need utilize two semiconductor chip fabrication, thereby makes that the cost of existing microelectromechanicdevices devices is higher.Usually, the Semiconductor substrate that contains control circuit is to be arranged in side by side in the lead frame with the Semiconductor substrate that is formed with micro electro mechanical device, and therefore, the volume of existing microelectromechanicdevices devices is bigger, thereby the integrated level of microelectromechanicdevices devices is not high, can't satisfy requirement portable in the application.
In being the Chinese patent application of CN1935630A, publication number can also find more information about existing microelectromechanicdevices devices.
Summary of the invention
The problem that the embodiment of the invention solves has provided a kind of microelectromechanicdevices devices, has improved the integrated level of microelectromechanicdevices devices, has reduced the integrated level of microelectromechanicdevices devices, has satisfied the requirement of portability in using.
For addressing the above problem, the embodiment of the invention provides a kind of preparation method of microelectromechanicdevices devices, comprising:
Substrate and Semiconductor substrate are provided, are formed with control circuit on the described Semiconductor substrate;
On described substrate, form the substrate sacrifice layer;
On described substrate sacrifice layer, form semiconductor material layer;
Form the interlayer dielectric layer that covers described control circuit on described Semiconductor substrate, be formed with interconnection structure in the described interlayer dielectric layer, described interconnection structure is electrically connected with described control circuit;
Carry out bonding technology, described interlayer dielectric layer and semiconductor material layer are bonded together;
Remove described substrate sacrifice layer, described substrate is separated with described semiconductor material layer;
Utilize described semiconductor material layer to make micro electro mechanical device on described Semiconductor substrate, described micro electro mechanical device is electrically connected with above-mentioned control circuit by described interconnection structure.
Alternatively, described semiconductor material layer is any one in polysilicon layer, amorphous silicon layer, SiGe layer, germanium layer or its combination.
Alternatively, the material of described substrate sacrifice layer is an amorphous carbon, and the removal method of described substrate sacrifice layer is to utilize the plasma of oxonium ion to carry out cineration technics, and the temperature range of described cineration technics is 150～450 degrees centigrade.
Alternatively, described bonding technology is anode linkage or Direct Bonding.
Alternatively, described anode linkage technology comprises:
Described substrate and Semiconductor substrate are positioned in the electric field, and described semiconductor material layer and described interlayer dielectric layer are over against setting;
Described substrate and Semiconductor substrate are heated.
Alternatively, the material of described substrate sacrifice layer and substrate sacrifice layer is an amorphous carbon, and described Direct Bonding technology comprises:
Described semiconductor material layer and interlayer dielectric layer are carried out flatening process;
Semiconductor material layer behind the flatening process and interlayer dielectric layer are carried out cleaning surfaces;
Adopt the surface of hydrionic plasma-activated described semiconductor material layer and interlayer dielectric layer;
Over against placement, make described substrate and Semiconductor substrate overlap described semiconductor material layer and interlayer dielectric layer;
Described substrate and Semiconductor substrate be positioned in 150～600 degrees centigrade the hot environment heat treatment 5～30 hours.
Alternatively, the preparation method of described interlayer dielectric layer comprises:
On described Semiconductor substrate, form first dielectric layer;
Form interconnection structure in described first dielectric layer, described interconnection structure is electrically connected with described control circuit;
Form second dielectric layer on described first dielectric layer, described second dielectric layer and first dielectric layer constitute described interlayer dielectric layer;
Form the substrate sacrifice layer in described second dielectric layer, the position of described substrate sacrifice layer is corresponding with the position of described interconnection structure.
Alternatively, the preparation method of described micro electro mechanical device comprises:
The described semiconductor material layer of etching forms movable electrode, is formed with through hole in the described movable electrode, and described through hole exposes the substrate sacrifice layer of below;
Utilize described through hole to remove described substrate sacrifice layer, form cavity in described second dielectric layer, described movable electrode is suspended on the described cavity.
Alternatively, before forming the substrate sacrifice layer on the described substrate, also comprise:
Form the step of first cushion on described substrate, described first cushion is used to reduce the stress between described substrate and the described substrate sacrifice layer.
Alternatively, after described substrate sacrifice layer forms, also comprise: form the step of second cushion on described substrate sacrifice layer, described second cushion is used to reduce the stress between described substrate sacrifice layer and the described semiconductor material layer.
Alternatively, before carrying out bonding technology, also comprise:
Make the step of three buffer layer on described interlayer dielectric layer, described three buffer layer is used to reduce the stress between described semiconductor material layer and the described interlayer dielectric layer.
Alternatively, the material of described first cushion, second cushion and three buffer layer is the insulation material, and described insulation material is silica or silicon oxynitride.
Correspondingly, the present invention also provides a kind of microelectromechanicdevices devices, comprising:
Semiconductor substrate is formed with control circuit in the described Semiconductor substrate;
Interlayer dielectric layer is positioned on the described Semiconductor substrate;
Interconnection structure is positioned at described interlayer dielectric layer, and described interconnection structure is electrically connected with described control circuit;
Cavity is positioned at described interlayer dielectric layer, and the position of described cavity is corresponding with the position of described interconnection structure;
Movable electrode, an end of described movable electrode is electrically connected with described interconnection structure, and the described movable electrode other end is suspended on the cavity, and the material of described movable electrode is a semiconductor material.
Alternatively, described semiconductor material layer is any one in polysilicon layer, amorphous silicon layer, SiGe layer, germanium layer or its combination.
Compared with prior art, the embodiment of the invention has the following advantages:
The embodiment of the invention will be formed at semiconductor material layer on the substrate by bonding technology and the interlayer dielectric layer on the Semiconductor substrate is bonded together, then by the substrate sacrifice layer between substrate and the semiconductor material layer is removed, thereby described semiconductor material layer and interlayer dielectric layer are bonded together, described substrate is separated with described Semiconductor substrate; Then, utilize described semiconductor material layer to make micro electro mechanical device, thereby on described Semiconductor substrate, make micro electro mechanical device, the preparation method of the microelectromechanicdevices devices of prior art is: two Semiconductor substrate are provided, utilize a Semiconductor substrate to make micro electro mechanical device, utilize another semiconductor fabrication control circuit, described two Semiconductor substrate are listed in the same lead frame, the volume of the microelectromechanicdevices devices of prior art is bigger, compared with prior art, the embodiment of the invention is integrated in micro electro mechanical device and control circuit with on the semi-conductive substrate, not only reduced the cost of manufacture of microelectromechanicdevices devices, and reduced the volume of microelectromechanicdevices devices, improved the integrated level of microelectromechanicdevices devices, thus satisfied use in portable requirement.
Description of drawings
Fig. 1 is the microelectromechanicdevices devices preparation method schematic flow sheet of the embodiment of the invention;
Fig. 2～Fig. 7 is the preparation method cross-sectional view of the microelectromechanicdevices devices of one embodiment of the invention.
The specific embodiment
The microelectromechanicdevices devices of prior art adopts two Semiconductor substrate to make, one of them Semiconductor substrate is used to make control circuit, another Semiconductor substrate is used to make micro electro mechanical device, be arranged in two Semiconductor substrate in the lead frame side by side then, therefore, the volume of existing microelectromechanicdevices devices is bigger, thereby the integrated level of microelectromechanicdevices devices is not high, can't satisfy requirement portable in the application.And prior art utilizes two Semiconductor substrate to make a microelectromechanicdevices devices, and cost is higher.
Because the material of the movable electrode of micro electro mechanical device is generally semiconductor material layer, described semiconductor material layer can be polysilicon layer, described polysilicon layer utilizes chemical vapor deposition method to make usually, the temperature of described chemical vapor deposition method is a high temperature, described high temperature is greater than 500 degrees centigrade, described high temperature can influence the interconnection structure on the Semiconductor substrate, therefore, can not directly be formed with deposit spathic silicon layer on the Semiconductor substrate of interconnection structure.
Therefore, the inventor considers to provide a substrate that is formed with semiconductor material layer, described semiconductor material layer can be amorphous silicon layer, polysilicon layer, the SiGe layer, in germanium layer or its combination any one, then with the semiconductor material layer of this substrate and the Semiconductor substrate bonding that is formed with control circuit, then described substrate is removed (being about to described substrate separates with described semiconductor material layer) from semiconductor material layer, make described semiconductor material layer be transferred to Semiconductor substrate, utilize described semiconductor material layer to make micro electro mechanical device then, thereby micro electro mechanical device and control circuit are integrated in on the semi-conductive substrate, not only saved a Semiconductor substrate, reduced the cost of manufacture of microelectromechanicdevices devices, but also can improve the integrated level of microelectromechanicdevices devices, improved the portability of microelectromechanicdevices devices.
The present invention considers to utilize silicon-on-insulator substrate (SOI substrate, comprise silicon substrate, be positioned at the insulating barrier of silicon substrate and be positioned at silicon layer on the described insulating barrier) as described substrate, with described silicon-on-insulator substrate and the Semiconductor substrate bonding that is formed with control circuit, then silicon substrate is separated with described silicon layer with insulating barrier, described silicon layer is transferred on the Semiconductor substrate, thereby micro electro mechanical device and silicon substrate can be integrated in on the semi-conductive substrate, thereby the integrated level of raising microelectromechanicdevices devices.But the price of silicon-on-insulator substrate is expensive partially, makes that the cost of microelectromechanicdevices devices is higher.
In order to address the above problem, the invention provides a kind of preparation method of microelectromechanicdevices devices, please refer to the preparation method schematic flow sheet of microelectromechanicdevices devices of the present invention shown in Figure 1, described method comprises:
Step S1 provides substrate and Semiconductor substrate, is formed with control circuit on the described Semiconductor substrate;
Step S2 forms the substrate sacrifice layer on described substrate;
Step S3 forms semiconductor material layer on described substrate sacrifice layer;
Step S4 forms the interlayer dielectric layer that covers described control circuit on described Semiconductor substrate, be formed with interconnection structure in the described interlayer dielectric layer, and described interconnection structure is electrically connected with described control circuit;
Step S5 carries out bonding technology, and described interlayer dielectric layer and semiconductor material layer are bonded together;
Step S6 removes described substrate sacrifice layer, and described substrate is separated with described semiconductor material layer;
Step S7 utilizes described semiconductor material layer to make micro electro mechanical device on described Semiconductor substrate, and described micro electro mechanical device is electrically connected with above-mentioned control circuit by described interconnection structure.
Below in conjunction with specific embodiment technical scheme of the present invention is described in detail.For technical scheme of the present invention is described better, please in conjunction with the preparation method cross-sectional view of the microelectromechanicdevices devices of the one embodiment of the invention of Fig. 2～shown in Figure 7.
At first, please refer to Fig. 2, substrate 200 is provided, the material of described substrate 200 can be semiconductor material, and described semiconductor material can be silicon or germanium silicon etc.Described substrate 200 is used to provide platform, makes substrate sacrifice layer and semiconductor material layer in follow-up processing step.
Then, please continue with reference to figure 2, form first cushion 201 on described substrate 200, described first cushion 201 is used to reduce the stress between the substrate sacrifice layer of described substrate 200 and follow-up formation.The thickness range of described first cushion 201 is 20～5000 dusts.The material of described first cushion 201 is the insulation material, and for example described insulation material can be silica or silicon oxynitride.As another embodiment of the present invention, also can on described substrate 200, not form described cushion 201, directly carry out follow-up step, promptly directly on described substrate, form the substrate sacrifice layer.
Then, please continue, on described first cushion 201, form substrate sacrifice layer 202 with reference to figure 2.To in follow-up step, form semiconductor material layer on the described substrate sacrifice layer 202, in follow-up processing step, described semiconductor material layer can be separated with described substrate 200 by removing described substrate sacrifice layer 202.
The material of described substrate sacrifice layer 202 should be selected the material that is easy to remove.Damage semiconductor material layer when preventing to remove described substrate sacrifice layer 202, the material of described substrate sacrifice layer 202 should select to have with described semiconductor material layer the material of big etching selection ratio.The described described substrate sacrifice layer 202 of the embodiment of the invention has big etching selection ratio with described semiconductor material layer, be meant when the etching technics that utilizes the embodiment of the invention is removed described substrate sacrifice layer 202, the etch rate of described substrate sacrifice layer 202 is much larger than the etch rate of described semiconductor material layer, such as, the etch rate of described substrate sacrifice layer 202 can be more than 3 times of etch rate of described semiconductor material layer.
As an embodiment, the material of described substrate sacrifice layer 202 is an amorphous carbon, and its thickness range is 1000～10000 dusts.Described amorphous carbon can utilize the cineration technics of the plasma of oxonium ion to remove, and the temperature range of described cineration technics is preferably 150～450 degrees centigrade, so can residual described substrate sacrifice layer 202 on, can not damage semiconductor material layer yet.In another embodiment, described substrate sacrifice layer can also be photoresist layer or other sacrificial layer material.Need to prove, if the material of described substrate sacrifice layer is a photoresist layer, the temperature of the technology of the described semiconductor material layer of follow-up formation should be not too high, in the present embodiment, the temperature that forms the technology of described semiconductor material layer should not surpass 150 degrees centigrade, in order to avoid described photoresist layer is burnt.
As an embodiment, the preparation method of described substrate sacrifice layer 202 is plasma enhanced chemical vapor deposition (PECVD) technology.The parameter of described plasma reinforced chemical vapour deposition technology is: temperature range is 250 ℃～500 ℃, air pressure range is 1torr～20torr, the RF power bracket is 800W～2000W, reacting gas comprises: C3H6 and HE, reaction gas flow is that the volume ratio scope of 1000sccm～5000sccm, wherein C3H6: HE is 2: 1～10: 1.
As optional embodiment of the present invention, after described substrate sacrifice layer 202 forms, form second cushion 203 on described substrate sacrifice layer 202, described second cushion 203 is used to cushion the stress between the semiconductor material layer of described substrate sacrifice layer 202 and follow-up formation.The material of described second cushion 203 is the insulation material, and for example described insulation material can be silica or silicon oxynitride.The thickness range of described second cushion 203 is 20～5000 dusts.In another embodiment, can there be this second cushion yet.
Then, please continue with reference to figure 2, on described second cushion 203, make semiconductor material layer 204, described semiconductor material layer 204 will combine with the Semiconductor substrate that is formed with control circuit by bonding technology, and in follow-up processing step, described semiconductor material layer 204 will be used to make the movable electrode of micro electro mechanical device.The material of described semiconductor material layer 204 should be selected semiconductor material, and for example described semiconductor material layer 204 can be in amorphous silicon layer, polysilicon layer, germanium silicon compound layer, germanium layer or its combination any one.
As an embodiment, described semiconductor material layer 204 utilizes chemical vapor deposition method to make.The temperature of described chemical vapor deposition method is not less than 500 degrees centigrade.The thickness range of described semiconductor material layer 204 is 0.5～50 micron.
Then, please refer to Fig. 3, Semiconductor substrate 100 is provided, the material of described Semiconductor substrate 100 is a semiconductor material, and the material of described Semiconductor substrate 100 can be silicon or germanium silicon.Also be formed with the control circuit (not shown) in the described Semiconductor substrate 100.Described control circuit can utilize cmos process flow to make.Described control circuit can be used for providing control signal to the micro electro mechanical device of follow-up formation.
Then, please continue with reference to figure 3, on described Semiconductor substrate 100, form first dielectric layer 101, be formed with interconnection structure in described first dielectric layer 101, described interconnection structure comprises first conductive plunger 102 that is electrically connected with described control circuit and the interconnection line 103 that is electrically connected with described first conductive plunger 102.The material of described first dielectric layer 101 is silica or silicon oxynitride, and described first dielectric layer 101 can utilize oxidation technology or chemical vapor deposition method to make.
Then, please continue, on described first dielectric layer 101, form second dielectric layer 104, described second dielectric layer 104 and first dielectric layer, 101 common formation interlayer dielectric layers with reference to figure 3.The material of described second dielectric layer 104 is silica or silicon nitride, and described second dielectric layer 104 can utilize oxidation technology or chemical vapor deposition method to make.
Then, form groove in described second dielectric layer 104, described groove exposes first dielectric layer 101 of below, and the position of described groove is corresponding with the position of described interconnection structure.The position of groove of the present invention is corresponding with the position of described interconnection structure, and described groove is on second dielectric layer between the adjacent interconnection structure.
Need to prove, as another embodiment of the present invention, one deck interlayer dielectric layer be can also only on described Semiconductor substrate 100, form, interconnection structure that is electrically connected with described control circuit and the described groove that is filled with sacrifice layer in described interlayer dielectric layer, formed then respectively.The position of described groove is corresponding with the position of described interconnection structure.
Then, in described groove, form substrate sacrifice layer 105, described substrate sacrifice layer 105 is used at follow-up step and semiconductor material layer 204 bondings that are positioned on the described substrate 200, after described semiconductor material layer 204 was made into to movable electrode, described substrate sacrifice layer 105 finally will be removed.
Described second dielectric layer 104 is caused damage when preventing to remove described substrate sacrifice layer 105, the material of described substrate sacrifice layer 105 should select to have with described second dielectric layer 104 material of big etching selection ratio.The described described substrate sacrifice layer 10 of the embodiment of the invention has big etching selection ratio with described second dielectric layer 104, be meant when the etching technics that utilizes the embodiment of the invention is removed described substrate sacrifice layer 105, the etch rate of described substrate sacrifice layer 105 is much larger than the etch rate of described second dielectric layer 104, such as, the etch rate of described substrate sacrifice layer 105 can be more than 3 times of etch rate of described second dielectric layer 104.
As an embodiment, the material of described substrate sacrifice layer 105 is an amorphous carbon, and it can utilize enhancement mode plasma activated chemical vapour deposition technology to make.Concrete parameter please refer to the method that the present invention makes substrate sacrifice layer 202, does not do at this and gives unnecessary details.As another embodiment of the present invention, the material of described substrate sacrifice layer 105 can also be easy to the sacrificial layer material removed by cineration technics or wet-etching technology for photoresist or other.As an embodiment, when the material of described substrate sacrifice layer 105 was photoresist layer, the temperature of follow-up bonding technology was unsuitable too high, and the temperature of for example follow-up bonding technology is no more than 150 degrees centigrade, in order to avoid photoresist is burnt.
Because in the subsequent step, to carry out bonding technology, thereby described second dielectric layer 104 will be bonded together with described semiconductor material layer 204 (combining Fig. 2), and the substrate sacrifice layer 105 in described second dielectric layer 104 also will be bonded together with described semiconductor material layer 204.Because the material of substrate sacrifice layer 105 is an amorphous carbon, the material of described semiconductor material layer 204 is a silicon, there is stress between the two, described stress can influence the reliability of the bonding of the described semiconductor material layer 204 and second dielectric layer 104, make described semiconductor material layer 204 to come off from described second dielectric layer 104, therefore, in order to improve the reliability of the bonding between described semiconductor material layer 204 and the substrate sacrifice layer 105.
As an optional embodiment of the present invention, after described substrate sacrifice layer 105 forms, also on described second dielectric layer 104, form three buffer layer 106.The material of described three buffer layer 106 can be silica or silicon oxynitride.The thickness range of described three buffer layer 106 is 20～5000 dusts, and described three buffer layer 106 can utilize chemical vapor deposition method to make.Certainly can there be this three buffer layer in other embodiments yet.
Then, please refer to Fig. 4, carry out bonding technology, described three buffer layer 106 and semiconductor material layer 204 are bonded together, make described substrate 200, be positioned at first cushion 201 on the substrate 200, substrate sacrifice layer 202, second cushion 203 and described Semiconductor substrate 100, first dielectric layer 101, second dielectric layer 104 that are positioned on the described Semiconductor substrate 100 form whole.Above-mentioned bonding technology forms firm bonding face between described three buffer layer 106 described semiconductor material layers 204.
Described bonding technology can be anode linkage technology or Direct Bonding technology.
As an embodiment, described bonding technology is an anode linkage technology.The method of described anode linkage technology comprises:
At first, surface having an even surface processing to described three buffer layer 106 surfaces and semiconductor material layer 204, make the having an even surface of described three buffer layer 106 and semiconductor material layer 204, to improve the reliability of the bonding between described three buffer layer 106 and the semiconductor material layer 204.Described planarization is a chemical mechanical milling tech.
Then, described substrate 200 and Semiconductor substrate 100 are positioned in the electric field, described semiconductor material layer 204 and described three buffer layer 106 apply negative voltage over against setting on the wherein said substrate 200, add positive voltage on the described Semiconductor substrate 100.As an embodiment, the voltage of described electric field is higher than 500V.Under the described electric field action, the alkaline metal ions on described semiconductor material layer 204 surfaces for example sodium ion and potassium ion moves to the direction of substrate 200 under the effect of negative voltage, thereby the surface at described semiconductor material layer 204 forms anion (this anion is a silicon ion), the direction of positive charge Semiconductor substrate 100 under the effect of the positive voltage on the described substrate 200 on described three buffer layer 106 surfaces moves, thereby the surface at described three buffer layer 106 forms cation (this cation is an oxonium ion), negatron (the being silicon ion) charge neutrality on the cation (being oxonium ion) on described three buffer layer 106 surfaces and described semiconductor material layer 204 surfaces, and formation silica, thereby described three buffer layer 106 and described semiconductor material layer 204 bondings.
When being positioned over described substrate 200 and Semiconductor substrate 100 in the electric field, also need described substrate 200 and Semiconductor substrate 100 are heated, make the temperature of described substrate 200 and Semiconductor substrate 100 between 200～400 degrees centigrade, described heating more helps improving the bond strength between three buffer layer 106 and the described semiconductor material layer 204.
Need to prove that when the material of described substrate sacrifice layer 102 and substrate sacrifice layer 202 was photoresist layer, the temperature of described anode linkage technology should be not too high, the temperature of for example described anode linkage technology should not surpass 150 degrees centigrade, in order to avoid photoresist is burnt.Certainly, described substrate sacrifice layer 102 and substrate sacrifice layer 202 can bear the material of high temperature for amorphous carbon etc., the temperature of described anode linkage technology can be higher than 150 degrees centigrade, and the temperature of for example described anode linkage technology can be aforesaid 200～400 degrees centigrade.
As another embodiment of the present invention, the material of described substrate sacrifice layer 202 and substrate sacrifice layer 102 is an amorphous carbon, and described Direct Bonding technology comprises:
Flatening process is carried out on surface to described semiconductor material layer 204 and three buffer layer 106, described flatening process is a chemical mechanical milling tech, and described flatening process helps improving the bond strength between described semiconductor material layer 204 and the three buffer layer 106;
Semiconductor material layer behind the flatening process 204 and three buffer layer 106 are carried out cleaning surfaces, described cleaning surfaces is removed the pollutant on described semiconductor material layer 204 and three buffer layer 106 surfaces, prevents the bond strength between described pollutant effect semiconductor material layer 204 and the three buffer layer 106;
Adopt the surface of hydrionic plasma-activated described semiconductor material layer 204 and three buffer layer 106, follow-up to help strengthening with the bond strength between described semiconductor material layer 204 and the three buffer layer 106;
Over against placement, make described substrate 200 and Semiconductor substrate 100 overlap the semiconductor material layer after the described activation processing 204 and three buffer layer 106;
Described substrate 200 and Semiconductor substrate 100 are positioned in the hot environment, heat treatment 5～30 hours, described hot environment is 150～600 degrees centigrade, for example described hot environment can be 300～450 degrees centigrade;
In the heat treated while, apply certain pressure on described substrate 200 and the Semiconductor substrate 100, more to help improving the bond strength between described semiconductor material layer 204 and the three buffer layer 106, described pressure limit is 7600～50000 holders.
The material that above-mentioned Direct Bonding technology is applicable to substrate sacrifice layer 202 and substrate sacrifice layer 102 is situation (for example the material of substrate sacrifice layer 202 and substrate sacrifice layer 102 is an amorphous carbon) that can withstand high temperatures, if the material of described substrate sacrifice layer 202 and substrate sacrifice layer 102 is a photoresist, the temperature of then described Direct Bonding technology should not surpass 150 degrees centigrade, in order to avoid photoresist is burnt.
Then, please refer to Fig. 5, remove described substrate sacrifice layer 202 (being represented by dotted lines in the drawings), the described substrate 200 and first cushion 201 are removed from 204 layers of described semiconductor material layers and Semiconductor substrate 100, described second cushion 203 also is retained on the described semiconductor material layer 204.Described substrate sacrifice layer 202 utilizes the plasma of oxonium ion to carry out cineration technics and removes.As an embodiment, the parameter of described cineration technics is: described removal material is an oxygen, the plasma that produces is an oxonium ion, the temperature range of described etching technics is 150 ℃～450 ℃, under this temperature, violent burning can't take place in fine and close amorphous carbon, and can be oxidized to carbon dioxide, first sacrifice layer 113 can be removed up hill and dale, and the remainder of device can't be affected.
Through above-mentioned steps, semiconductor material layer 204 is transferred on the Semiconductor substrate from substrate 200, thereby described substrate 200 can reuse, and has further saved cost.
Then, need utilize described semiconductor material layer 204 on described Semiconductor substrate 200, to make micro electro mechanical device.The manufacturing process of described micro electro mechanical device need form cavity on Semiconductor substrate 200, make movable electrode then on cavity, and described movable electrode can carry out relative motion with described cavity.
Particularly, please refer to Fig. 6, the three buffer layer 106 of described second cushion 203 of etching and semiconductor material layer 204 and below, form movable electrode 207, the present invention simultaneously forms through hole 205 in described movable electrode 207 and three buffer layer 106, described through hole 205 exposes the substrate sacrifice layer 105 of below.Described through hole 205 is used to remove the inlet of described substrate sacrifice layer 105.
Need to prove that the part movable electrode 207 between adjacent through hole 205 is the structure of one with the movable electrode 207 of remainder.
Then, please continue with reference to figure 6, make conductive plunger 206, described conductive plunger 206 is electrically connected with the interconnection line 103 of described interconnection structure, and described conduction difference connector 206 is positioned at outside the substrate sacrifice layer 105.
Then, please refer to Fig. 7, utilize described through hole 205 to remove described substrate sacrifice layer, in described second dielectric layer 104, form cavity, described movable electrode 207 is suspended on the described cavity, and described movable electrode 207 can carry out relative motion with described cavity, and described movable electrode 207 constitutes micro electro mechanical device with described cavity.Described micro electro mechanical device can contain the MEMS device of movable electrode and cavity for gyroscope, acceleration transducer, microphone, optical modulator, crystal oscillator etc.The removal method of described substrate sacrifice layer please refer to the removal method of described substrate sacrifice layer, does not elaborate at this.
Through above-mentioned processing step, form microelectromechanicdevices devices of the present invention, microelectromechanicdevices devices of the present invention can be for containing gyroscope, acceleration transducer, microphone, optical modulator, crystal oscillator etc.Please refer to Fig. 7, described microelectromechanicdevices devices comprises:
First dielectric layer 101 is positioned on the described Semiconductor substrate 100;
Interconnection structure is positioned at described first dielectric layer 101, and described interconnection structure is electrically connected with described control circuit, and described interconnection structure comprises conductive plunger 102 that is electrically connected with described control circuit and the interconnection line 103 that is electrically connected with described conductive plunger 102;
To sum up, the present invention will be formed at semiconductor material layer on the substrate by bonding technology and the interlayer dielectric layer on the Semiconductor substrate is bonded together, then by the substrate sacrifice layer between substrate and the semiconductor material layer is removed, thereby described semiconductor material layer and interlayer dielectric layer are bonded together, described substrate is separated with described Semiconductor substrate; Then, utilize described semiconductor material layer to make micro electro mechanical device, thereby on described Semiconductor substrate, make micro electro mechanical device, the preparation method of the microelectromechanicdevices devices of prior art is: two Semiconductor substrate are provided, utilize a Semiconductor substrate to make micro electro mechanical device, utilize another semiconductor fabrication control circuit, described two Semiconductor substrate are listed in the same lead frame, the volume of the microelectromechanicdevices devices of prior art is bigger, compared with prior art, the present invention is integrated in micro electro mechanical device and control circuit with on the semi-conductive substrate, not only reduced the cost of manufacture of microelectromechanicdevices devices, and reduced the volume of microelectromechanicdevices devices, improved the integrated level of microelectromechanicdevices devices, thus satisfied use in portable requirement.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (14)
1. the preparation method of a microelectromechanicdevices devices is characterized in that, comprising:
Substrate and Semiconductor substrate are provided, are formed with control circuit on the described Semiconductor substrate;
On described substrate, form the substrate sacrifice layer;
On described substrate sacrifice layer, form semiconductor material layer;
Form the interlayer dielectric layer that covers described control circuit on described Semiconductor substrate, be formed with interconnection structure in the described interlayer dielectric layer, described interconnection structure is electrically connected with described control circuit;
Carry out bonding technology, described interlayer dielectric layer and semiconductor material layer are bonded together;
Remove described substrate sacrifice layer, described substrate is separated with described semiconductor material layer;
Utilize described semiconductor material layer to make micro electro mechanical device on described Semiconductor substrate, described micro electro mechanical device is electrically connected with above-mentioned control circuit by described interconnection structure.
2. the preparation method of microelectromechanicdevices devices as claimed in claim 1 is characterized in that, described semiconductor material layer is any one in polysilicon layer, amorphous silicon layer, germanium silicon compound layer, germanium layer or its combination.
3. the preparation method of microelectromechanicdevices devices as claimed in claim 1, it is characterized in that, the material of described substrate sacrifice layer is an amorphous carbon, and the removal method of described substrate sacrifice layer is to utilize the plasma of oxonium ion to carry out cineration technics, and the temperature range of described cineration technics is 150～450 degrees centigrade.
4. the preparation method of microelectromechanicdevices devices as claimed in claim 1 is characterized in that, described bonding technology is anode linkage or Direct Bonding.
5. the preparation method of microelectromechanicdevices devices as claimed in claim 4 is characterized in that, described anode linkage technology comprises:
Described substrate and Semiconductor substrate are positioned in the electric field, and described semiconductor material layer and described interlayer dielectric layer are over against setting;
Described substrate and Semiconductor substrate are heated.
6. the preparation method of microelectromechanicdevices devices as claimed in claim 4 is characterized in that, the material of described substrate sacrifice layer and substrate sacrifice layer is an amorphous carbon, and described Direct Bonding technology comprises:
Described semiconductor material layer and interlayer dielectric layer are carried out flatening process;
Semiconductor material layer behind the flatening process and interlayer dielectric layer are carried out cleaning surfaces;
Adopt the surface of hydrionic plasma-activated described semiconductor material layer and interlayer dielectric layer;
Over against placement, make described substrate and Semiconductor substrate overlap described semiconductor material layer and interlayer dielectric layer;
Described substrate and Semiconductor substrate be positioned in 150～600 degrees centigrade the hot environment heat treatment 5～30 hours.
7. the preparation method of microelectromechanicdevices devices as claimed in claim 1 is characterized in that, the preparation method of described interlayer dielectric layer comprises:
On described Semiconductor substrate, form first dielectric layer;
Form interconnection structure in described first dielectric layer, described interconnection structure is electrically connected with described control circuit;
Form second dielectric layer on described first dielectric layer, described second dielectric layer and first dielectric layer constitute described interlayer dielectric layer;
Form the substrate sacrifice layer in described second dielectric layer, the position of described substrate sacrifice layer is corresponding with the position of described interconnection structure.
8. the preparation method of microelectromechanicdevices devices as claimed in claim 1 is characterized in that, the preparation method of described micro electro mechanical device comprises:
The described semiconductor material layer of etching forms movable electrode, is formed with through hole in the described movable electrode, and described through hole exposes the substrate sacrifice layer of below;
Utilize described through hole to remove described substrate sacrifice layer, form cavity in described second dielectric layer, described movable electrode is suspended on the described cavity.
9. the preparation method of microelectromechanicdevices devices as claimed in claim 1 is characterized in that, before forming the substrate sacrifice layer on the described substrate, also comprises:
Form the step of first cushion on described substrate, described first cushion is used to reduce the stress between described substrate and the described substrate sacrifice layer.
10. the preparation method of microelectromechanicdevices devices as claimed in claim 9, it is characterized in that, after described substrate sacrifice layer forms, also comprise: form the step of second cushion on described substrate sacrifice layer, described second cushion is used to reduce the stress between described substrate sacrifice layer and the described semiconductor material layer.
11. the preparation method of microelectromechanicdevices devices as claimed in claim 10 is characterized in that, before carrying out bonding technology, also comprises:
Make the step of three buffer layer on described interlayer dielectric layer, described three buffer layer is used to reduce the stress between described semiconductor material layer and the described interlayer dielectric layer.
12. the preparation method of microelectromechanicdevices devices as claimed in claim 11 is characterized in that, the material of described first cushion, second cushion and three buffer layer is the insulation material, and described insulation material is silica or silicon oxynitride.
13. a microelectromechanicdevices devices is characterized in that, comprising:
Semiconductor substrate is formed with control circuit in the described Semiconductor substrate;
Interlayer dielectric layer is positioned on the described Semiconductor substrate;
Interconnection structure is positioned at described interlayer dielectric layer, and described interconnection structure is electrically connected with described control circuit;
Cavity is positioned at described interlayer dielectric layer, and the position of described cavity is corresponding with the position of described interconnection structure;
Movable electrode, an end of described movable electrode is electrically connected with described interconnection structure, and the described movable electrode other end is suspended on the cavity, and the material of described movable electrode is a semiconductor material.
14. microelectromechanicdevices devices as claimed in claim 13 is characterized in that, described semiconductor material layer is any one in polysilicon layer, amorphous silicon layer, germanium silicon compound layer, germanium layer or its combination.
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